vdec.c 75 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/of.h>
  9. #include <linux/pm_runtime.h>
  10. #include <linux/wait.h>
  11. #include <linux/list.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/uaccess.h>
  15. #include <linux/cdev.h>
  16. #include <linux/slab.h>
  17. #include <linux/of_address.h>
  18. #include <linux/sched.h>
  19. #include <linux/sched/signal.h>
  20. #include <linux/version.h>
  21. #include <linux/kfifo.h>
  22. #include <linux/kthread.h>
  23. #include <linux/reset.h>
  24. #include <asm/io.h>
  25. #include <soc/sifive/sifive_l2_cache.h>
  26. #include "../../../vpuapi/vpuconfig.h"
  27. #include "vpu.h"
  28. //#define ENABLE_DEBUG_MSG
  29. #ifdef ENABLE_DEBUG_MSG
  30. #define DPRINTK(args...) printk(KERN_INFO args);
  31. #else
  32. #define DPRINTK(args...)
  33. #endif
  34. /* definitions to be changed as customer configuration */
  35. /* if you want to have clock gating scheme frame by frame */
  36. /* #define VPU_SUPPORT_CLOCK_CONTROL */
  37. /* if the driver want to use interrupt service from kernel ISR */
  38. #define VPU_SUPPORT_ISR
  39. #ifdef VPU_SUPPORT_ISR
  40. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  41. //#define VPU_IRQ_CONTROL
  42. #endif
  43. #define VPU_SUPPORT_CLOCK_CONTROL
  44. /* if clktree is work,try this...*/
  45. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  46. /* if the platform driver knows the name of this driver */
  47. /* VPU_PLATFORM_DEVICE_NAME */
  48. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  49. /* if this driver knows the dedicated video memory address */
  50. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  51. static void starfive_flush_dcache(unsigned long start, unsigned long len)
  52. {
  53. sifive_l2_flush64_range(start, len);
  54. }
  55. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  56. #define VPU_CLK_NAME "vcodec"
  57. #define VPU_DEV_NAME "vdec"
  58. /* if the platform driver knows this driver */
  59. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  60. #define VPU_REG_BASE_ADDR 0x118F0000
  61. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  62. #ifdef VPU_SUPPORT_ISR
  63. #define VPU_IRQ_NUM (23)
  64. #endif
  65. /* this definition is only for chipsnmedia FPGA board env */
  66. /* so for SOC env of customers can be ignored */
  67. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  68. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  69. #endif
  70. struct device *vpu_dev;
  71. typedef struct vpu_drv_context_t {
  72. struct fasync_struct *async_queue;
  73. #ifdef SUPPORT_MULTI_INST_INTR
  74. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  75. #else
  76. unsigned long interrupt_reason;
  77. #endif
  78. u32 open_count; /*!<< device reference count. Not instance count */
  79. } vpu_drv_context_t;
  80. /* To track the allocated memory buffer */
  81. typedef struct vpudrv_buffer_pool_t {
  82. struct list_head list;
  83. struct vpudrv_buffer_t vb;
  84. struct file *filp;
  85. } vpudrv_buffer_pool_t;
  86. /* To track the instance index and buffer in instance pool */
  87. typedef struct vpudrv_instanace_list_t {
  88. struct list_head list;
  89. unsigned long inst_idx;
  90. unsigned long core_idx;
  91. struct file *filp;
  92. } vpudrv_instanace_list_t;
  93. typedef struct vpudrv_instance_pool_t {
  94. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  95. } vpudrv_instance_pool_t;
  96. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  97. typedef struct vpu_clkgen_t {
  98. void __iomem *en_ctrl;
  99. uint32_t rst_mask;
  100. } vpu_clkgen_t;
  101. #endif
  102. struct clk_bulk_data vpu_clks[] = {
  103. { .id = "apb_clk" },
  104. { .id = "axi_clk" },
  105. { .id = "bpu_clk" },
  106. { .id = "vce_clk" },
  107. { .id = "noc_bus" },
  108. };
  109. typedef struct vpu_clk_t {
  110. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  111. void __iomem *clkgen;
  112. void __iomem *rst_ctrl;
  113. void __iomem *rst_status;
  114. void __iomem *noc_bus;
  115. uint32_t en_shift;
  116. uint32_t en_mask;
  117. vpu_clkgen_t apb_clk;
  118. vpu_clkgen_t axi_clk;
  119. vpu_clkgen_t bpu_clk;
  120. vpu_clkgen_t vce_clk;
  121. vpu_clkgen_t aximem_128b;
  122. #else
  123. struct clk_bulk_data *clks;
  124. struct reset_control *resets;
  125. int nr_clks;
  126. #endif
  127. struct device *dev;
  128. bool noc_ctrl;
  129. } vpu_clk_t;
  130. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  131. #include "vmm.h"
  132. static video_mm_t s_vmem;
  133. static vpudrv_buffer_t s_video_memory = {0};
  134. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  135. static int vpu_hw_reset(void);
  136. static void vpu_clk_disable(vpu_clk_t *clk);
  137. static int vpu_clk_enable(vpu_clk_t *clk);
  138. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  139. static void vpu_clk_put(vpu_clk_t *clk);
  140. static int vpu_pmu_enable(struct device *dev);
  141. static void vpu_pmu_disable(struct device *dev);
  142. /* end customer definition */
  143. static vpudrv_buffer_t s_instance_pool = {0};
  144. static vpudrv_buffer_t s_common_memory = {0};
  145. static vpu_drv_context_t s_vpu_drv_context;
  146. static int s_vpu_major;
  147. static struct cdev s_vpu_cdev;
  148. static vpu_clk_t *s_vpu_clk;
  149. static int s_vpu_open_ref_count;
  150. #ifdef VPU_SUPPORT_ISR
  151. static int s_vpu_irq = VPU_IRQ_NUM;
  152. #endif
  153. static vpudrv_buffer_t s_vpu_register = {0};
  154. #ifdef SUPPORT_MULTI_INST_INTR
  155. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  156. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  157. typedef struct kfifo kfifo_t;
  158. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  159. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  160. #else
  161. static int s_interrupt_flag;
  162. static wait_queue_head_t s_interrupt_wait_q;
  163. #endif
  164. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  165. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  166. static DECLARE_MUTEX(s_vpu_sem);
  167. #else
  168. static DEFINE_SEMAPHORE(s_vpu_sem);
  169. #endif
  170. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  171. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  172. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  173. //#ifdef CONFIG_PM
  174. /* implement to power management functions */
  175. #define BIT_BASE 0x0000
  176. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  177. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  178. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  179. #define BIT_INT_STS (BIT_BASE + 0x010)
  180. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  181. #define BIT_INT_REASON (BIT_BASE + 0x174)
  182. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  183. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  184. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  185. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  186. /* WAVE5 registers */
  187. #define W5_REG_BASE 0x0000
  188. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  189. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  190. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  191. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  192. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  193. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  194. #ifdef SUPPORT_MULTI_INST_INTR
  195. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  196. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  197. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  198. typedef enum {
  199. INT_WAVE5_INIT_VPU = 0,
  200. INT_WAVE5_WAKEUP_VPU = 1,
  201. INT_WAVE5_SLEEP_VPU = 2,
  202. INT_WAVE5_CREATE_INSTANCE = 3,
  203. INT_WAVE5_FLUSH_INSTANCE = 4,
  204. INT_WAVE5_DESTORY_INSTANCE = 5,
  205. INT_WAVE5_INIT_SEQ = 6,
  206. INT_WAVE5_SET_FRAMEBUF = 7,
  207. INT_WAVE5_DEC_PIC = 8,
  208. INT_WAVE5_ENC_PIC = 8,
  209. INT_WAVE5_ENC_SET_PARAM = 9,
  210. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  211. INT_WAVE5_ENC_SRC_RELEASE = 10,
  212. #endif
  213. INT_WAVE5_ENC_LOW_LATENCY = 13,
  214. INT_WAVE5_DEC_QUERY = 14,
  215. INT_WAVE5_BSBUF_EMPTY = 15,
  216. INT_WAVE5_BSBUF_FULL = 15,
  217. } Wave5InterruptBit;
  218. #endif
  219. /* WAVE5 INIT, WAKEUP */
  220. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  221. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  222. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  223. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  224. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  225. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  226. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  227. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  228. #define W5_REMAP_CODE_INDEX 0
  229. /* WAVE5 registers */
  230. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  231. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  232. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  233. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  234. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  235. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  236. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  237. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  238. /* Product register */
  239. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  240. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  241. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  242. #endif
  243. //#endif //CONFIG_PM
  244. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  245. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  246. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  247. #ifdef CONFIG_CPU_FREQ
  248. #include <linux/fs.h>
  249. #include <linux/file.h>
  250. struct freq_ctrl {
  251. struct device *dev;
  252. struct file *governor;
  253. struct file *maxfreq;
  254. struct file *parameters_off;
  255. const char *scaling_governor;
  256. const char *scaling_maxfreq;
  257. const char *scaling_parameters_off;
  258. const char *fixed_freq;
  259. char re_cpu_gov[16];
  260. char re_max_freq[16];
  261. };
  262. static struct freq_ctrl *vpu_freq_ctrl;
  263. static int vpu_freq_open(struct freq_ctrl *vpu_freq_ctrl)
  264. {
  265. vpu_freq_ctrl->governor = filp_open(
  266. vpu_freq_ctrl->scaling_governor, O_RDWR, 0);
  267. if (IS_ERR(vpu_freq_ctrl->governor))
  268. goto out;
  269. vpu_freq_ctrl->maxfreq = filp_open(
  270. vpu_freq_ctrl->scaling_maxfreq, O_RDWR, 0);
  271. if (IS_ERR(vpu_freq_ctrl->maxfreq))
  272. goto out;
  273. vpu_freq_ctrl->parameters_off = filp_open(
  274. vpu_freq_ctrl->scaling_parameters_off, O_RDWR, 0);
  275. if (IS_ERR(vpu_freq_ctrl->parameters_off))
  276. goto out;
  277. return 0;
  278. out:
  279. dev_err(vpu_freq_ctrl->dev, "failed open scaling_governor.\n");
  280. return -ENXIO;
  281. }
  282. static int vpu_freq_close(void)
  283. {
  284. if (!vpu_freq_ctrl)
  285. return -ENODEV;
  286. if (vpu_freq_ctrl->governor && vpu_freq_ctrl->maxfreq
  287. && vpu_freq_ctrl->parameters_off) {
  288. fput(vpu_freq_ctrl->governor);
  289. fput(vpu_freq_ctrl->maxfreq);
  290. fput(vpu_freq_ctrl->parameters_off);
  291. vpu_freq_ctrl->governor = NULL;
  292. vpu_freq_ctrl->maxfreq = NULL;
  293. vpu_freq_ctrl->parameters_off = NULL;
  294. }
  295. return 0;
  296. }
  297. static int vpu_freq_save_env(void)
  298. {
  299. const char *fixed_freq = vpu_freq_ctrl->fixed_freq;
  300. const char *governor_mode = "performance";
  301. size_t rv;
  302. if (!vpu_freq_ctrl)
  303. return -ENODEV;
  304. /*save env*/
  305. kernel_read(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  306. sizeof(vpu_freq_ctrl->re_cpu_gov), NULL);
  307. kernel_read(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  308. sizeof(vpu_freq_ctrl->re_max_freq), NULL);
  309. /*setenv*/
  310. rv = kernel_write(vpu_freq_ctrl->maxfreq, fixed_freq,
  311. strlen(fixed_freq), NULL);
  312. rv = kernel_write(vpu_freq_ctrl->governor, governor_mode,
  313. strlen(governor_mode), NULL);
  314. rv = kernel_write(vpu_freq_ctrl->parameters_off, "1", 1, NULL);
  315. return 0;
  316. }
  317. static int vpu_freq_put_env(void)
  318. {
  319. size_t rv;
  320. if (!vpu_freq_ctrl)
  321. return -ENODEV;
  322. rv = kernel_write(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  323. strlen(vpu_freq_ctrl->re_cpu_gov), NULL);
  324. rv = kernel_write(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  325. strlen(vpu_freq_ctrl->re_max_freq), NULL);
  326. rv = kernel_write(vpu_freq_ctrl->parameters_off, "0", 1, NULL);
  327. return 0;
  328. }
  329. static int vpu_freq_init(struct device *dev)
  330. {
  331. int ret;
  332. const char *of_str;
  333. vpu_freq_ctrl = devm_kzalloc(dev, sizeof(*vpu_freq_ctrl), GFP_KERNEL);
  334. if (!vpu_freq_ctrl)
  335. return -ENOMEM;
  336. vpu_freq_ctrl->scaling_governor = "/sys/devices/system/cpu/cpufreq/policy0/scaling_governor";
  337. vpu_freq_ctrl->scaling_maxfreq = "/sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq";
  338. vpu_freq_ctrl->scaling_parameters_off = "/sys/module/cpufreq/parameters/off";
  339. vpu_freq_ctrl->dev = dev;
  340. ret = vpu_freq_open(vpu_freq_ctrl);
  341. if (ret) {
  342. devm_kfree(dev, vpu_freq_ctrl);
  343. vpu_freq_ctrl = NULL;
  344. return ret;
  345. }
  346. if (!device_property_read_string(dev, "vdec,runtime-cpufreq", &of_str))
  347. vpu_freq_ctrl->fixed_freq = of_str;
  348. else
  349. vpu_freq_ctrl->fixed_freq = "1250000";
  350. dev_dbg(dev, "fixed_freq:%s\n", vpu_freq_ctrl->fixed_freq);
  351. return 0;
  352. }
  353. #endif
  354. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  355. {
  356. if (!vb)
  357. return -1;
  358. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  359. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  360. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  361. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  362. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  363. return -1;
  364. }
  365. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  366. #else
  367. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  368. if ((void *)(vb->base) == NULL) {
  369. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  370. return -1;
  371. }
  372. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  373. #endif
  374. return 0;
  375. }
  376. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  377. {
  378. if (!vb)
  379. return;
  380. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  381. if (vb->base)
  382. vmem_free(&s_vmem, vb->phys_addr, 0);
  383. #else
  384. if (vb->base)
  385. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  386. #endif
  387. }
  388. static int vpu_free_instances(struct file *filp)
  389. {
  390. vpudrv_instanace_list_t *vil, *n;
  391. vpudrv_instance_pool_t *vip;
  392. void *vip_base;
  393. int instance_pool_size_per_core;
  394. void *vdi_mutexes_base;
  395. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  396. DPRINTK("[VPUDRV] vpu_free_instances\n");
  397. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  398. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  399. {
  400. if (vil->filp == filp) {
  401. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  402. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  403. vip = (vpudrv_instance_pool_t *)vip_base;
  404. if (vip) {
  405. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  406. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  407. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  408. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  409. if (vdi_mutexes_base) {
  410. int i;
  411. for (i = 0; i < 4; i++) {
  412. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  413. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  414. }
  415. }
  416. }
  417. s_vpu_open_ref_count--;
  418. list_del(&vil->list);
  419. kfree(vil);
  420. }
  421. }
  422. return 1;
  423. }
  424. static int vpu_free_buffers(struct file *filp)
  425. {
  426. vpudrv_buffer_pool_t *pool, *n;
  427. vpudrv_buffer_t vb;
  428. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  429. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  430. {
  431. if (pool->filp == filp) {
  432. vb = pool->vb;
  433. if (vb.base) {
  434. vpu_free_dma_buffer(&vb);
  435. list_del(&pool->list);
  436. kfree(pool);
  437. }
  438. }
  439. }
  440. return 0;
  441. }
  442. #ifdef SUPPORT_MULTI_INST_INTR
  443. static inline u32 get_inst_idx(u32 reg_val)
  444. {
  445. u32 inst_idx;
  446. int i;
  447. for (i=0; i < MAX_NUM_INSTANCE; i++)
  448. {
  449. if(((reg_val >> i)&0x01) == 1)
  450. break;
  451. }
  452. inst_idx = i;
  453. return inst_idx;
  454. }
  455. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  456. {
  457. s32 inst_idx;
  458. u32 reg_val;
  459. u32 int_reason;
  460. int_reason = *reason;
  461. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  462. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  463. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  464. {
  465. reg_val = (empty_inst & 0xffff);
  466. inst_idx = get_inst_idx(reg_val);
  467. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  468. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  469. goto GET_VPU_INST_IDX_HANDLED;
  470. }
  471. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  472. {
  473. reg_val = (seq_inst & 0xffff);
  474. inst_idx = get_inst_idx(reg_val);
  475. *reason = (1 << INT_WAVE5_INIT_SEQ);
  476. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  477. goto GET_VPU_INST_IDX_HANDLED;
  478. }
  479. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  480. {
  481. reg_val = (done_inst & 0xffff);
  482. inst_idx = get_inst_idx(reg_val);
  483. *reason = (1 << INT_WAVE5_DEC_PIC);
  484. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  485. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  486. {
  487. u32 ll_inst_idx;
  488. reg_val = (done_inst >> 16);
  489. ll_inst_idx = get_inst_idx(reg_val);
  490. if (ll_inst_idx == inst_idx)
  491. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  492. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  493. }
  494. goto GET_VPU_INST_IDX_HANDLED;
  495. }
  496. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  497. {
  498. reg_val = (seq_inst & 0xffff);
  499. inst_idx = get_inst_idx(reg_val);
  500. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  501. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  502. goto GET_VPU_INST_IDX_HANDLED;
  503. }
  504. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  505. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  506. {
  507. reg_val = (done_inst & 0xffff);
  508. inst_idx = get_inst_idx(reg_val);
  509. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  510. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  511. goto GET_VPU_INST_IDX_HANDLED;
  512. }
  513. #endif
  514. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  515. {
  516. reg_val = (done_inst >> 16);
  517. inst_idx = get_inst_idx(reg_val);
  518. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  519. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  520. goto GET_VPU_INST_IDX_HANDLED;
  521. }
  522. inst_idx = -1;
  523. *reason = 0;
  524. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  525. GET_VPU_INST_IDX_HANDLED:
  526. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  527. return inst_idx;
  528. }
  529. #endif
  530. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  531. {
  532. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  533. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  534. int core;
  535. int product_code;
  536. #ifdef SUPPORT_MULTI_INST_INTR
  537. u32 intr_reason;
  538. s32 intr_inst_index;
  539. #endif
  540. DPRINTK("[VPUDRV][+]%s\n", __func__);
  541. #ifdef VPU_IRQ_CONTROL
  542. disable_irq_nosync(s_vpu_irq);
  543. #endif
  544. #ifdef SUPPORT_MULTI_INST_INTR
  545. intr_inst_index = 0;
  546. intr_reason = 0;
  547. #endif
  548. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  549. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  550. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  551. continue;
  552. }
  553. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  554. if (PRODUCT_CODE_W_SERIES(product_code)) {
  555. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  556. #ifdef SUPPORT_MULTI_INST_INTR
  557. u32 empty_inst;
  558. u32 done_inst;
  559. u32 seq_inst;
  560. u32 i, reason, reason_clr;
  561. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  562. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  563. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  564. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  565. reason_clr = reason;
  566. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  567. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  568. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  569. intr_reason = reason;
  570. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  571. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  572. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  573. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  574. empty_inst = empty_inst & ~(1 << intr_inst_index);
  575. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  576. if (0 == empty_inst) {
  577. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  578. }
  579. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  580. }
  581. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  582. {
  583. done_inst = done_inst & ~(1 << intr_inst_index);
  584. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  585. if (0 == done_inst) {
  586. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  587. }
  588. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  589. }
  590. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  591. {
  592. seq_inst = seq_inst & ~(1 << intr_inst_index);
  593. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  594. if (0 == seq_inst) {
  595. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  596. }
  597. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  598. }
  599. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  600. {
  601. done_inst = (done_inst >> 16);
  602. done_inst = done_inst & ~(1 << intr_inst_index);
  603. done_inst = (done_inst << 16);
  604. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  605. if (0 == done_inst) {
  606. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  607. }
  608. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  609. }
  610. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  611. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  612. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  613. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  614. }
  615. else
  616. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  617. }
  618. else {
  619. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  620. }
  621. }
  622. else {
  623. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  624. }
  625. }
  626. if (0 != reason)
  627. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  628. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  629. #else
  630. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  631. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  632. #endif
  633. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  634. }
  635. }
  636. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  637. if (ReadVpuRegister(BIT_INT_STS)) {
  638. #ifdef SUPPORT_MULTI_INST_INTR
  639. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  640. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  641. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  642. #else
  643. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  644. #endif
  645. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  646. }
  647. }
  648. else {
  649. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  650. continue;
  651. }
  652. #ifdef SUPPORT_MULTI_INST_INTR
  653. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  654. #else
  655. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  656. #endif
  657. }
  658. if (dev->async_queue)
  659. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  660. #ifdef SUPPORT_MULTI_INST_INTR
  661. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  662. s_interrupt_flag[intr_inst_index]= 1;
  663. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  664. }
  665. #else
  666. s_interrupt_flag = 1;
  667. wake_up_interruptible(&s_interrupt_wait_q);
  668. #endif
  669. DPRINTK("[VPUDRV][-]%s\n", __func__);
  670. return IRQ_HANDLED;
  671. }
  672. static int vpu_open(struct inode *inode, struct file *filp)
  673. {
  674. DPRINTK("[VPUDRV][+] %s\n", __func__);
  675. vpu_clk_enable(s_vpu_clk);
  676. reset_control_deassert(s_vpu_clk->resets);
  677. spin_lock(&s_vpu_lock);
  678. s_vpu_drv_context.open_count++;
  679. filp->private_data = (void *)(&s_vpu_drv_context);
  680. spin_unlock(&s_vpu_lock);
  681. DPRINTK("[VPUDRV][-] %s\n", __func__);
  682. return 0;
  683. }
  684. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  685. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  686. {
  687. int ret = 0;
  688. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  689. switch (cmd) {
  690. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  691. {
  692. vpudrv_buffer_pool_t *vbp = NULL;
  693. void *user_address = NULL;
  694. struct task_struct *my_struct = NULL;
  695. struct mm_struct *mm = NULL;
  696. unsigned long address = 0;
  697. pgd_t *pgd = NULL;
  698. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  699. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  700. if (!vbp) {
  701. up(&s_vpu_sem);
  702. return -ENOMEM;
  703. }
  704. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  705. if (ret) {
  706. kfree(vbp);
  707. up(&s_vpu_sem);
  708. return -EFAULT;
  709. }
  710. user_address = (void *)vbp->vb.virt_addr;
  711. my_struct = get_current();
  712. mm = my_struct->mm;
  713. address = (unsigned long)user_address;
  714. pgd = pgd_offset(mm, address);
  715. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  716. p4d_t *p4d = p4d_offset(pgd, address);
  717. pud_t *pud = pud_offset(p4d, address);
  718. if (!pud_none(*pud) && !pud_bad(*pud)) {
  719. pmd_t *pmd = pmd_offset(pud, address);
  720. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  721. pte_t *pte = pte_offset_map(pmd, address);
  722. if (!pte_none(*pte)) {
  723. struct page *pg = pte_page(*pte);
  724. unsigned long phys = page_to_phys(pg);
  725. unsigned long virt = (unsigned long)phys_to_virt(phys);
  726. printk("attach phy address = %lx, virt = %lx\r\n", phys, virt);
  727. vbp->vb.phys_addr = phys;
  728. vbp->vb.base = virt;
  729. }
  730. pte_unmap(pte);
  731. }
  732. }
  733. }
  734. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  735. if (ret) {
  736. kfree(vbp);
  737. ret = -EFAULT;
  738. up(&s_vpu_sem);
  739. break;
  740. }
  741. vbp->filp = filp;
  742. spin_lock(&s_vpu_lock);
  743. list_add(&vbp->list, &s_vbp_head);
  744. spin_unlock(&s_vpu_lock);
  745. up(&s_vpu_sem);
  746. }
  747. }
  748. break;
  749. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  750. {
  751. vpudrv_buffer_pool_t *vbp;
  752. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  753. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  754. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  755. if (!vbp) {
  756. up(&s_vpu_sem);
  757. return -ENOMEM;
  758. }
  759. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  760. if (ret) {
  761. kfree(vbp);
  762. up(&s_vpu_sem);
  763. return -EFAULT;
  764. }
  765. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  766. if (ret == -1) {
  767. ret = -ENOMEM;
  768. kfree(vbp);
  769. up(&s_vpu_sem);
  770. break;
  771. }
  772. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  773. if (ret) {
  774. kfree(vbp);
  775. ret = -EFAULT;
  776. up(&s_vpu_sem);
  777. break;
  778. }
  779. vbp->filp = filp;
  780. spin_lock(&s_vpu_lock);
  781. list_add(&vbp->list, &s_vbp_head);
  782. spin_unlock(&s_vpu_lock);
  783. up(&s_vpu_sem);
  784. }
  785. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  786. }
  787. break;
  788. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  789. {
  790. vpudrv_buffer_pool_t *vbp, *n;
  791. vpudrv_buffer_t vb;
  792. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  793. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  794. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  795. if (ret) {
  796. up(&s_vpu_sem);
  797. return -EACCES;
  798. }
  799. if (vb.base)
  800. vpu_free_dma_buffer(&vb);
  801. spin_lock(&s_vpu_lock);
  802. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  803. {
  804. if (vbp->vb.base == vb.base) {
  805. list_del(&vbp->list);
  806. kfree(vbp);
  807. break;
  808. }
  809. }
  810. spin_unlock(&s_vpu_lock);
  811. up(&s_vpu_sem);
  812. }
  813. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  814. }
  815. break;
  816. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  817. {
  818. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  819. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  820. if (s_video_memory.base != 0) {
  821. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  822. if (ret != 0)
  823. ret = -EFAULT;
  824. } else {
  825. ret = -EFAULT;
  826. }
  827. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  828. #endif
  829. }
  830. break;
  831. case VDI_IOCTL_WAIT_INTERRUPT:
  832. {
  833. vpudrv_intr_info_t info;
  834. #ifdef SUPPORT_MULTI_INST_INTR
  835. u32 intr_inst_index;
  836. u32 intr_reason_in_q;
  837. u32 interrupt_flag_in_q;
  838. #endif
  839. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  840. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  841. if (ret != 0)
  842. {
  843. return -EFAULT;
  844. }
  845. #ifdef SUPPORT_MULTI_INST_INTR
  846. intr_inst_index = info.intr_inst_index;
  847. intr_reason_in_q = 0;
  848. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  849. if (interrupt_flag_in_q > 0)
  850. {
  851. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  852. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  853. goto INTERRUPT_REMAIN_IN_QUEUE;
  854. }
  855. #endif
  856. #ifdef SUPPORT_MULTI_INST_INTR
  857. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  858. kt = ktime_set(0, info.timeout*1000*1000);
  859. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  860. #else
  861. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  862. #endif
  863. #else
  864. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  865. #endif
  866. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  867. if (ret == -ETIME) {
  868. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  869. break;
  870. }
  871. #endif
  872. if (!ret) {
  873. ret = -ETIME;
  874. break;
  875. }
  876. if (signal_pending(current)) {
  877. ret = -ERESTARTSYS;
  878. break;
  879. }
  880. #ifdef SUPPORT_MULTI_INST_INTR
  881. intr_reason_in_q = 0;
  882. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  883. if (interrupt_flag_in_q > 0) {
  884. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  885. }
  886. else {
  887. dev->interrupt_reason[intr_inst_index] = 0;
  888. }
  889. #endif
  890. #ifdef SUPPORT_MULTI_INST_INTR
  891. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  892. #else
  893. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  894. #endif
  895. #ifdef SUPPORT_MULTI_INST_INTR
  896. INTERRUPT_REMAIN_IN_QUEUE:
  897. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  898. s_interrupt_flag[intr_inst_index] = 0;
  899. dev->interrupt_reason[intr_inst_index] = 0;
  900. #else
  901. info.intr_reason = dev->interrupt_reason;
  902. s_interrupt_flag = 0;
  903. dev->interrupt_reason = 0;
  904. #endif
  905. #ifdef VPU_IRQ_CONTROL
  906. enable_irq(s_vpu_irq);
  907. #endif
  908. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  909. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  910. if (ret != 0)
  911. {
  912. return -EFAULT;
  913. }
  914. }
  915. break;
  916. case VDI_IOCTL_SET_CLOCK_GATE:
  917. {
  918. u32 clkgate;
  919. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  920. if (get_user(clkgate, (u32 __user *) arg))
  921. return -EFAULT;
  922. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  923. if (clkgate)
  924. vpu_clk_enable(s_vpu_clk);
  925. else
  926. vpu_clk_disable(s_vpu_clk);
  927. #endif
  928. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  929. }
  930. break;
  931. case VDI_IOCTL_GET_INSTANCE_POOL:
  932. {
  933. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  934. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  935. if (s_instance_pool.base != 0) {
  936. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  937. if (ret != 0)
  938. ret = -EFAULT;
  939. } else {
  940. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  941. if (ret == 0) {
  942. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  943. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  944. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  945. s_instance_pool.phys_addr = s_instance_pool.base;
  946. if (s_instance_pool.base != 0)
  947. #else
  948. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  949. #endif
  950. {
  951. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  952. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  953. if (ret == 0) {
  954. /* success to get memory for instance pool */
  955. up(&s_vpu_sem);
  956. break;
  957. }
  958. }
  959. }
  960. ret = -EFAULT;
  961. }
  962. up(&s_vpu_sem);
  963. }
  964. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  965. }
  966. break;
  967. case VDI_IOCTL_GET_COMMON_MEMORY:
  968. {
  969. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  970. if (s_common_memory.base != 0) {
  971. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  972. if (ret != 0)
  973. ret = -EFAULT;
  974. } else {
  975. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  976. if (ret == 0) {
  977. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  978. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  979. if (ret == 0) {
  980. /* success to get memory for common memory */
  981. break;
  982. }
  983. }
  984. }
  985. ret = -EFAULT;
  986. }
  987. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  988. }
  989. break;
  990. case VDI_IOCTL_OPEN_INSTANCE:
  991. {
  992. vpudrv_inst_info_t inst_info;
  993. vpudrv_instanace_list_t *vil, *n;
  994. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  995. if (!vil)
  996. return -ENOMEM;
  997. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  998. return -EFAULT;
  999. vil->inst_idx = inst_info.inst_idx;
  1000. vil->core_idx = inst_info.core_idx;
  1001. vil->filp = filp;
  1002. spin_lock(&s_vpu_lock);
  1003. list_add(&vil->list, &s_inst_list_head);
  1004. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1005. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1006. {
  1007. if (vil->core_idx == inst_info.core_idx)
  1008. inst_info.inst_open_count++;
  1009. }
  1010. #ifdef SUPPORT_MULTI_INST_INTR
  1011. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1012. #endif
  1013. spin_unlock(&s_vpu_lock);
  1014. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  1015. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  1016. kfree(vil);
  1017. return -EFAULT;
  1018. }
  1019. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1020. }
  1021. break;
  1022. case VDI_IOCTL_CLOSE_INSTANCE:
  1023. {
  1024. vpudrv_inst_info_t inst_info;
  1025. vpudrv_instanace_list_t *vil, *n;
  1026. u32 found = 0;
  1027. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  1028. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1029. return -EFAULT;
  1030. spin_lock(&s_vpu_lock);
  1031. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1032. {
  1033. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  1034. list_del(&vil->list);
  1035. kfree(vil);
  1036. found = 1;
  1037. break;
  1038. }
  1039. }
  1040. if (0 == found) {
  1041. spin_unlock(&s_vpu_lock);
  1042. return -EINVAL;
  1043. }
  1044. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1045. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1046. {
  1047. if (vil->core_idx == inst_info.core_idx)
  1048. inst_info.inst_open_count++;
  1049. }
  1050. #ifdef SUPPORT_MULTI_INST_INTR
  1051. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1052. #endif
  1053. spin_unlock(&s_vpu_lock);
  1054. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  1055. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  1056. return -EFAULT;
  1057. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1058. }
  1059. break;
  1060. case VDI_IOCTL_GET_INSTANCE_NUM:
  1061. {
  1062. vpudrv_inst_info_t inst_info;
  1063. vpudrv_instanace_list_t *vil, *n;
  1064. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  1065. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  1066. if (ret != 0)
  1067. break;
  1068. spin_lock(&s_vpu_lock);
  1069. inst_info.inst_open_count = 0;
  1070. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1071. {
  1072. if (vil->core_idx == inst_info.core_idx)
  1073. inst_info.inst_open_count++;
  1074. }
  1075. spin_unlock(&s_vpu_lock);
  1076. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  1077. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  1078. }
  1079. break;
  1080. case VDI_IOCTL_RESET:
  1081. {
  1082. vpu_hw_reset();
  1083. }
  1084. break;
  1085. case VDI_IOCTL_GET_REGISTER_INFO:
  1086. {
  1087. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  1088. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  1089. if (ret != 0)
  1090. ret = -EFAULT;
  1091. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  1092. }
  1093. break;
  1094. case VDI_IOCTL_FLUSH_DCACHE:
  1095. {
  1096. vpudrv_flush_cache_t cache_info;
  1097. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  1098. if (ret != 0)
  1099. ret = -EFAULT;
  1100. if(cache_info.flag)
  1101. starfive_flush_dcache(cache_info.start,cache_info.size);
  1102. }
  1103. break;
  1104. case VDI_IOCTL_CPUFREQ_SAVEENV:
  1105. {
  1106. #ifdef CONFIG_CPU_FREQ
  1107. vpu_freq_save_env();
  1108. #endif
  1109. }
  1110. break;
  1111. case VDI_IOCTL_CPUFREQ_PUTENV:
  1112. {
  1113. #ifdef CONFIG_CPU_FREQ
  1114. vpu_freq_put_env();
  1115. #endif
  1116. }
  1117. break;
  1118. default:
  1119. {
  1120. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  1121. }
  1122. break;
  1123. }
  1124. return ret;
  1125. }
  1126. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  1127. {
  1128. return -1;
  1129. }
  1130. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  1131. {
  1132. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  1133. if (!buf) {
  1134. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  1135. return -EFAULT;
  1136. }
  1137. if (len == sizeof(vpu_bit_firmware_info_t)) {
  1138. vpu_bit_firmware_info_t *bit_firmware_info;
  1139. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  1140. if (!bit_firmware_info) {
  1141. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  1142. return -EFAULT;
  1143. }
  1144. if (copy_from_user(bit_firmware_info, buf, len)) {
  1145. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1146. return -EFAULT;
  1147. }
  1148. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1149. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1150. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1151. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1152. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1153. return -ENODEV;
  1154. }
  1155. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1156. kfree(bit_firmware_info);
  1157. return len;
  1158. }
  1159. kfree(bit_firmware_info);
  1160. }
  1161. return -1;
  1162. }
  1163. static int vpu_release(struct inode *inode, struct file *filp)
  1164. {
  1165. int ret = 0;
  1166. u32 open_count;
  1167. #ifdef SUPPORT_MULTI_INST_INTR
  1168. int i;
  1169. #endif
  1170. DPRINTK("[VPUDRV] vpu_release\n");
  1171. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1172. /* found and free the not handled buffer by user applications */
  1173. vpu_free_buffers(filp);
  1174. /* found and free the not closed instance by user applications */
  1175. vpu_free_instances(filp);
  1176. spin_lock(&s_vpu_lock);
  1177. s_vpu_drv_context.open_count--;
  1178. open_count = s_vpu_drv_context.open_count;
  1179. spin_unlock(&s_vpu_lock);
  1180. if (open_count == 0) {
  1181. #ifdef SUPPORT_MULTI_INST_INTR
  1182. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1183. kfifo_reset(&s_interrupt_pending_q[i]);
  1184. }
  1185. #endif
  1186. if (s_instance_pool.base) {
  1187. DPRINTK("[VPUDRV] free instance pool\n");
  1188. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1189. vfree((const void *)s_instance_pool.base);
  1190. #else
  1191. vpu_free_dma_buffer(&s_instance_pool);
  1192. #endif
  1193. s_instance_pool.base = 0;
  1194. }
  1195. }
  1196. }
  1197. up(&s_vpu_sem);
  1198. reset_control_assert(s_vpu_clk->resets);
  1199. vpu_clk_disable(s_vpu_clk);
  1200. return 0;
  1201. }
  1202. static int vpu_fasync(int fd, struct file *filp, int mode)
  1203. {
  1204. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1205. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1206. }
  1207. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1208. {
  1209. unsigned long pfn;
  1210. vm->vm_flags |= VM_IO | VM_RESERVED;
  1211. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1212. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1213. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1214. }
  1215. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1216. {
  1217. vm->vm_flags |= VM_IO | VM_RESERVED;
  1218. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1219. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1220. }
  1221. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1222. {
  1223. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1224. int ret;
  1225. long length = vm->vm_end - vm->vm_start;
  1226. unsigned long start = vm->vm_start;
  1227. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1228. unsigned long pfn;
  1229. vm->vm_flags |= VM_RESERVED;
  1230. /* loop over all pages, map it page individually */
  1231. while (length > 0)
  1232. {
  1233. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1234. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1235. return ret;
  1236. }
  1237. start += PAGE_SIZE;
  1238. vmalloc_area_ptr += PAGE_SIZE;
  1239. length -= PAGE_SIZE;
  1240. }
  1241. return 0;
  1242. #else
  1243. vm->vm_flags |= VM_RESERVED;
  1244. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1245. #endif
  1246. }
  1247. /*!
  1248. * @brief memory map interface for vpu file operation
  1249. * @return 0 on success or negative error code on error
  1250. */
  1251. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1252. {
  1253. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1254. if (vm->vm_pgoff == 0)
  1255. return vpu_map_to_instance_pool_memory(fp, vm);
  1256. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1257. return vpu_map_to_register(fp, vm);
  1258. return vpu_map_to_physical_memory(fp, vm);
  1259. #else
  1260. if (vm->vm_pgoff) {
  1261. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1262. return vpu_map_to_instance_pool_memory(fp, vm);
  1263. return vpu_map_to_physical_memory(fp, vm);
  1264. } else {
  1265. return vpu_map_to_register(fp, vm);
  1266. }
  1267. #endif
  1268. }
  1269. struct file_operations vpu_fops = {
  1270. .owner = THIS_MODULE,
  1271. .open = vpu_open,
  1272. .read = vpu_read,
  1273. .write = vpu_write,
  1274. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1275. .unlocked_ioctl = vpu_ioctl,
  1276. .release = vpu_release,
  1277. .fasync = vpu_fasync,
  1278. .mmap = vpu_mmap,
  1279. };
  1280. static int vpu_probe(struct platform_device *pdev)
  1281. {
  1282. int err = 0;
  1283. struct resource *res = NULL;
  1284. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1285. struct resource res_cma;
  1286. struct device_node *node;
  1287. #endif
  1288. DPRINTK("[VPUDRV] vpu_probe\n");
  1289. if(pdev){
  1290. vpu_dev = &pdev->dev;
  1291. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1292. dev_info(vpu_dev,"device init.\n");
  1293. }
  1294. if (pdev)
  1295. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1296. if (res) {/* if platform driver is implemented */
  1297. s_vpu_register.phys_addr = res->start;
  1298. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1299. s_vpu_register.size = res->end - res->start;
  1300. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1301. } else {
  1302. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1303. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1304. s_vpu_register.size = VPU_REG_SIZE;
  1305. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1306. }
  1307. /* get the major number of the character device */
  1308. if ((alloc_chrdev_region(&s_vpu_major, 0, 1, VPU_DEV_NAME)) < 0) {
  1309. err = -EBUSY;
  1310. printk(KERN_ERR "could not allocate major number\n");
  1311. goto ERROR_PROVE_DEVICE;
  1312. }
  1313. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1314. /* initialize the device structure and register the device with the kernel */
  1315. cdev_init(&s_vpu_cdev, &vpu_fops);
  1316. if ((cdev_add(&s_vpu_cdev, s_vpu_major, 1)) < 0) {
  1317. err = -EBUSY;
  1318. printk(KERN_ERR "could not allocate chrdev\n");
  1319. goto ERROR_PROVE_DEVICE;
  1320. }
  1321. if (pdev)
  1322. s_vpu_clk = vpu_clk_get(pdev);
  1323. else
  1324. s_vpu_clk = vpu_clk_get(NULL);
  1325. if (!s_vpu_clk)
  1326. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1327. else
  1328. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1329. #ifdef CONFIG_CPU_FREQ
  1330. vpu_freq_init(&pdev->dev);
  1331. #endif
  1332. vpu_pmu_enable(s_vpu_clk->dev);
  1333. #ifdef VPU_SUPPORT_ISR
  1334. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1335. if (pdev)
  1336. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1337. if (res) {/* if platform driver is implemented */
  1338. s_vpu_irq = res->start;
  1339. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1340. } else {
  1341. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1342. }
  1343. #else
  1344. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1345. #endif
  1346. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1347. if (err) {
  1348. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1349. goto ERROR_PROVE_DEVICE;
  1350. }
  1351. #endif
  1352. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1353. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1354. if(node){
  1355. dev_info(vpu_dev, "Get mem form memory-region\n");
  1356. of_address_to_resource(node, 0, &res_cma);
  1357. s_video_memory.size = resource_size(&res_cma);
  1358. s_video_memory.phys_addr = res_cma.start;
  1359. }else{
  1360. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1361. return 0;
  1362. }
  1363. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1364. if (!s_video_memory.base) {
  1365. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1366. goto ERROR_PROVE_DEVICE;
  1367. }
  1368. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1369. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1370. goto ERROR_PROVE_DEVICE;
  1371. }
  1372. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1373. #else
  1374. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1375. #endif
  1376. return 0;
  1377. ERROR_PROVE_DEVICE:
  1378. if (s_vpu_major)
  1379. unregister_chrdev_region(s_vpu_major, 1);
  1380. if (s_vpu_register.virt_addr)
  1381. iounmap((void *)s_vpu_register.virt_addr);
  1382. return err;
  1383. }
  1384. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1385. static int vpu_remove(struct platform_device *pdev)
  1386. {
  1387. DPRINTK("[VPUDRV] vpu_remove\n");
  1388. if (s_instance_pool.base) {
  1389. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1390. vfree((const void *)s_instance_pool.base);
  1391. #else
  1392. vpu_free_dma_buffer(&s_instance_pool);
  1393. #endif
  1394. s_instance_pool.base = 0;
  1395. }
  1396. if (s_common_memory.base) {
  1397. vpu_free_dma_buffer(&s_common_memory);
  1398. s_common_memory.base = 0;
  1399. }
  1400. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1401. if (s_video_memory.base) {
  1402. iounmap((void *)s_video_memory.base);
  1403. s_video_memory.base = 0;
  1404. vmem_exit(&s_vmem);
  1405. }
  1406. #endif
  1407. if (s_vpu_major > 0) {
  1408. cdev_del(&s_vpu_cdev);
  1409. unregister_chrdev_region(s_vpu_major, 1);
  1410. s_vpu_major = 0;
  1411. }
  1412. #ifdef VPU_SUPPORT_ISR
  1413. if (s_vpu_irq)
  1414. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1415. #endif
  1416. if (s_vpu_register.virt_addr)
  1417. iounmap((void *)s_vpu_register.virt_addr);
  1418. vpu_clk_put(s_vpu_clk);
  1419. vpu_pmu_disable(s_vpu_clk->dev);
  1420. return 0;
  1421. }
  1422. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1423. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1424. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1425. #define W5_CMD_INIT_VPU (0x0001)
  1426. #define W5_CMD_SLEEP_VPU (0x0004)
  1427. #define W5_CMD_WAKEUP_VPU (0x0002)
  1428. static void Wave5BitIssueCommand(int core, u32 cmd)
  1429. {
  1430. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1431. WriteVpuRegister(W5_COMMAND, cmd);
  1432. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1433. return;
  1434. }
  1435. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1436. {
  1437. int i;
  1438. int core;
  1439. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1440. int product_code;
  1441. DPRINTK("[VPUDRV] vpu_suspend\n");
  1442. vpu_clk_enable(s_vpu_clk);
  1443. if (s_vpu_open_ref_count > 0) {
  1444. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1445. if (s_bit_firmware_info[core].size == 0)
  1446. continue;
  1447. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1448. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1449. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1450. if (time_after(jiffies, timeout)) {
  1451. DPRINTK("SLEEP_VPU BUSY timeout");
  1452. goto DONE_SUSPEND;
  1453. }
  1454. }
  1455. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1456. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1457. if (time_after(jiffies, timeout)) {
  1458. DPRINTK("SLEEP_VPU BUSY timeout");
  1459. goto DONE_SUSPEND;
  1460. }
  1461. }
  1462. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1463. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1464. goto DONE_SUSPEND;
  1465. }
  1466. }
  1467. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1468. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1469. if (time_after(jiffies, timeout))
  1470. goto DONE_SUSPEND;
  1471. }
  1472. for (i = 0; i < 64; i++)
  1473. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1474. }
  1475. else {
  1476. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1477. goto DONE_SUSPEND;
  1478. }
  1479. }
  1480. }
  1481. vpu_clk_disable(s_vpu_clk);
  1482. return 0;
  1483. DONE_SUSPEND:
  1484. vpu_clk_disable(s_vpu_clk);
  1485. return -EAGAIN;
  1486. }
  1487. static int vpu_resume(struct platform_device *pdev)
  1488. {
  1489. int i;
  1490. int core;
  1491. u32 val;
  1492. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1493. int product_code;
  1494. unsigned long code_base;
  1495. u32 code_size;
  1496. u32 remap_size;
  1497. int regVal;
  1498. u32 hwOption = 0;
  1499. DPRINTK("[VPUDRV] vpu_resume\n");
  1500. vpu_clk_enable(s_vpu_clk);
  1501. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1502. if (s_bit_firmware_info[core].size == 0) {
  1503. continue;
  1504. }
  1505. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1506. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1507. code_base = s_common_memory.phys_addr;
  1508. /* ALIGN TO 4KB */
  1509. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1510. if (code_size < s_bit_firmware_info[core].size*2) {
  1511. goto DONE_WAKEUP;
  1512. }
  1513. regVal = 0;
  1514. WriteVpuRegister(W5_PO_CONF, regVal);
  1515. /* Reset All blocks */
  1516. regVal = 0x7ffffff;
  1517. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1518. /* Waiting reset done */
  1519. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1520. if (time_after(jiffies, timeout))
  1521. goto DONE_WAKEUP;
  1522. }
  1523. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1524. /* remap page size */
  1525. remap_size = (code_size >> 12) & 0x1ff;
  1526. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1527. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1528. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1529. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1530. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1531. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1532. WriteVpuRegister(W5_CODE_PARAM, 0);
  1533. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1534. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1535. /* Interrupt */
  1536. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1537. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1538. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1539. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1540. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1541. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1542. }
  1543. else {
  1544. // decoder
  1545. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1546. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1547. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1548. }
  1549. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1550. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1551. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1552. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1553. if (time_after(jiffies, timeout))
  1554. goto DONE_WAKEUP;
  1555. }
  1556. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1557. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1558. goto DONE_WAKEUP;
  1559. }
  1560. }
  1561. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1562. WriteVpuRegister(BIT_CODE_RUN, 0);
  1563. /*---- LOAD BOOT CODE*/
  1564. for (i = 0; i < 512; i++) {
  1565. val = s_bit_firmware_info[core].bit_code[i];
  1566. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1567. }
  1568. for (i = 0 ; i < 64 ; i++)
  1569. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1570. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1571. WriteVpuRegister(BIT_CODE_RESET, 1);
  1572. WriteVpuRegister(BIT_CODE_RUN, 1);
  1573. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1574. if (time_after(jiffies, timeout))
  1575. goto DONE_WAKEUP;
  1576. }
  1577. }
  1578. else {
  1579. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1580. goto DONE_WAKEUP;
  1581. }
  1582. }
  1583. if (s_vpu_open_ref_count == 0)
  1584. vpu_clk_disable(s_vpu_clk);
  1585. DONE_WAKEUP:
  1586. if (s_vpu_open_ref_count > 0)
  1587. vpu_clk_enable(s_vpu_clk);
  1588. return 0;
  1589. }
  1590. #else
  1591. #define vpu_suspend NULL
  1592. #define vpu_resume NULL
  1593. #endif /* !CONFIG_PM */
  1594. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1595. static const struct of_device_id cm_vpu_match[] = {
  1596. {
  1597. .compatible = "c&m,cm511-vpu",
  1598. },
  1599. {
  1600. .compatible = "starfive,vdec",
  1601. },
  1602. {
  1603. /* end of table */
  1604. },
  1605. };
  1606. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1607. static struct platform_driver vpu_driver = {
  1608. .driver = {
  1609. .name = VPU_PLATFORM_DEVICE_NAME,
  1610. .of_match_table = cm_vpu_match,
  1611. },
  1612. .probe = vpu_probe,
  1613. .remove = vpu_remove,
  1614. .suspend = vpu_suspend,
  1615. .resume = vpu_resume,
  1616. };
  1617. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1618. static int __init vpu_init(void)
  1619. {
  1620. int res;
  1621. #ifdef SUPPORT_MULTI_INST_INTR
  1622. int i;
  1623. #endif
  1624. DPRINTK("[VPUDRV] begin vpu_init\n");
  1625. #ifdef SUPPORT_MULTI_INST_INTR
  1626. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1627. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1628. }
  1629. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1630. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1631. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1632. if (res) {
  1633. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1634. }
  1635. }
  1636. #else
  1637. init_waitqueue_head(&s_interrupt_wait_q);
  1638. #endif
  1639. s_common_memory.base = 0;
  1640. s_instance_pool.base = 0;
  1641. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1642. res = platform_driver_register(&vpu_driver);
  1643. #else
  1644. res = vpu_probe(NULL);
  1645. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1646. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1647. return res;
  1648. }
  1649. static void __exit vpu_exit(void)
  1650. {
  1651. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1652. DPRINTK("[VPUDRV] vpu_exit\n");
  1653. platform_driver_unregister(&vpu_driver);
  1654. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1655. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1656. #else
  1657. vpu_clk_disable(s_vpu_clk);
  1658. #endif
  1659. vpu_clk_put(s_vpu_clk);
  1660. if (s_instance_pool.base) {
  1661. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1662. vfree((const void *)s_instance_pool.base);
  1663. #else
  1664. vpu_free_dma_buffer(&s_instance_pool);
  1665. #endif
  1666. s_instance_pool.base = 0;
  1667. }
  1668. if (s_common_memory.base) {
  1669. vpu_free_dma_buffer(&s_common_memory);
  1670. s_common_memory.base = 0;
  1671. }
  1672. #ifdef CONFIG_CPU_FREQ
  1673. vpu_freq_close();
  1674. #endif
  1675. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1676. if (s_video_memory.base) {
  1677. iounmap((void *)s_video_memory.base);
  1678. s_video_memory.base = 0;
  1679. vmem_exit(&s_vmem);
  1680. }
  1681. #endif
  1682. if (s_vpu_major > 0) {
  1683. cdev_del(&s_vpu_cdev);
  1684. unregister_chrdev_region(s_vpu_major, 1);
  1685. s_vpu_major = 0;
  1686. }
  1687. #ifdef VPU_SUPPORT_ISR
  1688. if (s_vpu_irq)
  1689. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1690. #endif
  1691. #ifdef SUPPORT_MULTI_INST_INTR
  1692. {
  1693. int i;
  1694. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1695. kfifo_free(&s_interrupt_pending_q[i]);
  1696. }
  1697. }
  1698. #endif
  1699. if (s_vpu_register.virt_addr) {
  1700. iounmap((void *)s_vpu_register.virt_addr);
  1701. s_vpu_register.virt_addr = 0x00;
  1702. }
  1703. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1704. return;
  1705. }
  1706. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1707. MODULE_DESCRIPTION("VPU linux driver");
  1708. MODULE_LICENSE("GPL");
  1709. module_init(vpu_init);
  1710. module_exit(vpu_exit);
  1711. static int vpu_pmu_enable(struct device *dev)
  1712. {
  1713. int ret;
  1714. pm_runtime_enable(dev);
  1715. ret = pm_runtime_get_sync(dev);
  1716. if (ret < 0)
  1717. dev_err(dev, "failed to get pm runtime: %d\n", ret);
  1718. return ret;
  1719. }
  1720. static void vpu_pmu_disable(struct device *dev)
  1721. {
  1722. pm_runtime_put_sync(dev);
  1723. pm_runtime_disable(dev);
  1724. }
  1725. /* clk&reset for starfive jh7110*/
  1726. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1727. #define CLK_ENABLE_DATA 1
  1728. #define CLK_DISABLE_DATA 0
  1729. #define CLK_EN_SHIFT 31
  1730. #define CLK_EN_MASK 0x80000000U
  1731. #define SAIF_BD_APBS_BASE 0x13020000
  1732. #define WAVE511_CLK_AXI_CTRL 0x118U
  1733. #define WAVE511_CLK_BPU_CTRL 0x11cU
  1734. #define WAVE511_CLK_VCE_CTRL 0x120U
  1735. #define WAVE511_CLK_APB_CTRL 0x124U
  1736. #define WAVE511_CLK_NOCBUS_CTRL 0x130U
  1737. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1738. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1739. #define RSTN_AXI_MASK (0x1 << 15)
  1740. #define RSTN_BPU_MASK (0x1 << 16)
  1741. #define RSTN_VCE_MASK (0x1 << 17)
  1742. #define RSTN_APB_MASK (0x1 << 18)
  1743. #define RSTN_128B_AXIMEM_MASK (0x1 << 21)
  1744. static uint32_t saif_get_reg(const volatile void __iomem *addr,
  1745. uint32_t shift, uint32_t mask)
  1746. {
  1747. u32 tmp;
  1748. tmp = readl(addr);
  1749. tmp = (tmp & mask) >> shift;
  1750. return tmp;
  1751. }
  1752. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1753. uint32_t shift, uint32_t mask)
  1754. {
  1755. uint32_t tmp;
  1756. tmp = readl(addr);
  1757. tmp &= ~mask;
  1758. tmp |= (data << shift) & mask;
  1759. writel(tmp, addr);
  1760. }
  1761. static void saif_assert_rst(volatile void __iomem *addr,
  1762. const volatile void __iomem *addr_status, uint32_t mask)
  1763. {
  1764. uint32_t tmp;
  1765. tmp = readl(addr);
  1766. tmp |= mask;
  1767. writel(tmp, addr);
  1768. do {
  1769. tmp = readl(addr_status);
  1770. } while ((tmp & mask) != 0);
  1771. }
  1772. static void saif_clear_rst(volatile void __iomem *addr,
  1773. const volatile void __iomem *addr_status, uint32_t mask)
  1774. {
  1775. uint32_t tmp;
  1776. tmp = readl(addr);
  1777. tmp &= ~mask;
  1778. writel(tmp, addr);
  1779. do {
  1780. tmp = readl(addr_status);
  1781. } while ((tmp & mask) != mask);
  1782. }
  1783. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1784. {
  1785. if (enable)
  1786. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1787. else
  1788. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1789. }
  1790. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1791. {
  1792. if (enable) {
  1793. /*enable*/
  1794. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1795. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1796. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1797. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1798. /*clr-reset*/
  1799. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1800. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1801. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1802. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1803. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1804. } else {
  1805. /*assert-reset*/
  1806. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1807. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1808. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1809. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1810. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1811. /*disable*/
  1812. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1813. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1814. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1815. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1816. }
  1817. }
  1818. static void vpu_clk_reset(vpu_clk_t *clk)
  1819. {
  1820. /*assert-reset*/
  1821. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1822. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1823. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1824. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1825. /*clr-reset*/
  1826. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1827. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1828. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1829. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1830. }
  1831. int vpu_hw_reset(void)
  1832. {
  1833. if (!s_vpu_clk)
  1834. return -1;
  1835. vpu_clk_reset(s_vpu_clk);
  1836. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1837. return 0;
  1838. }
  1839. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1840. {
  1841. if (!pdev)
  1842. return -ENXIO;
  1843. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1844. if (IS_ERR(vpu_clk->clkgen)) {
  1845. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1846. return PTR_ERR(vpu_clk->clkgen);
  1847. }
  1848. /* clkgen define */
  1849. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
  1850. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
  1851. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
  1852. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
  1853. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
  1854. vpu_clk->en_mask = CLK_EN_MASK;
  1855. vpu_clk->en_shift = CLK_EN_SHIFT;
  1856. /* rstgen define */
  1857. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1858. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1859. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1860. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1861. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1862. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1863. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1864. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
  1865. vpu_clk->noc_ctrl = true;
  1866. return 0;
  1867. }
  1868. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1869. {
  1870. vpu_clk_t *vpu_clk;
  1871. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1872. if (!vpu_clk)
  1873. return NULL;
  1874. if (vpu_of_clk_get(pdev, vpu_clk))
  1875. goto err_get_clk;
  1876. return vpu_clk;
  1877. err_get_clk:
  1878. devm_kfree(&pdev->dev, vpu_clk);
  1879. return NULL;
  1880. }
  1881. static void vpu_clk_put(vpu_clk_t *clk)
  1882. {
  1883. if (clk->clkgen) {
  1884. iounmap(clk->clkgen);
  1885. clk->clkgen = NULL;
  1886. }
  1887. }
  1888. static int vpu_clk_enable(vpu_clk_t *clk)
  1889. {
  1890. if (clk == NULL || IS_ERR(clk))
  1891. return -1;
  1892. vpu_pmu_enable(clk->dev);
  1893. vpu_clk_control(clk, true);
  1894. if (clk->noc_ctrl == true)
  1895. vpu_noc_vdec_bus_control(clk, true);
  1896. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1897. return 0;
  1898. }
  1899. static void vpu_clk_disable(vpu_clk_t *clk)
  1900. {
  1901. if (clk == NULL || IS_ERR(clk))
  1902. return;
  1903. vpu_clk_control(clk, false);
  1904. vpu_pmu_disable(clk->dev);
  1905. if (clk->noc_ctrl == true)
  1906. vpu_noc_vdec_bus_control(clk, false);
  1907. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1908. }
  1909. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1910. int vpu_hw_reset(void)
  1911. {
  1912. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1913. /* sram do not need reset */
  1914. return reset_control_reset(s_vpu_clk->resets);
  1915. }
  1916. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1917. {
  1918. struct device *dev = &pdev->dev;
  1919. int ret;
  1920. vpu_clk->dev = dev;
  1921. vpu_clk->clks = vpu_clks;
  1922. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  1923. vpu_clk->resets = devm_reset_control_array_get_shared(dev);
  1924. if (IS_ERR(vpu_clk->resets)) {
  1925. ret = PTR_ERR(vpu_clk->resets);
  1926. dev_err(dev, "faied to get vpu reset controls\n");
  1927. }
  1928. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  1929. if (ret)
  1930. dev_err(dev, "faied to get vpu clk controls\n");
  1931. if (device_property_read_bool(dev, "starfive,vdec_noc_ctrl"))
  1932. vpu_clk->noc_ctrl = true;
  1933. return 0;
  1934. }
  1935. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1936. {
  1937. vpu_clk_t *vpu_clk;
  1938. if (!pdev)
  1939. return NULL;
  1940. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1941. if (!vpu_clk)
  1942. return NULL;
  1943. if (vpu_of_clk_get(pdev, vpu_clk))
  1944. goto err_of_clk_get;
  1945. return vpu_clk;
  1946. err_of_clk_get:
  1947. devm_kfree(&pdev->dev, vpu_clk);
  1948. return NULL;
  1949. }
  1950. static void vpu_clk_put(vpu_clk_t *clk)
  1951. {
  1952. clk_bulk_put(clk->nr_clks, clk->clks);
  1953. }
  1954. static int vpu_clk_enable(vpu_clk_t *clk)
  1955. {
  1956. int ret;
  1957. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1958. if (ret)
  1959. dev_err(clk->dev, "enable clk error.\n");
  1960. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1961. return ret;
  1962. }
  1963. static void vpu_clk_disable(vpu_clk_t *clk)
  1964. {
  1965. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  1966. }
  1967. #endif