vdec.c 78 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2022, Chips&Media
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  16. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  19. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  22. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  24. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. *
  26. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  27. */
  28. #include <linux/kernel.h>
  29. #include <linux/mm.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/ioport.h>
  32. #include <linux/module.h>
  33. #include <linux/mutex.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/of.h>
  37. #include <linux/pm_runtime.h>
  38. #include <linux/wait.h>
  39. #include <linux/list.h>
  40. #include <linux/clk.h>
  41. #include <linux/delay.h>
  42. #include <linux/uaccess.h>
  43. #include <linux/cdev.h>
  44. #include <linux/slab.h>
  45. #include <linux/of_address.h>
  46. #include <linux/sched.h>
  47. #include <linux/sched/signal.h>
  48. #include <linux/version.h>
  49. #include <linux/kfifo.h>
  50. #include <linux/kthread.h>
  51. #include <linux/reset.h>
  52. #include <asm/io.h>
  53. #include "../../../vpuapi/vpuconfig.h"
  54. #include "vpu.h"
  55. extern void sifive_ccache_flush_range(phys_addr_t start, size_t len);
  56. //#define ENABLE_DEBUG_MSG
  57. #ifdef ENABLE_DEBUG_MSG
  58. #define DPRINTK(args...) printk(KERN_INFO args);
  59. #else
  60. #define DPRINTK(args...)
  61. #endif
  62. /* definitions to be changed as customer configuration */
  63. /* if you want to have clock gating scheme frame by frame */
  64. /* #define VPU_SUPPORT_CLOCK_CONTROL */
  65. /* if the driver want to use interrupt service from kernel ISR */
  66. #define VPU_SUPPORT_ISR
  67. #ifdef VPU_SUPPORT_ISR
  68. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  69. //#define VPU_IRQ_CONTROL
  70. #endif
  71. //#define CONFIG_USE_PLL_DYNAMIC_FREQ
  72. #define VPU_SUPPORT_CLOCK_CONTROL
  73. /* if clktree is work,try this...*/
  74. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  75. /* if the platform driver knows the name of this driver */
  76. /* VPU_PLATFORM_DEVICE_NAME */
  77. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  78. /* if this driver knows the dedicated video memory address */
  79. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  80. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  81. #define VPU_CLK_NAME "vcodec"
  82. #define VPU_DEV_NAME "vdec"
  83. /* if the platform driver knows this driver */
  84. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  85. #define VPU_REG_BASE_ADDR 0x118F0000
  86. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  87. #ifdef VPU_SUPPORT_ISR
  88. #define VPU_IRQ_NUM (23)
  89. #endif
  90. /* this definition is only for chipsnmedia FPGA board env */
  91. /* so for SOC env of customers can be ignored */
  92. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  93. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  94. #endif
  95. struct device *vpu_dev;
  96. typedef struct vpu_drv_context_t {
  97. struct fasync_struct *async_queue;
  98. #ifdef SUPPORT_MULTI_INST_INTR
  99. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  100. #else
  101. unsigned long interrupt_reason;
  102. #endif
  103. u32 open_count; /*!<< device reference count. Not instance count */
  104. } vpu_drv_context_t;
  105. /* To track the allocated memory buffer */
  106. typedef struct vpudrv_buffer_pool_t {
  107. struct list_head list;
  108. struct vpudrv_buffer_t vb;
  109. struct file *filp;
  110. } vpudrv_buffer_pool_t;
  111. /* To track the instance index and buffer in instance pool */
  112. typedef struct vpudrv_instanace_list_t {
  113. struct list_head list;
  114. unsigned long inst_idx;
  115. unsigned long core_idx;
  116. struct file *filp;
  117. } vpudrv_instanace_list_t;
  118. typedef struct vpudrv_instance_pool_t {
  119. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  120. } vpudrv_instance_pool_t;
  121. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  122. typedef struct vpu_clkgen_t {
  123. void __iomem *en_ctrl;
  124. uint32_t rst_mask;
  125. } vpu_clkgen_t;
  126. #endif
  127. struct clk_bulk_data vpu_clks[] = {
  128. { .id = "apb_clk" },
  129. { .id = "axi_clk" },
  130. { .id = "bpu_clk" },
  131. { .id = "vce_clk" },
  132. { .id = "noc_bus" },
  133. };
  134. typedef struct vpu_clk_t {
  135. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  136. void __iomem *clkgen;
  137. void __iomem *rst_ctrl;
  138. void __iomem *rst_status;
  139. void __iomem *noc_bus;
  140. uint32_t en_shift;
  141. uint32_t en_mask;
  142. vpu_clkgen_t apb_clk;
  143. vpu_clkgen_t axi_clk;
  144. vpu_clkgen_t bpu_clk;
  145. vpu_clkgen_t vce_clk;
  146. vpu_clkgen_t aximem_128b;
  147. #else
  148. struct clk_bulk_data *clks;
  149. struct reset_control *resets;
  150. int nr_clks;
  151. #endif
  152. struct device *dev;
  153. bool noc_ctrl;
  154. } vpu_clk_t;
  155. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  156. #include "vmm.h"
  157. static video_mm_t s_vmem;
  158. static vpudrv_buffer_t s_video_memory = {0};
  159. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  160. static int vpu_hw_reset(void);
  161. static void vpu_clk_disable(vpu_clk_t *clk);
  162. static int vpu_clk_enable(vpu_clk_t *clk);
  163. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  164. static void vpu_clk_put(vpu_clk_t *clk);
  165. static int vpu_pmu_enable(struct device *dev);
  166. static void vpu_pmu_disable(struct device *dev);
  167. /* end customer definition */
  168. static vpudrv_buffer_t s_instance_pool = {0};
  169. static vpudrv_buffer_t s_common_memory = {0};
  170. static vpu_drv_context_t s_vpu_drv_context;
  171. static dev_t s_vpu_devt;
  172. static int s_vpu_major;
  173. static struct cdev s_vpu_cdev;
  174. static struct class *s_vpu_class;
  175. static vpu_clk_t *s_vpu_clk;
  176. static int s_vpu_open_ref_count;
  177. #ifdef VPU_SUPPORT_ISR
  178. static int s_vpu_irq = VPU_IRQ_NUM;
  179. #endif
  180. static vpudrv_buffer_t s_vpu_register = {0};
  181. #ifdef SUPPORT_MULTI_INST_INTR
  182. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  183. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  184. typedef struct kfifo kfifo_t;
  185. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  186. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  187. #else
  188. static int s_interrupt_flag;
  189. static wait_queue_head_t s_interrupt_wait_q;
  190. #endif
  191. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  192. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  193. static DECLARE_MUTEX(s_vpu_sem);
  194. #else
  195. static DEFINE_SEMAPHORE(s_vpu_sem);
  196. #endif
  197. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  198. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  199. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  200. //#ifdef CONFIG_PM
  201. /* implement to power management functions */
  202. #define BIT_BASE 0x0000
  203. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  204. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  205. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  206. #define BIT_INT_STS (BIT_BASE + 0x010)
  207. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  208. #define BIT_INT_REASON (BIT_BASE + 0x174)
  209. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  210. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  211. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  212. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  213. /* WAVE5 registers */
  214. #define W5_REG_BASE 0x0000
  215. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  216. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  217. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  218. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  219. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  220. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  221. #ifdef SUPPORT_MULTI_INST_INTR
  222. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  223. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  224. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  225. typedef enum {
  226. INT_WAVE5_INIT_VPU = 0,
  227. INT_WAVE5_WAKEUP_VPU = 1,
  228. INT_WAVE5_SLEEP_VPU = 2,
  229. INT_WAVE5_CREATE_INSTANCE = 3,
  230. INT_WAVE5_FLUSH_INSTANCE = 4,
  231. INT_WAVE5_DESTORY_INSTANCE = 5,
  232. INT_WAVE5_INIT_SEQ = 6,
  233. INT_WAVE5_SET_FRAMEBUF = 7,
  234. INT_WAVE5_DEC_PIC = 8,
  235. INT_WAVE5_ENC_PIC = 8,
  236. INT_WAVE5_ENC_SET_PARAM = 9,
  237. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  238. INT_WAVE5_ENC_SRC_RELEASE = 10,
  239. #endif
  240. INT_WAVE5_ENC_LOW_LATENCY = 13,
  241. INT_WAVE5_DEC_QUERY = 14,
  242. INT_WAVE5_BSBUF_EMPTY = 15,
  243. INT_WAVE5_BSBUF_FULL = 15,
  244. } Wave5InterruptBit;
  245. #endif
  246. /* WAVE5 INIT, WAKEUP */
  247. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  248. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  249. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  250. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  251. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  252. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  253. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  254. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  255. #define W5_REMAP_CODE_INDEX 0
  256. /* WAVE5 registers */
  257. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  258. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  259. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  260. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  261. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  262. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  263. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  264. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  265. /* Product register */
  266. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  267. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  268. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  269. #endif
  270. //#endif //CONFIG_PM
  271. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  272. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  273. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  274. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  275. #include <linux/fs.h>
  276. #include <linux/file.h>
  277. struct freq_ctrl {
  278. struct device *dev;
  279. struct file *governor;
  280. struct file *maxfreq;
  281. struct file *parameters_off;
  282. const char *scaling_governor;
  283. const char *scaling_maxfreq;
  284. const char *scaling_parameters_off;
  285. const char *fixed_freq;
  286. char re_cpu_gov[16];
  287. char re_max_freq[16];
  288. struct mutex mutex_lock;
  289. int count;
  290. };
  291. static struct freq_ctrl *vpu_freq_ctrl;
  292. static int vpu_freq_open(struct freq_ctrl *vpu_freq_ctrl)
  293. {
  294. vpu_freq_ctrl->governor = filp_open(
  295. vpu_freq_ctrl->scaling_governor, O_RDWR, 0);
  296. if (IS_ERR(vpu_freq_ctrl->governor))
  297. goto out;
  298. vpu_freq_ctrl->maxfreq = filp_open(
  299. vpu_freq_ctrl->scaling_maxfreq, O_RDWR, 0);
  300. if (IS_ERR(vpu_freq_ctrl->maxfreq))
  301. goto out;
  302. vpu_freq_ctrl->parameters_off = filp_open(
  303. vpu_freq_ctrl->scaling_parameters_off, O_RDWR, 0);
  304. if (IS_ERR(vpu_freq_ctrl->parameters_off))
  305. goto out;
  306. return 0;
  307. out:
  308. dev_err(vpu_freq_ctrl->dev, "failed open scaling_governor.\n");
  309. return -ENXIO;
  310. }
  311. static int vpu_freq_close(void)
  312. {
  313. if (!vpu_freq_ctrl)
  314. return -ENODEV;
  315. mutex_destroy(&vpu_freq_ctrl->mutex_lock);
  316. if (vpu_freq_ctrl->governor && vpu_freq_ctrl->maxfreq
  317. && vpu_freq_ctrl->parameters_off) {
  318. fput(vpu_freq_ctrl->governor);
  319. fput(vpu_freq_ctrl->maxfreq);
  320. fput(vpu_freq_ctrl->parameters_off);
  321. vpu_freq_ctrl->governor = NULL;
  322. vpu_freq_ctrl->maxfreq = NULL;
  323. vpu_freq_ctrl->parameters_off = NULL;
  324. }
  325. return 0;
  326. }
  327. static int vpu_freq_save_env(void)
  328. {
  329. const char *fixed_freq = vpu_freq_ctrl->fixed_freq;
  330. const char *governor_mode = "performance";
  331. size_t rv;
  332. if (!vpu_freq_ctrl)
  333. return -ENODEV;
  334. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  335. if (vpu_freq_ctrl->count == 0) {
  336. /*save env*/
  337. kernel_read(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  338. sizeof(vpu_freq_ctrl->re_cpu_gov), NULL);
  339. kernel_read(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  340. sizeof(vpu_freq_ctrl->re_max_freq), NULL);
  341. /*setenv*/
  342. rv = kernel_write(vpu_freq_ctrl->maxfreq, fixed_freq,
  343. strlen(fixed_freq), NULL);
  344. rv = kernel_write(vpu_freq_ctrl->governor, governor_mode,
  345. strlen(governor_mode), NULL);
  346. rv = kernel_write(vpu_freq_ctrl->parameters_off, "1", 1, NULL);
  347. }
  348. vpu_freq_ctrl->count++;
  349. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  350. return 0;
  351. }
  352. static int vpu_freq_put_env(void)
  353. {
  354. size_t rv;
  355. if (!vpu_freq_ctrl)
  356. return -ENODEV;
  357. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  358. vpu_freq_ctrl->count--;
  359. if (vpu_freq_ctrl->count == 0) {
  360. rv = kernel_write(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  361. strlen(vpu_freq_ctrl->re_cpu_gov), NULL);
  362. rv = kernel_write(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  363. strlen(vpu_freq_ctrl->re_max_freq), NULL);
  364. rv = kernel_write(vpu_freq_ctrl->parameters_off, "0", 1, NULL);
  365. }
  366. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  367. return 0;
  368. }
  369. static int vpu_freq_init(struct device *dev)
  370. {
  371. int ret;
  372. const char *of_str;
  373. vpu_freq_ctrl = devm_kzalloc(dev, sizeof(*vpu_freq_ctrl), GFP_KERNEL);
  374. if (!vpu_freq_ctrl)
  375. return -ENOMEM;
  376. vpu_freq_ctrl->scaling_governor = "/sys/devices/system/cpu/cpufreq/policy0/scaling_governor";
  377. vpu_freq_ctrl->scaling_maxfreq = "/sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq";
  378. vpu_freq_ctrl->scaling_parameters_off = "/sys/module/cpufreq/parameters/off";
  379. vpu_freq_ctrl->dev = dev;
  380. ret = vpu_freq_open(vpu_freq_ctrl);
  381. if (ret) {
  382. devm_kfree(dev, vpu_freq_ctrl);
  383. vpu_freq_ctrl = NULL;
  384. return ret;
  385. }
  386. if (!device_property_read_string(dev, "vdec,runtime-cpufreq", &of_str))
  387. vpu_freq_ctrl->fixed_freq = of_str;
  388. else
  389. vpu_freq_ctrl->fixed_freq = "1250000";
  390. vpu_freq_ctrl->count = 0;
  391. mutex_init(&vpu_freq_ctrl->mutex_lock);
  392. dev_dbg(dev, "fixed_freq:%s\n", vpu_freq_ctrl->fixed_freq);
  393. return 0;
  394. }
  395. #endif
  396. static void starfive_flush_dcache(phys_addr_t start, size_t len)
  397. {
  398. #ifdef ARCH_HAS_SYNC_DMA_FOR_DEVICE
  399. dma_sync_single_for_device(vpu_dev, start, len, DMA_FROM_DEVICE);
  400. #else
  401. sifive_ccache_flush_range(start, len);
  402. #endif
  403. }
  404. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  405. {
  406. if (!vb)
  407. return -1;
  408. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  409. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  410. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  411. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  412. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  413. return -1;
  414. }
  415. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  416. #else
  417. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  418. if ((void *)(vb->base) == NULL) {
  419. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  420. return -1;
  421. }
  422. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  423. #endif
  424. return 0;
  425. }
  426. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  427. {
  428. if (!vb)
  429. return;
  430. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  431. if (vb->base)
  432. vmem_free(&s_vmem, vb->phys_addr, 0);
  433. #else
  434. if (vb->base)
  435. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  436. #endif
  437. }
  438. static int vpu_free_instances(struct file *filp)
  439. {
  440. vpudrv_instanace_list_t *vil, *n;
  441. vpudrv_instance_pool_t *vip;
  442. void *vip_base;
  443. int instance_pool_size_per_core;
  444. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  445. void *vdi_mutexes_base;
  446. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  447. #endif
  448. DPRINTK("[VPUDRV] vpu_free_instances\n");
  449. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  450. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  451. {
  452. if (vil->filp == filp) {
  453. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  454. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  455. vip = (vpudrv_instance_pool_t *)vip_base;
  456. if (vip) {
  457. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  458. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  459. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  460. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  461. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  462. if (vdi_mutexes_base) {
  463. int i;
  464. for (i = 0; i < 4; i++) {
  465. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  466. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  467. }
  468. }
  469. #endif
  470. }
  471. s_vpu_open_ref_count--;
  472. list_del(&vil->list);
  473. kfree(vil);
  474. }
  475. }
  476. return 1;
  477. }
  478. static int vpu_free_buffers(struct file *filp)
  479. {
  480. vpudrv_buffer_pool_t *pool, *n;
  481. vpudrv_buffer_t vb;
  482. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  483. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  484. {
  485. if (pool->filp == filp) {
  486. vb = pool->vb;
  487. if (vb.base) {
  488. vpu_free_dma_buffer(&vb);
  489. list_del(&pool->list);
  490. kfree(pool);
  491. }
  492. }
  493. }
  494. return 0;
  495. }
  496. #ifdef SUPPORT_MULTI_INST_INTR
  497. static inline u32 get_inst_idx(u32 reg_val)
  498. {
  499. u32 inst_idx;
  500. int i;
  501. for (i=0; i < MAX_NUM_INSTANCE; i++)
  502. {
  503. if(((reg_val >> i)&0x01) == 1)
  504. break;
  505. }
  506. inst_idx = i;
  507. return inst_idx;
  508. }
  509. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  510. {
  511. s32 inst_idx;
  512. u32 reg_val;
  513. u32 int_reason;
  514. int_reason = *reason;
  515. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  516. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  517. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  518. {
  519. reg_val = (empty_inst & 0xffff);
  520. inst_idx = get_inst_idx(reg_val);
  521. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  522. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  523. goto GET_VPU_INST_IDX_HANDLED;
  524. }
  525. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  526. {
  527. reg_val = (seq_inst & 0xffff);
  528. inst_idx = get_inst_idx(reg_val);
  529. *reason = (1 << INT_WAVE5_INIT_SEQ);
  530. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  531. goto GET_VPU_INST_IDX_HANDLED;
  532. }
  533. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  534. {
  535. reg_val = (done_inst & 0xffff);
  536. inst_idx = get_inst_idx(reg_val);
  537. *reason = (1 << INT_WAVE5_DEC_PIC);
  538. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  539. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  540. {
  541. u32 ll_inst_idx;
  542. reg_val = (done_inst >> 16);
  543. ll_inst_idx = get_inst_idx(reg_val);
  544. if (ll_inst_idx == inst_idx)
  545. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  546. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  547. }
  548. goto GET_VPU_INST_IDX_HANDLED;
  549. }
  550. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  551. {
  552. reg_val = (seq_inst & 0xffff);
  553. inst_idx = get_inst_idx(reg_val);
  554. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  555. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  556. goto GET_VPU_INST_IDX_HANDLED;
  557. }
  558. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  559. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  560. {
  561. reg_val = (done_inst & 0xffff);
  562. inst_idx = get_inst_idx(reg_val);
  563. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  564. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  565. goto GET_VPU_INST_IDX_HANDLED;
  566. }
  567. #endif
  568. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  569. {
  570. reg_val = (done_inst >> 16);
  571. inst_idx = get_inst_idx(reg_val);
  572. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  573. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  574. goto GET_VPU_INST_IDX_HANDLED;
  575. }
  576. inst_idx = -1;
  577. *reason = 0;
  578. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  579. GET_VPU_INST_IDX_HANDLED:
  580. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  581. return inst_idx;
  582. }
  583. #endif
  584. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  585. {
  586. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  587. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  588. int core;
  589. int product_code;
  590. #ifdef SUPPORT_MULTI_INST_INTR
  591. u32 intr_reason;
  592. s32 intr_inst_index;
  593. #endif
  594. DPRINTK("[VPUDRV][+]%s\n", __func__);
  595. #ifdef VPU_IRQ_CONTROL
  596. disable_irq_nosync(s_vpu_irq);
  597. #endif
  598. #ifdef SUPPORT_MULTI_INST_INTR
  599. intr_inst_index = 0;
  600. intr_reason = 0;
  601. #endif
  602. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  603. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  604. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  605. continue;
  606. }
  607. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  608. if (PRODUCT_CODE_W_SERIES(product_code)) {
  609. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  610. #ifdef SUPPORT_MULTI_INST_INTR
  611. u32 empty_inst;
  612. u32 done_inst;
  613. u32 seq_inst;
  614. u32 i, reason, reason_clr;
  615. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  616. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  617. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  618. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  619. reason_clr = reason;
  620. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  621. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  622. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  623. intr_reason = reason;
  624. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  625. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  626. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  627. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  628. empty_inst = empty_inst & ~(1 << intr_inst_index);
  629. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  630. if (0 == empty_inst) {
  631. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  632. }
  633. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  634. }
  635. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  636. {
  637. done_inst = done_inst & ~(1 << intr_inst_index);
  638. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  639. if (0 == done_inst) {
  640. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  641. }
  642. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  643. }
  644. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  645. {
  646. seq_inst = seq_inst & ~(1 << intr_inst_index);
  647. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  648. if (0 == seq_inst) {
  649. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  650. }
  651. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  652. }
  653. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  654. {
  655. done_inst = (done_inst >> 16);
  656. done_inst = done_inst & ~(1 << intr_inst_index);
  657. done_inst = (done_inst << 16);
  658. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  659. if (0 == done_inst) {
  660. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  661. }
  662. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  663. }
  664. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  665. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  666. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  667. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  668. }
  669. else
  670. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  671. }
  672. else {
  673. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  674. }
  675. }
  676. else {
  677. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  678. }
  679. }
  680. if (0 != reason)
  681. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  682. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  683. #else
  684. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  685. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  686. #endif
  687. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  688. }
  689. }
  690. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  691. if (ReadVpuRegister(BIT_INT_STS)) {
  692. #ifdef SUPPORT_MULTI_INST_INTR
  693. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  694. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  695. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  696. #else
  697. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  698. #endif
  699. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  700. }
  701. }
  702. else {
  703. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  704. continue;
  705. }
  706. #ifdef SUPPORT_MULTI_INST_INTR
  707. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  708. #else
  709. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  710. #endif
  711. }
  712. if (dev->async_queue)
  713. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  714. #ifdef SUPPORT_MULTI_INST_INTR
  715. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  716. s_interrupt_flag[intr_inst_index]= 1;
  717. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  718. }
  719. #else
  720. s_interrupt_flag = 1;
  721. wake_up_interruptible(&s_interrupt_wait_q);
  722. #endif
  723. DPRINTK("[VPUDRV][-]%s\n", __func__);
  724. return IRQ_HANDLED;
  725. }
  726. static int vpu_open(struct inode *inode, struct file *filp)
  727. {
  728. DPRINTK("[VPUDRV][+] %s\n", __func__);
  729. pm_runtime_get_sync(s_vpu_clk->dev);
  730. spin_lock(&s_vpu_lock);
  731. s_vpu_drv_context.open_count++;
  732. filp->private_data = (void *)(&s_vpu_drv_context);
  733. spin_unlock(&s_vpu_lock);
  734. DPRINTK("[VPUDRV][-] %s\n", __func__);
  735. return 0;
  736. }
  737. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  738. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  739. {
  740. int ret = 0;
  741. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  742. switch (cmd) {
  743. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  744. {
  745. vpudrv_buffer_pool_t *vbp = NULL;
  746. void *user_address = NULL;
  747. struct task_struct *my_struct = NULL;
  748. struct mm_struct *mm = NULL;
  749. unsigned long address = 0;
  750. pgd_t *pgd = NULL;
  751. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  752. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  753. if (!vbp) {
  754. up(&s_vpu_sem);
  755. return -ENOMEM;
  756. }
  757. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  758. if (ret) {
  759. kfree(vbp);
  760. up(&s_vpu_sem);
  761. return -EFAULT;
  762. }
  763. user_address = (void *)vbp->vb.virt_addr;
  764. my_struct = get_current();
  765. mm = my_struct->mm;
  766. address = (unsigned long)user_address;
  767. pgd = pgd_offset(mm, address);
  768. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  769. p4d_t *p4d = p4d_offset(pgd, address);
  770. pud_t *pud = pud_offset(p4d, address);
  771. if (!pud_none(*pud) && !pud_bad(*pud)) {
  772. pmd_t *pmd = pmd_offset(pud, address);
  773. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  774. pte_t *pte = pte_offset_map(pmd, address);
  775. if (!pte_none(*pte)) {
  776. struct page *pg = pte_page(*pte);
  777. unsigned long phys = page_to_phys(pg);
  778. unsigned long virt = (unsigned long)phys_to_virt(phys);
  779. printk("attach phy address = %lx, virt = %lx\r\n", phys, virt);
  780. vbp->vb.phys_addr = phys;
  781. vbp->vb.base = virt;
  782. }
  783. pte_unmap(pte);
  784. }
  785. }
  786. }
  787. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  788. if (ret) {
  789. kfree(vbp);
  790. ret = -EFAULT;
  791. up(&s_vpu_sem);
  792. break;
  793. }
  794. vbp->filp = filp;
  795. spin_lock(&s_vpu_lock);
  796. list_add(&vbp->list, &s_vbp_head);
  797. spin_unlock(&s_vpu_lock);
  798. up(&s_vpu_sem);
  799. }
  800. }
  801. break;
  802. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  803. {
  804. vpudrv_buffer_pool_t *vbp;
  805. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  806. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  807. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  808. if (!vbp) {
  809. up(&s_vpu_sem);
  810. return -ENOMEM;
  811. }
  812. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  813. if (ret) {
  814. kfree(vbp);
  815. up(&s_vpu_sem);
  816. return -EFAULT;
  817. }
  818. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  819. if (ret == -1) {
  820. ret = -ENOMEM;
  821. kfree(vbp);
  822. up(&s_vpu_sem);
  823. break;
  824. }
  825. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  826. if (ret) {
  827. kfree(vbp);
  828. ret = -EFAULT;
  829. up(&s_vpu_sem);
  830. break;
  831. }
  832. vbp->filp = filp;
  833. spin_lock(&s_vpu_lock);
  834. list_add(&vbp->list, &s_vbp_head);
  835. spin_unlock(&s_vpu_lock);
  836. up(&s_vpu_sem);
  837. }
  838. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  839. }
  840. break;
  841. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  842. {
  843. vpudrv_buffer_pool_t *vbp, *n;
  844. vpudrv_buffer_t vb;
  845. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  846. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  847. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  848. if (ret) {
  849. up(&s_vpu_sem);
  850. return -EACCES;
  851. }
  852. if (vb.base)
  853. vpu_free_dma_buffer(&vb);
  854. spin_lock(&s_vpu_lock);
  855. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  856. {
  857. if (vbp->vb.base == vb.base) {
  858. list_del(&vbp->list);
  859. kfree(vbp);
  860. break;
  861. }
  862. }
  863. spin_unlock(&s_vpu_lock);
  864. up(&s_vpu_sem);
  865. }
  866. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  867. }
  868. break;
  869. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  870. {
  871. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  872. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  873. if (s_video_memory.base != 0) {
  874. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  875. if (ret != 0)
  876. ret = -EFAULT;
  877. } else {
  878. ret = -EFAULT;
  879. }
  880. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  881. #endif
  882. }
  883. break;
  884. case VDI_IOCTL_WAIT_INTERRUPT:
  885. {
  886. vpudrv_intr_info_t info;
  887. #ifdef SUPPORT_MULTI_INST_INTR
  888. u32 intr_inst_index;
  889. u32 intr_reason_in_q;
  890. u32 interrupt_flag_in_q;
  891. #endif
  892. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  893. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  894. if (ret != 0)
  895. {
  896. return -EFAULT;
  897. }
  898. #ifdef SUPPORT_MULTI_INST_INTR
  899. intr_inst_index = info.intr_inst_index;
  900. intr_reason_in_q = 0;
  901. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  902. if (interrupt_flag_in_q > 0)
  903. {
  904. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  905. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  906. goto INTERRUPT_REMAIN_IN_QUEUE;
  907. }
  908. #endif
  909. #ifdef SUPPORT_MULTI_INST_INTR
  910. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  911. kt = ktime_set(0, info.timeout*1000*1000);
  912. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  913. #else
  914. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  915. #endif
  916. #else
  917. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  918. #endif
  919. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  920. if (ret == -ETIME) {
  921. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  922. break;
  923. }
  924. #endif
  925. if (!ret) {
  926. ret = -ETIME;
  927. break;
  928. }
  929. if (signal_pending(current)) {
  930. ret = -ERESTARTSYS;
  931. break;
  932. }
  933. #ifdef SUPPORT_MULTI_INST_INTR
  934. intr_reason_in_q = 0;
  935. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  936. if (interrupt_flag_in_q > 0) {
  937. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  938. }
  939. else {
  940. dev->interrupt_reason[intr_inst_index] = 0;
  941. }
  942. #endif
  943. #ifdef SUPPORT_MULTI_INST_INTR
  944. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  945. #else
  946. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  947. #endif
  948. #ifdef SUPPORT_MULTI_INST_INTR
  949. INTERRUPT_REMAIN_IN_QUEUE:
  950. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  951. s_interrupt_flag[intr_inst_index] = 0;
  952. dev->interrupt_reason[intr_inst_index] = 0;
  953. #else
  954. info.intr_reason = dev->interrupt_reason;
  955. s_interrupt_flag = 0;
  956. dev->interrupt_reason = 0;
  957. #endif
  958. #ifdef VPU_IRQ_CONTROL
  959. enable_irq(s_vpu_irq);
  960. #endif
  961. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  962. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  963. if (ret != 0)
  964. {
  965. return -EFAULT;
  966. }
  967. }
  968. break;
  969. case VDI_IOCTL_SET_CLOCK_GATE:
  970. {
  971. u32 clkgate;
  972. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  973. if (get_user(clkgate, (u32 __user *) arg))
  974. return -EFAULT;
  975. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  976. if (clkgate)
  977. vpu_clk_enable(s_vpu_clk);
  978. else
  979. vpu_clk_disable(s_vpu_clk);
  980. #endif
  981. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  982. }
  983. break;
  984. case VDI_IOCTL_GET_INSTANCE_POOL:
  985. {
  986. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  987. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  988. if (s_instance_pool.base != 0) {
  989. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  990. if (ret != 0)
  991. ret = -EFAULT;
  992. } else {
  993. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  994. if (ret == 0) {
  995. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  996. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  997. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  998. s_instance_pool.phys_addr = s_instance_pool.base;
  999. if (s_instance_pool.base != 0)
  1000. #else
  1001. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  1002. #endif
  1003. {
  1004. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  1005. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  1006. if (ret == 0) {
  1007. /* success to get memory for instance pool */
  1008. up(&s_vpu_sem);
  1009. break;
  1010. }
  1011. }
  1012. }
  1013. ret = -EFAULT;
  1014. }
  1015. up(&s_vpu_sem);
  1016. }
  1017. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  1018. }
  1019. break;
  1020. case VDI_IOCTL_GET_COMMON_MEMORY:
  1021. {
  1022. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  1023. if (s_common_memory.base != 0) {
  1024. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  1025. if (ret != 0)
  1026. ret = -EFAULT;
  1027. } else {
  1028. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  1029. if (ret == 0) {
  1030. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  1031. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  1032. if (ret == 0) {
  1033. /* success to get memory for common memory */
  1034. break;
  1035. }
  1036. }
  1037. }
  1038. ret = -EFAULT;
  1039. }
  1040. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  1041. }
  1042. break;
  1043. case VDI_IOCTL_OPEN_INSTANCE:
  1044. {
  1045. vpudrv_inst_info_t inst_info;
  1046. vpudrv_instanace_list_t *vil, *n;
  1047. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  1048. if (!vil)
  1049. return -ENOMEM;
  1050. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1051. return -EFAULT;
  1052. vil->inst_idx = inst_info.inst_idx;
  1053. vil->core_idx = inst_info.core_idx;
  1054. vil->filp = filp;
  1055. spin_lock(&s_vpu_lock);
  1056. list_add(&vil->list, &s_inst_list_head);
  1057. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1058. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1059. {
  1060. if (vil->core_idx == inst_info.core_idx)
  1061. inst_info.inst_open_count++;
  1062. }
  1063. #ifdef SUPPORT_MULTI_INST_INTR
  1064. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1065. #endif
  1066. spin_unlock(&s_vpu_lock);
  1067. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  1068. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  1069. kfree(vil);
  1070. return -EFAULT;
  1071. }
  1072. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1073. }
  1074. break;
  1075. case VDI_IOCTL_CLOSE_INSTANCE:
  1076. {
  1077. vpudrv_inst_info_t inst_info;
  1078. vpudrv_instanace_list_t *vil, *n;
  1079. u32 found = 0;
  1080. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  1081. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1082. return -EFAULT;
  1083. spin_lock(&s_vpu_lock);
  1084. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1085. {
  1086. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  1087. list_del(&vil->list);
  1088. kfree(vil);
  1089. found = 1;
  1090. break;
  1091. }
  1092. }
  1093. if (0 == found) {
  1094. spin_unlock(&s_vpu_lock);
  1095. return -EINVAL;
  1096. }
  1097. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1098. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1099. {
  1100. if (vil->core_idx == inst_info.core_idx)
  1101. inst_info.inst_open_count++;
  1102. }
  1103. #ifdef SUPPORT_MULTI_INST_INTR
  1104. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1105. #endif
  1106. spin_unlock(&s_vpu_lock);
  1107. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  1108. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  1109. return -EFAULT;
  1110. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1111. }
  1112. break;
  1113. case VDI_IOCTL_GET_INSTANCE_NUM:
  1114. {
  1115. vpudrv_inst_info_t inst_info;
  1116. vpudrv_instanace_list_t *vil, *n;
  1117. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  1118. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  1119. if (ret != 0)
  1120. break;
  1121. spin_lock(&s_vpu_lock);
  1122. inst_info.inst_open_count = 0;
  1123. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1124. {
  1125. if (vil->core_idx == inst_info.core_idx)
  1126. inst_info.inst_open_count++;
  1127. }
  1128. spin_unlock(&s_vpu_lock);
  1129. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  1130. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  1131. }
  1132. break;
  1133. case VDI_IOCTL_RESET:
  1134. {
  1135. vpu_hw_reset();
  1136. }
  1137. break;
  1138. case VDI_IOCTL_GET_REGISTER_INFO:
  1139. {
  1140. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  1141. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  1142. if (ret != 0)
  1143. ret = -EFAULT;
  1144. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  1145. }
  1146. break;
  1147. case VDI_IOCTL_FLUSH_DCACHE:
  1148. {
  1149. vpudrv_flush_cache_t cache_info;
  1150. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  1151. if (ret != 0)
  1152. ret = -EFAULT;
  1153. if(cache_info.flag)
  1154. starfive_flush_dcache(cache_info.start,cache_info.size);
  1155. }
  1156. break;
  1157. case VDI_IOCTL_CPUFREQ_SAVEENV:
  1158. {
  1159. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1160. vpu_freq_save_env();
  1161. #endif
  1162. }
  1163. break;
  1164. case VDI_IOCTL_CPUFREQ_PUTENV:
  1165. {
  1166. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1167. vpu_freq_put_env();
  1168. #endif
  1169. }
  1170. break;
  1171. default:
  1172. {
  1173. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  1174. }
  1175. break;
  1176. }
  1177. return ret;
  1178. }
  1179. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  1180. {
  1181. return -1;
  1182. }
  1183. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  1184. {
  1185. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  1186. if (!buf) {
  1187. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  1188. return -EFAULT;
  1189. }
  1190. if (len == sizeof(vpu_bit_firmware_info_t)) {
  1191. vpu_bit_firmware_info_t *bit_firmware_info;
  1192. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  1193. if (!bit_firmware_info) {
  1194. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  1195. return -EFAULT;
  1196. }
  1197. if (copy_from_user(bit_firmware_info, buf, len)) {
  1198. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1199. return -EFAULT;
  1200. }
  1201. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1202. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1203. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1204. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1205. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1206. return -ENODEV;
  1207. }
  1208. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1209. kfree(bit_firmware_info);
  1210. return len;
  1211. }
  1212. kfree(bit_firmware_info);
  1213. }
  1214. return -1;
  1215. }
  1216. static int vpu_release(struct inode *inode, struct file *filp)
  1217. {
  1218. int ret = 0;
  1219. u32 open_count;
  1220. #ifdef SUPPORT_MULTI_INST_INTR
  1221. int i;
  1222. #endif
  1223. DPRINTK("[VPUDRV] vpu_release\n");
  1224. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1225. /* found and free the not handled buffer by user applications */
  1226. vpu_free_buffers(filp);
  1227. /* found and free the not closed instance by user applications */
  1228. vpu_free_instances(filp);
  1229. spin_lock(&s_vpu_lock);
  1230. s_vpu_drv_context.open_count--;
  1231. open_count = s_vpu_drv_context.open_count;
  1232. spin_unlock(&s_vpu_lock);
  1233. if (open_count == 0) {
  1234. #ifdef SUPPORT_MULTI_INST_INTR
  1235. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1236. kfifo_reset(&s_interrupt_pending_q[i]);
  1237. }
  1238. #endif
  1239. if (s_instance_pool.base) {
  1240. DPRINTK("[VPUDRV] free instance pool\n");
  1241. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1242. vfree((const void *)s_instance_pool.base);
  1243. #else
  1244. vpu_free_dma_buffer(&s_instance_pool);
  1245. #endif
  1246. s_instance_pool.base = 0;
  1247. }
  1248. }
  1249. }
  1250. up(&s_vpu_sem);
  1251. pm_runtime_put_sync(s_vpu_clk->dev);
  1252. return 0;
  1253. }
  1254. static int vpu_fasync(int fd, struct file *filp, int mode)
  1255. {
  1256. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1257. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1258. }
  1259. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1260. {
  1261. unsigned long pfn;
  1262. vm->vm_flags |= VM_IO | VM_RESERVED;
  1263. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1264. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1265. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1266. }
  1267. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1268. {
  1269. vm->vm_flags |= VM_IO | VM_RESERVED;
  1270. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1271. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1272. }
  1273. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1274. {
  1275. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1276. int ret;
  1277. long length = vm->vm_end - vm->vm_start;
  1278. unsigned long start = vm->vm_start;
  1279. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1280. unsigned long pfn;
  1281. vm->vm_flags |= VM_RESERVED;
  1282. /* loop over all pages, map it page individually */
  1283. while (length > 0)
  1284. {
  1285. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1286. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1287. return ret;
  1288. }
  1289. start += PAGE_SIZE;
  1290. vmalloc_area_ptr += PAGE_SIZE;
  1291. length -= PAGE_SIZE;
  1292. }
  1293. return 0;
  1294. #else
  1295. vm->vm_flags |= VM_RESERVED;
  1296. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1297. #endif
  1298. }
  1299. /*!
  1300. * @brief memory map interface for vpu file operation
  1301. * @return 0 on success or negative error code on error
  1302. */
  1303. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1304. {
  1305. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1306. if (vm->vm_pgoff == 0)
  1307. return vpu_map_to_instance_pool_memory(fp, vm);
  1308. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1309. return vpu_map_to_register(fp, vm);
  1310. return vpu_map_to_physical_memory(fp, vm);
  1311. #else
  1312. if (vm->vm_pgoff) {
  1313. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1314. return vpu_map_to_instance_pool_memory(fp, vm);
  1315. return vpu_map_to_physical_memory(fp, vm);
  1316. } else {
  1317. return vpu_map_to_register(fp, vm);
  1318. }
  1319. #endif
  1320. }
  1321. struct file_operations vpu_fops = {
  1322. .owner = THIS_MODULE,
  1323. .open = vpu_open,
  1324. .read = vpu_read,
  1325. .write = vpu_write,
  1326. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1327. .unlocked_ioctl = vpu_ioctl,
  1328. .release = vpu_release,
  1329. .fasync = vpu_fasync,
  1330. .mmap = vpu_mmap,
  1331. };
  1332. static int vpu_probe(struct platform_device *pdev)
  1333. {
  1334. int err = 0;
  1335. struct resource *res = NULL;
  1336. struct device *devices;
  1337. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1338. struct resource res_cma;
  1339. struct device_node *node;
  1340. #endif
  1341. int irq = -1;
  1342. DPRINTK("[VPUDRV] vpu_probe\n");
  1343. if(pdev){
  1344. vpu_dev = &pdev->dev;
  1345. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1346. dev_info(vpu_dev,"device init.\n");
  1347. }
  1348. if (pdev)
  1349. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1350. if (res) {/* if platform driver is implemented */
  1351. s_vpu_register.phys_addr = res->start;
  1352. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1353. s_vpu_register.size = res->end - res->start;
  1354. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1355. } else {
  1356. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1357. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1358. s_vpu_register.size = VPU_REG_SIZE;
  1359. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1360. }
  1361. /* get the major number of the character device */
  1362. if ((alloc_chrdev_region(&s_vpu_devt, 0, 1, VPU_DEV_NAME)) < 0) {
  1363. err = -EBUSY;
  1364. printk(KERN_ERR "could not allocate major number\n");
  1365. goto ERROR_PROVE_DEVICE;
  1366. }
  1367. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1368. s_vpu_major = MAJOR(s_vpu_devt);
  1369. /* initialize the device structure and register the device with the kernel */
  1370. cdev_init(&s_vpu_cdev, &vpu_fops);
  1371. if ((cdev_add(&s_vpu_cdev, s_vpu_devt, 1)) < 0) {
  1372. err = -EBUSY;
  1373. printk(KERN_ERR "could not allocate chrdev\n");
  1374. goto ERROR_PROVE_DEVICE;
  1375. }
  1376. s_vpu_class = class_create(THIS_MODULE, VPU_DEV_NAME);
  1377. if (IS_ERR(s_vpu_class)) {
  1378. dev_err(vpu_dev, "class creat error.\n");
  1379. goto ERROR_CRART_CLASS;
  1380. }
  1381. devices = device_create(s_vpu_class, 0, MKDEV(s_vpu_major, 0),
  1382. NULL, VPU_DEV_NAME);
  1383. if (IS_ERR(devices)) {
  1384. dev_err(vpu_dev, "device creat error.\n");
  1385. goto ERROR_CREAT_DEVICE;
  1386. }
  1387. if (pdev)
  1388. s_vpu_clk = vpu_clk_get(pdev);
  1389. else
  1390. s_vpu_clk = vpu_clk_get(NULL);
  1391. if (!s_vpu_clk)
  1392. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1393. else
  1394. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1395. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1396. vpu_freq_init(&pdev->dev);
  1397. #endif
  1398. vpu_pmu_enable(s_vpu_clk->dev);
  1399. vpu_clk_enable(s_vpu_clk);
  1400. reset_control_deassert(s_vpu_clk->resets);
  1401. #ifdef VPU_SUPPORT_ISR
  1402. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1403. if (pdev)
  1404. irq = platform_get_irq(pdev, 0);
  1405. if (irq >= 0) {/* if platform driver is implemented */
  1406. s_vpu_irq = irq;
  1407. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1408. } else {
  1409. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1410. }
  1411. #else
  1412. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1413. #endif
  1414. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1415. if (err) {
  1416. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1417. goto ERROR_PROVE_DEVICE;
  1418. }
  1419. #endif
  1420. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1421. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1422. if(node){
  1423. dev_info(vpu_dev, "Get mem form memory-region\n");
  1424. of_address_to_resource(node, 0, &res_cma);
  1425. s_video_memory.size = resource_size(&res_cma);
  1426. s_video_memory.phys_addr = res_cma.start;
  1427. }else{
  1428. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1429. return 0;
  1430. }
  1431. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1432. if (!s_video_memory.base) {
  1433. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1434. goto ERROR_PROVE_DEVICE;
  1435. }
  1436. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1437. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1438. goto ERROR_PROVE_DEVICE;
  1439. }
  1440. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1441. #else
  1442. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1443. #endif
  1444. return 0;
  1445. ERROR_CREAT_DEVICE:
  1446. class_destroy(s_vpu_class);
  1447. ERROR_CRART_CLASS:
  1448. cdev_del(&s_vpu_cdev);
  1449. ERROR_PROVE_DEVICE:
  1450. if (s_vpu_major)
  1451. unregister_chrdev_region(s_vpu_major, 1);
  1452. if (s_vpu_register.virt_addr)
  1453. iounmap((void *)s_vpu_register.virt_addr);
  1454. return err;
  1455. }
  1456. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1457. static int vpu_remove(struct platform_device *pdev)
  1458. {
  1459. DPRINTK("[VPUDRV] vpu_remove\n");
  1460. if (s_instance_pool.base) {
  1461. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1462. vfree((const void *)s_instance_pool.base);
  1463. #else
  1464. vpu_free_dma_buffer(&s_instance_pool);
  1465. #endif
  1466. s_instance_pool.base = 0;
  1467. }
  1468. if (s_common_memory.base) {
  1469. vpu_free_dma_buffer(&s_common_memory);
  1470. s_common_memory.base = 0;
  1471. }
  1472. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1473. if (s_video_memory.base) {
  1474. iounmap((void *)s_video_memory.base);
  1475. s_video_memory.base = 0;
  1476. vmem_exit(&s_vmem);
  1477. }
  1478. #endif
  1479. if (s_vpu_major > 0) {
  1480. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1481. class_destroy(s_vpu_class);
  1482. cdev_del(&s_vpu_cdev);
  1483. unregister_chrdev_region(s_vpu_devt, 1);
  1484. s_vpu_major = 0;
  1485. }
  1486. #ifdef VPU_SUPPORT_ISR
  1487. if (s_vpu_irq)
  1488. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1489. #endif
  1490. if (s_vpu_register.virt_addr)
  1491. iounmap((void *)s_vpu_register.virt_addr);
  1492. vpu_clk_put(s_vpu_clk);
  1493. vpu_pmu_disable(s_vpu_clk->dev);
  1494. return 0;
  1495. }
  1496. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1497. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1498. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1499. #define W5_CMD_INIT_VPU (0x0001)
  1500. #define W5_CMD_SLEEP_VPU (0x0004)
  1501. #define W5_CMD_WAKEUP_VPU (0x0002)
  1502. static void Wave5BitIssueCommand(int core, u32 cmd)
  1503. {
  1504. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1505. WriteVpuRegister(W5_COMMAND, cmd);
  1506. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1507. return;
  1508. }
  1509. static int __maybe_unused vpu_runtime_suspend(struct device *dev)
  1510. {
  1511. reset_control_assert(s_vpu_clk->resets);
  1512. vpu_clk_disable(s_vpu_clk);
  1513. return 0;
  1514. }
  1515. static int __maybe_unused vpu_runtime_resume(struct device *dev)
  1516. {
  1517. vpu_clk_enable(s_vpu_clk);
  1518. return reset_control_deassert(s_vpu_clk->resets);
  1519. }
  1520. #ifdef CONFIG_PM_SLEEP
  1521. static int __maybe_unused vpu_suspend(struct device *dev)
  1522. {
  1523. int i;
  1524. int core;
  1525. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1526. int product_code;
  1527. DPRINTK("[VPUDRV] vpu_suspend\n");
  1528. pm_runtime_get_sync(dev);
  1529. if (s_vpu_open_ref_count > 0) {
  1530. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1531. if (s_bit_firmware_info[core].size == 0)
  1532. continue;
  1533. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1534. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1535. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1536. if (time_after(jiffies, timeout)) {
  1537. DPRINTK("SLEEP_VPU BUSY timeout");
  1538. goto DONE_SUSPEND;
  1539. }
  1540. }
  1541. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1542. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1543. if (time_after(jiffies, timeout)) {
  1544. DPRINTK("SLEEP_VPU BUSY timeout");
  1545. goto DONE_SUSPEND;
  1546. }
  1547. }
  1548. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1549. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1550. goto DONE_SUSPEND;
  1551. }
  1552. }
  1553. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1554. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1555. if (time_after(jiffies, timeout))
  1556. goto DONE_SUSPEND;
  1557. }
  1558. for (i = 0; i < 64; i++)
  1559. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1560. }
  1561. else {
  1562. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1563. goto DONE_SUSPEND;
  1564. }
  1565. }
  1566. }
  1567. DONE_SUSPEND:
  1568. pm_runtime_put_sync(dev);
  1569. pm_runtime_force_suspend(dev);
  1570. return 0;
  1571. }
  1572. static int __maybe_unused vpu_resume(struct device *dev)
  1573. {
  1574. int i;
  1575. int core;
  1576. u32 val;
  1577. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1578. int product_code;
  1579. unsigned long code_base;
  1580. u32 code_size;
  1581. u32 remap_size;
  1582. int regVal;
  1583. u32 hwOption = 0;
  1584. DPRINTK("[VPUDRV] vpu_resume\n");
  1585. pm_runtime_force_resume(dev);
  1586. pm_runtime_get_sync(dev);
  1587. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1588. if (s_bit_firmware_info[core].size == 0) {
  1589. continue;
  1590. }
  1591. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1592. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1593. code_base = s_common_memory.phys_addr;
  1594. /* ALIGN TO 4KB */
  1595. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1596. if (code_size < s_bit_firmware_info[core].size*2) {
  1597. goto DONE_WAKEUP;
  1598. }
  1599. regVal = 0;
  1600. WriteVpuRegister(W5_PO_CONF, regVal);
  1601. /* Reset All blocks */
  1602. regVal = 0x7ffffff;
  1603. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1604. /* Waiting reset done */
  1605. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1606. if (time_after(jiffies, timeout))
  1607. goto DONE_WAKEUP;
  1608. }
  1609. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1610. /* remap page size */
  1611. remap_size = (code_size >> 12) & 0x1ff;
  1612. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1613. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1614. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1615. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1616. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1617. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1618. WriteVpuRegister(W5_CODE_PARAM, 0);
  1619. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1620. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1621. /* Interrupt */
  1622. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1623. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1624. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1625. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1626. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1627. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1628. }
  1629. else {
  1630. // decoder
  1631. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1632. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1633. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1634. }
  1635. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1636. Wave5BitIssueCommand(core, W5_CMD_WAKEUP_VPU);
  1637. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1638. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1639. if (time_after(jiffies, timeout))
  1640. goto DONE_WAKEUP;
  1641. }
  1642. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1643. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1644. goto DONE_WAKEUP;
  1645. }
  1646. }
  1647. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1648. WriteVpuRegister(BIT_CODE_RUN, 0);
  1649. /*---- LOAD BOOT CODE*/
  1650. for (i = 0; i < 512; i++) {
  1651. val = s_bit_firmware_info[core].bit_code[i];
  1652. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1653. }
  1654. for (i = 0 ; i < 64 ; i++)
  1655. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1656. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1657. WriteVpuRegister(BIT_CODE_RESET, 1);
  1658. WriteVpuRegister(BIT_CODE_RUN, 1);
  1659. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1660. if (time_after(jiffies, timeout))
  1661. goto DONE_WAKEUP;
  1662. }
  1663. }
  1664. else {
  1665. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1666. goto DONE_WAKEUP;
  1667. }
  1668. }
  1669. DONE_WAKEUP:
  1670. pm_runtime_put_sync(dev);
  1671. return 0;
  1672. }
  1673. #endif /* CONFIG_PM_SLEEP */
  1674. #endif /* !CONFIG_PM */
  1675. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1676. static const struct of_device_id cm_vpu_match[] = {
  1677. {
  1678. .compatible = "c&m,cm511-vpu",
  1679. },
  1680. {
  1681. .compatible = "starfive,vdec",
  1682. },
  1683. {
  1684. /* end of table */
  1685. },
  1686. };
  1687. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1688. static const struct dev_pm_ops cm_vpu_pm_ops = {
  1689. SET_RUNTIME_PM_OPS(vpu_runtime_suspend,
  1690. vpu_runtime_resume, NULL)
  1691. SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
  1692. };
  1693. static struct platform_driver vpu_driver = {
  1694. .driver = {
  1695. .name = VPU_PLATFORM_DEVICE_NAME,
  1696. .of_match_table = cm_vpu_match,
  1697. .pm = &cm_vpu_pm_ops,
  1698. },
  1699. .probe = vpu_probe,
  1700. .remove = vpu_remove,
  1701. };
  1702. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1703. static int __init vpu_init(void)
  1704. {
  1705. int res;
  1706. #ifdef SUPPORT_MULTI_INST_INTR
  1707. int i;
  1708. #endif
  1709. DPRINTK("[VPUDRV] begin vpu_init\n");
  1710. #ifdef SUPPORT_MULTI_INST_INTR
  1711. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1712. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1713. }
  1714. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1715. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1716. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1717. if (res) {
  1718. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1719. }
  1720. }
  1721. #else
  1722. init_waitqueue_head(&s_interrupt_wait_q);
  1723. #endif
  1724. s_common_memory.base = 0;
  1725. s_instance_pool.base = 0;
  1726. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1727. res = platform_driver_register(&vpu_driver);
  1728. #else
  1729. res = vpu_probe(NULL);
  1730. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1731. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1732. return res;
  1733. }
  1734. static void __exit vpu_exit(void)
  1735. {
  1736. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1737. DPRINTK("[VPUDRV] vpu_exit\n");
  1738. platform_driver_unregister(&vpu_driver);
  1739. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1740. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1741. #else
  1742. vpu_clk_disable(s_vpu_clk);
  1743. #endif
  1744. vpu_clk_put(s_vpu_clk);
  1745. if (s_instance_pool.base) {
  1746. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1747. vfree((const void *)s_instance_pool.base);
  1748. #else
  1749. vpu_free_dma_buffer(&s_instance_pool);
  1750. #endif
  1751. s_instance_pool.base = 0;
  1752. }
  1753. if (s_common_memory.base) {
  1754. vpu_free_dma_buffer(&s_common_memory);
  1755. s_common_memory.base = 0;
  1756. }
  1757. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1758. vpu_freq_close();
  1759. #endif
  1760. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1761. if (s_video_memory.base) {
  1762. iounmap((void *)s_video_memory.base);
  1763. s_video_memory.base = 0;
  1764. vmem_exit(&s_vmem);
  1765. }
  1766. #endif
  1767. if (s_vpu_major > 0) {
  1768. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1769. class_destroy(s_vpu_class);
  1770. cdev_del(&s_vpu_cdev);
  1771. unregister_chrdev_region(s_vpu_devt, 1);
  1772. s_vpu_major = 0;
  1773. }
  1774. #ifdef VPU_SUPPORT_ISR
  1775. if (s_vpu_irq)
  1776. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1777. #endif
  1778. #ifdef SUPPORT_MULTI_INST_INTR
  1779. {
  1780. int i;
  1781. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1782. kfifo_free(&s_interrupt_pending_q[i]);
  1783. }
  1784. }
  1785. #endif
  1786. if (s_vpu_register.virt_addr) {
  1787. iounmap((void *)s_vpu_register.virt_addr);
  1788. s_vpu_register.virt_addr = 0x00;
  1789. }
  1790. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1791. return;
  1792. }
  1793. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1794. MODULE_DESCRIPTION("VPU linux driver");
  1795. MODULE_LICENSE("Dual BSD/GPL");
  1796. module_init(vpu_init);
  1797. module_exit(vpu_exit);
  1798. static int vpu_pmu_enable(struct device *dev)
  1799. {
  1800. pm_runtime_set_active(dev);
  1801. pm_runtime_enable(dev);
  1802. return 0;
  1803. }
  1804. static void vpu_pmu_disable(struct device *dev)
  1805. {
  1806. pm_runtime_disable(dev);
  1807. pm_runtime_set_suspended(dev);
  1808. }
  1809. /* clk&reset for starfive jh7110*/
  1810. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1811. #define CLK_ENABLE_DATA 1
  1812. #define CLK_DISABLE_DATA 0
  1813. #define CLK_EN_SHIFT 31
  1814. #define CLK_EN_MASK 0x80000000U
  1815. #define SAIF_BD_APBS_BASE 0x13020000
  1816. #define WAVE511_CLK_AXI_CTRL 0x118U
  1817. #define WAVE511_CLK_BPU_CTRL 0x11cU
  1818. #define WAVE511_CLK_VCE_CTRL 0x120U
  1819. #define WAVE511_CLK_APB_CTRL 0x124U
  1820. #define WAVE511_CLK_NOCBUS_CTRL 0x130U
  1821. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1822. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1823. #define RSTN_AXI_MASK (0x1 << 15)
  1824. #define RSTN_BPU_MASK (0x1 << 16)
  1825. #define RSTN_VCE_MASK (0x1 << 17)
  1826. #define RSTN_APB_MASK (0x1 << 18)
  1827. #define RSTN_128B_AXIMEM_MASK (0x1 << 21)
  1828. static uint32_t saif_get_reg(const volatile void __iomem *addr,
  1829. uint32_t shift, uint32_t mask)
  1830. {
  1831. u32 tmp;
  1832. tmp = readl(addr);
  1833. tmp = (tmp & mask) >> shift;
  1834. return tmp;
  1835. }
  1836. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1837. uint32_t shift, uint32_t mask)
  1838. {
  1839. uint32_t tmp;
  1840. tmp = readl(addr);
  1841. tmp &= ~mask;
  1842. tmp |= (data << shift) & mask;
  1843. writel(tmp, addr);
  1844. }
  1845. static void saif_assert_rst(volatile void __iomem *addr,
  1846. const volatile void __iomem *addr_status, uint32_t mask)
  1847. {
  1848. uint32_t tmp;
  1849. tmp = readl(addr);
  1850. tmp |= mask;
  1851. writel(tmp, addr);
  1852. do {
  1853. tmp = readl(addr_status);
  1854. } while ((tmp & mask) != 0);
  1855. }
  1856. static void saif_clear_rst(volatile void __iomem *addr,
  1857. const volatile void __iomem *addr_status, uint32_t mask)
  1858. {
  1859. uint32_t tmp;
  1860. tmp = readl(addr);
  1861. tmp &= ~mask;
  1862. writel(tmp, addr);
  1863. do {
  1864. tmp = readl(addr_status);
  1865. } while ((tmp & mask) != mask);
  1866. }
  1867. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1868. {
  1869. if (enable)
  1870. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1871. else
  1872. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1873. }
  1874. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1875. {
  1876. if (enable) {
  1877. /*enable*/
  1878. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1879. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1880. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1881. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1882. /*clr-reset*/
  1883. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1884. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1885. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1886. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1887. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1888. } else {
  1889. /*assert-reset*/
  1890. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1891. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1892. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1893. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1894. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1895. /*disable*/
  1896. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1897. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1898. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1899. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1900. }
  1901. }
  1902. static void vpu_clk_reset(vpu_clk_t *clk)
  1903. {
  1904. /*assert-reset*/
  1905. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1906. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1907. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1908. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1909. /*clr-reset*/
  1910. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1911. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1912. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1913. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1914. }
  1915. int vpu_hw_reset(void)
  1916. {
  1917. if (!s_vpu_clk)
  1918. return -1;
  1919. vpu_clk_reset(s_vpu_clk);
  1920. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1921. return 0;
  1922. }
  1923. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1924. {
  1925. if (!pdev)
  1926. return -ENXIO;
  1927. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1928. if (IS_ERR(vpu_clk->clkgen)) {
  1929. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1930. return PTR_ERR(vpu_clk->clkgen);
  1931. }
  1932. /* clkgen define */
  1933. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
  1934. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
  1935. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
  1936. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
  1937. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
  1938. vpu_clk->en_mask = CLK_EN_MASK;
  1939. vpu_clk->en_shift = CLK_EN_SHIFT;
  1940. /* rstgen define */
  1941. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1942. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1943. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1944. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1945. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1946. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1947. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1948. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
  1949. vpu_clk->noc_ctrl = true;
  1950. return 0;
  1951. }
  1952. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1953. {
  1954. vpu_clk_t *vpu_clk;
  1955. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1956. if (!vpu_clk)
  1957. return NULL;
  1958. if (vpu_of_clk_get(pdev, vpu_clk))
  1959. goto err_get_clk;
  1960. return vpu_clk;
  1961. err_get_clk:
  1962. devm_kfree(&pdev->dev, vpu_clk);
  1963. return NULL;
  1964. }
  1965. static void vpu_clk_put(vpu_clk_t *clk)
  1966. {
  1967. if (clk->clkgen) {
  1968. iounmap(clk->clkgen);
  1969. clk->clkgen = NULL;
  1970. }
  1971. }
  1972. static int vpu_clk_enable(vpu_clk_t *clk)
  1973. {
  1974. if (clk == NULL || IS_ERR(clk))
  1975. return -1;
  1976. vpu_pmu_enable(clk->dev);
  1977. vpu_clk_control(clk, true);
  1978. if (clk->noc_ctrl == true)
  1979. vpu_noc_vdec_bus_control(clk, true);
  1980. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1981. return 0;
  1982. }
  1983. static void vpu_clk_disable(vpu_clk_t *clk)
  1984. {
  1985. if (clk == NULL || IS_ERR(clk))
  1986. return;
  1987. vpu_clk_control(clk, false);
  1988. vpu_pmu_disable(clk->dev);
  1989. if (clk->noc_ctrl == true)
  1990. vpu_noc_vdec_bus_control(clk, false);
  1991. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1992. }
  1993. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1994. int vpu_hw_reset(void)
  1995. {
  1996. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1997. /* sram do not need reset */
  1998. return reset_control_reset(s_vpu_clk->resets);
  1999. }
  2000. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  2001. {
  2002. struct device *dev = &pdev->dev;
  2003. int ret;
  2004. vpu_clk->dev = dev;
  2005. vpu_clk->clks = vpu_clks;
  2006. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  2007. vpu_clk->resets = devm_reset_control_array_get_shared(dev);
  2008. if (IS_ERR(vpu_clk->resets)) {
  2009. ret = PTR_ERR(vpu_clk->resets);
  2010. dev_err(dev, "faied to get vpu reset controls\n");
  2011. }
  2012. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  2013. if (ret)
  2014. dev_err(dev, "faied to get vpu clk controls\n");
  2015. if (device_property_read_bool(dev, "starfive,vdec_noc_ctrl"))
  2016. vpu_clk->noc_ctrl = true;
  2017. return 0;
  2018. }
  2019. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  2020. {
  2021. vpu_clk_t *vpu_clk;
  2022. if (!pdev)
  2023. return NULL;
  2024. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  2025. if (!vpu_clk)
  2026. return NULL;
  2027. if (vpu_of_clk_get(pdev, vpu_clk))
  2028. goto err_of_clk_get;
  2029. return vpu_clk;
  2030. err_of_clk_get:
  2031. devm_kfree(&pdev->dev, vpu_clk);
  2032. return NULL;
  2033. }
  2034. static void vpu_clk_put(vpu_clk_t *clk)
  2035. {
  2036. clk_bulk_put(clk->nr_clks, clk->clks);
  2037. }
  2038. static int vpu_clk_enable(vpu_clk_t *clk)
  2039. {
  2040. int ret;
  2041. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  2042. if (ret)
  2043. dev_err(clk->dev, "enable clk error.\n");
  2044. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  2045. return ret;
  2046. }
  2047. static void vpu_clk_disable(vpu_clk_t *clk)
  2048. {
  2049. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  2050. }
  2051. #endif