venc.c 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. //--=========================================================================--
  3. // This file is linux device driver for VPU.
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2015 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================-
  17. #include <linux/kernel.h>
  18. #include <linux/mm.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ioport.h>
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/wait.h>
  25. #include <linux/list.h>
  26. #include <linux/clk.h>
  27. #include <linux/delay.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/cdev.h>
  30. #include <linux/slab.h>
  31. #include <linux/sched.h>
  32. #include <linux/reset.h>
  33. #include <linux/version.h>
  34. #include <linux/of.h>
  35. #include <linux/pm_runtime.h>
  36. #include "../../../vpuapi/vpuconfig.h"
  37. #include "vpu.h"
  38. extern void sifive_ccache_flush_range(phys_addr_t start, size_t len);
  39. #ifndef CONFIG_PM
  40. #define CONFIG_PM
  41. #endif
  42. //#define ENABLE_DEBUG_MSG
  43. #ifdef ENABLE_DEBUG_MSG
  44. #define DPRINTK(args...) printk(KERN_INFO args);
  45. #else
  46. #define DPRINTK(args...)
  47. #endif
  48. /* definitions to be changed as customer configuration */
  49. /* if you want to have clock gating scheme frame by frame */
  50. //#define VPU_SUPPORT_CLOCK_CONTROL
  51. /* if clktree is work,try this...*/
  52. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  53. /* if the driver want to use interrupt service from kernel ISR */
  54. #define VPU_SUPPORT_ISR
  55. /* if the platform driver knows the name of this driver */
  56. /* VPU_PLATFORM_DEVICE_NAME */
  57. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  58. /* if this driver knows the dedicated video memory address */
  59. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  60. #define VPU_PLATFORM_DEVICE_NAME "venc"
  61. #define VPU_CLK_NAME "vcoenc"
  62. #define VPU_DEV_NAME "venc"
  63. /* if the platform driver knows this driver */
  64. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  65. //#define VPU_REG_BASE_ADDR 0x75000000
  66. #define VPU_REG_BASE_ADDR 0x130B0000
  67. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  68. #ifdef VPU_SUPPORT_ISR
  69. #define VPU_IRQ_NUM (15)
  70. #endif
  71. /* this definition is only for chipsnmedia FPGA board env */
  72. /* so for SOC env of customers can be ignored */
  73. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  74. # define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  75. #endif
  76. #ifdef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  77. typedef struct vpu_clkgen_t {
  78. void __iomem *en_ctrl;
  79. uint32_t rst_mask;
  80. } vpu_clkgen_t;
  81. struct clk_bulk_data vpu_clks[] = {
  82. { .id = "apb_clk" },
  83. { .id = "axi_clk" },
  84. { .id = "bpu_clk" },
  85. { .id = "vce_clk" },
  86. { .id = "noc_bus" },
  87. };
  88. #define FRAMSIZE_1080P (1920*1080)
  89. #define FRAMSIZE_720P (1280*720)
  90. #define FRAMSIZE_480P (720*480)
  91. struct vpu_devfreq_t {
  92. struct clk *axi_clk;
  93. struct clk *bpu_clk;
  94. struct clk *vce_clk;
  95. };
  96. enum VPU_DEV_FREQ {
  97. VPU_DEV_FREQ_80 = 80000000,
  98. VPU_DEV_FREQ_100 = 100000000,
  99. VPU_DEV_FREQ_150 = 150000000,
  100. VPU_DEV_FREQ_200 = 200000000,
  101. VPU_DEV_FREQ_237 = 237600000,
  102. VPU_DEV_FREQ_300 = 300000000,
  103. VPU_DEV_FREQ_MAX = VPU_DEV_FREQ_300,
  104. };
  105. enum VPU_DEV_FREQ_MODE {
  106. MODE_480P_30F,
  107. MODE_480P_60F,
  108. MODE_720P_30F,
  109. MODE_720P_60F,
  110. MODE_1080P_30F,
  111. MODE_MAX,
  112. };
  113. struct vpu_dev_freq_list {
  114. int mode;
  115. unsigned long axi_rate;
  116. unsigned long bpu_rate;
  117. unsigned long vce_rate;
  118. };
  119. typedef struct vpu_clk_t{
  120. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  121. void __iomem *clkgen;
  122. void __iomem *rst_ctrl;
  123. void __iomem *rst_status;
  124. void __iomem *noc_bus;
  125. uint32_t en_shift;
  126. uint32_t en_mask;
  127. vpu_clkgen_t apb_clk;
  128. vpu_clkgen_t axi_clk;
  129. vpu_clkgen_t bpu_clk;
  130. vpu_clkgen_t vce_clk;
  131. vpu_clkgen_t aximem_128b;
  132. #else
  133. struct clk_bulk_data *clks;
  134. struct reset_control *resets;
  135. struct vpu_devfreq_t vpu_devfreq;
  136. int nr_clks;
  137. #endif
  138. struct device *dev;
  139. bool noc_ctrl;
  140. }vpu_clk_t;
  141. #endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  142. struct device *vpu_dev;
  143. typedef struct vpu_drv_context_t {
  144. struct fasync_struct *async_queue;
  145. unsigned long interrupt_reason;
  146. u32 open_count; /*!<< device reference count. Not instance count */
  147. } vpu_drv_context_t;
  148. /* To track the allocated memory buffer */
  149. typedef struct vpudrv_buffer_pool_t {
  150. struct list_head list;
  151. struct vpudrv_buffer_t vb;
  152. struct file *filp;
  153. } vpudrv_buffer_pool_t;
  154. /* To track the instance index and buffer in instance pool */
  155. typedef struct vpudrv_instanace_list_t {
  156. struct list_head list;
  157. unsigned long inst_idx;
  158. unsigned long core_idx;
  159. struct file *filp;
  160. } vpudrv_instanace_list_t;
  161. typedef struct vpudrv_instance_pool_t {
  162. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  163. } vpudrv_instance_pool_t;
  164. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  165. # define VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE (62*1024*1024)
  166. # define VPU_DRAM_PHYSICAL_BASE 0x86C00000
  167. #include "vmm.h"
  168. static video_mm_t s_vmem;
  169. static vpudrv_buffer_t s_video_memory = {0};
  170. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  171. static int vpu_hw_reset(void);
  172. static void vpu_clk_disable(vpu_clk_t *clk);
  173. static int vpu_clk_enable(vpu_clk_t *clk);
  174. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  175. static void vpu_clk_put(vpu_clk_t *clk);
  176. static int vpu_pmu_enable(struct device *dev);
  177. static void vpu_pmu_disable(struct device *dev);
  178. static int vpu_devfreq_select(struct vpudrv_devfreq_info_t *info);
  179. /* end customer definition */
  180. static vpudrv_buffer_t s_instance_pool = {0};
  181. static vpudrv_buffer_t s_common_memory = {0};
  182. static vpu_drv_context_t s_vpu_drv_context;
  183. static dev_t s_vpu_devt;
  184. static int s_vpu_major;
  185. static struct cdev s_vpu_cdev;
  186. static struct class *s_vpu_class;
  187. static struct vpu_clk_t *s_vpu_clk;
  188. static int s_vpu_open_ref_count;
  189. #ifdef VPU_SUPPORT_ISR
  190. static int s_vpu_irq = VPU_IRQ_NUM;
  191. #endif
  192. static vpudrv_buffer_t s_vpu_register = {0};
  193. static int s_interrupt_flag;
  194. static wait_queue_head_t s_interrupt_wait_q;
  195. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  196. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  197. static DECLARE_MUTEX(s_vpu_sem);
  198. #else
  199. static DEFINE_SEMAPHORE(s_vpu_sem);
  200. #endif
  201. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  202. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  203. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  204. #ifdef CONFIG_PM
  205. /* implement to power management functions */
  206. #define BIT_BASE 0x0000
  207. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  208. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  209. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  210. #define BIT_INT_STS (BIT_BASE + 0x010)
  211. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  212. #define BIT_INT_REASON (BIT_BASE + 0x174)
  213. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  214. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  215. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  216. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  217. /* WAVE4 registers */
  218. #define W4_REG_BASE 0x0000
  219. #define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070)
  220. #define W4_VPU_INT_REASON_CLEAR (W4_REG_BASE + 0x0034)
  221. #define W4_VPU_VINT_CLEAR (W4_REG_BASE + 0x003C)
  222. #define W4_VPU_VPU_INT_STS (W4_REG_BASE + 0x0044)
  223. #define W4_VPU_INT_REASON (W4_REG_BASE + 0x004c)
  224. #define W4_RET_SUCCESS (W4_REG_BASE + 0x0110)
  225. #define W4_RET_FAIL_REASON (W4_REG_BASE + 0x0114)
  226. /* WAVE4 INIT, WAKEUP */
  227. #define W4_PO_CONF (W4_REG_BASE + 0x0000)
  228. #define W4_VCPU_CUR_PC (W4_REG_BASE + 0x0004)
  229. #define W4_VPU_VINT_ENABLE (W4_REG_BASE + 0x0048)
  230. #define W4_VPU_RESET_REQ (W4_REG_BASE + 0x0050)
  231. #define W4_VPU_RESET_STATUS (W4_REG_BASE + 0x0054)
  232. #define W4_VPU_REMAP_CTRL (W4_REG_BASE + 0x0060)
  233. #define W4_VPU_REMAP_VADDR (W4_REG_BASE + 0x0064)
  234. #define W4_VPU_REMAP_PADDR (W4_REG_BASE + 0x0068)
  235. #define W4_VPU_REMAP_CORE_START (W4_REG_BASE + 0x006C)
  236. #define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070)
  237. #define W4_REMAP_CODE_INDEX 0
  238. enum {
  239. W4_INT_INIT_VPU = 0,
  240. W4_INT_DEC_PIC_HDR = 1,
  241. W4_INT_FINI_SEQ = 2,
  242. W4_INT_DEC_PIC = 3,
  243. W4_INT_SET_FRAMEBUF = 4,
  244. W4_INT_FLUSH_DEC = 5,
  245. W4_INT_GET_FW_VERSION = 9,
  246. W4_INT_QUERY_DEC = 10,
  247. W4_INT_SLEEP_VPU = 11,
  248. W4_INT_WAKEUP_VPU = 12,
  249. W4_INT_CHANGE_INT = 13,
  250. W4_INT_CREATE_INSTANCE = 14,
  251. W4_INT_BSBUF_EMPTY = 15, /*!<< Bitstream buffer empty */
  252. W4_INT_ENC_SLICE_INT = 15,
  253. };
  254. enum {
  255. W5_INT_INIT_VPU = 0,
  256. W5_INT_WAKEUP_VPU = 1,
  257. W5_INT_SLEEP_VPU = 2,
  258. W5_INT_CREATE_INSTANCE = 3,
  259. W5_INT_FLUSH_INSTANCE = 4,
  260. W5_INT_DESTORY_INSTANCE = 5,
  261. W5_INT_INIT_SEQ = 6,
  262. W5_INT_SET_FRAMEBUF = 7,
  263. W5_INT_DEC_PIC = 8,
  264. W5_INT_ENC_PIC = 8,
  265. W5_INT_ENC_SET_PARAM = 9,
  266. W5_INT_DEC_QUERY = 14,
  267. W5_INT_BSBUF_EMPTY = 15,
  268. };
  269. #define W4_HW_OPTION (W4_REG_BASE + 0x0124)
  270. #define W4_CODE_SIZE (W4_REG_BASE + 0x011C)
  271. /* Note: W4_INIT_CODE_BASE_ADDR should be aligned to 4KB */
  272. #define W4_ADDR_CODE_BASE (W4_REG_BASE + 0x0118)
  273. #define W4_CODE_PARAM (W4_REG_BASE + 0x0120)
  274. #define W4_INIT_VPU_TIME_OUT_CNT (W4_REG_BASE + 0x0134)
  275. /* WAVE5 registers */
  276. #define W5_ADDR_CODE_BASE (W4_REG_BASE + 0x0110)
  277. #define W5_CODE_SIZE (W4_REG_BASE + 0x0114)
  278. #define W5_CODE_PARAM (W4_REG_BASE + 0x0128)
  279. #define W5_INIT_VPU_TIME_OUT_CNT (W4_REG_BASE + 0x0130)
  280. #define W5_HW_OPTION (W4_REG_BASE + 0x012C)
  281. #define W5_RET_SUCCESS (W4_REG_BASE + 0x0108)
  282. /* WAVE4 Wave4BitIssueCommand */
  283. #define W4_CORE_INDEX (W4_REG_BASE + 0x0104)
  284. #define W4_INST_INDEX (W4_REG_BASE + 0x0108)
  285. #define W4_COMMAND (W4_REG_BASE + 0x0100)
  286. #define W4_VPU_HOST_INT_REQ (W4_REG_BASE + 0x0038)
  287. /* Product register */
  288. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  289. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  290. #endif
  291. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  292. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  293. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  294. static void starfive_flush_dcache(phys_addr_t start, size_t len)
  295. {
  296. #ifdef ARCH_HAS_SYNC_DMA_FOR_DEVICE
  297. dma_sync_single_for_device(vpu_dev, start, len, DMA_FROM_DEVICE);
  298. #else
  299. sifive_ccache_flush_range(start, len);
  300. #endif
  301. }
  302. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  303. {
  304. if (!vb)
  305. return -1;
  306. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  307. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  308. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  309. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  310. return -1;
  311. }
  312. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  313. #else
  314. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  315. if ((void *)(vb->base) == NULL) {
  316. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  317. return -1;
  318. }
  319. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  320. #endif
  321. return 0;
  322. }
  323. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  324. {
  325. if (!vb)
  326. return;
  327. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  328. if (vb->base)
  329. vmem_free(&s_vmem, vb->phys_addr, 0);
  330. #else
  331. if (vb->base)
  332. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  333. #endif
  334. }
  335. static int vpu_free_instances(struct file *filp)
  336. {
  337. vpudrv_instanace_list_t *vil, *n;
  338. vpudrv_instance_pool_t *vip;
  339. void *vip_base;
  340. int instance_pool_size_per_core;
  341. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  342. void *vdi_mutexes_base;
  343. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  344. #endif
  345. DPRINTK("[VPUDRV] vpu_free_instances\n");
  346. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  347. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  348. {
  349. if (vil->filp == filp) {
  350. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  351. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  352. vip = (vpudrv_instance_pool_t *)vip_base;
  353. if (vip) {
  354. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  355. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  356. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  357. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  358. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  359. if (vdi_mutexes_base) {
  360. int i;
  361. for (i = 0; i < 4; i++) {
  362. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  363. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  364. }
  365. }
  366. #endif
  367. }
  368. s_vpu_open_ref_count--;
  369. list_del(&vil->list);
  370. kfree(vil);
  371. }
  372. }
  373. return 1;
  374. }
  375. static int vpu_free_buffers(struct file *filp)
  376. {
  377. vpudrv_buffer_pool_t *pool, *n;
  378. vpudrv_buffer_t vb;
  379. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  380. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  381. {
  382. if (pool->filp == filp) {
  383. vb = pool->vb;
  384. if (vb.base) {
  385. vpu_free_dma_buffer(&vb);
  386. list_del(&pool->list);
  387. kfree(pool);
  388. }
  389. }
  390. }
  391. return 0;
  392. }
  393. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  394. {
  395. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  396. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  397. int core;
  398. int product_code;
  399. DPRINTK("[VPUDRV][+]%s\n", __func__);
  400. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  401. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  402. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  403. continue;
  404. }
  405. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  406. if (PRODUCT_CODE_W_SERIES(product_code)) {
  407. if (ReadVpuRegister(W4_VPU_VPU_INT_STS)) {
  408. dev->interrupt_reason = ReadVpuRegister(W4_VPU_INT_REASON);
  409. WriteVpuRegister(W4_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  410. WriteVpuRegister(W4_VPU_VINT_CLEAR, 0x1);
  411. }
  412. }
  413. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  414. if (ReadVpuRegister(BIT_INT_STS)) {
  415. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  416. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  417. }
  418. }
  419. else {
  420. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  421. continue;
  422. }
  423. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08lx\n", product_code, dev->interrupt_reason);
  424. }
  425. if (dev->async_queue)
  426. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  427. s_interrupt_flag = 1;
  428. wake_up_interruptible(&s_interrupt_wait_q);
  429. DPRINTK("[VPUDRV][-]%s\n", __func__);
  430. return IRQ_HANDLED;
  431. }
  432. static int vpu_open(struct inode *inode, struct file *filp)
  433. {
  434. DPRINTK("[VPUDRV][+] %s\n", __func__);
  435. pm_runtime_get_sync(s_vpu_clk->dev);
  436. vpu_hw_reset();
  437. spin_lock(&s_vpu_lock);
  438. s_vpu_drv_context.open_count++;
  439. filp->private_data = (void *)(&s_vpu_drv_context);
  440. spin_unlock(&s_vpu_lock);
  441. DPRINTK("[VPUDRV][-] %s\n", __func__);
  442. return 0;
  443. }
  444. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  445. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  446. {
  447. int ret = 0;
  448. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  449. switch (cmd) {
  450. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  451. {
  452. vpudrv_buffer_pool_t *vbp;
  453. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  454. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  455. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  456. if (!vbp) {
  457. up(&s_vpu_sem);
  458. return -ENOMEM;
  459. }
  460. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  461. if (ret) {
  462. kfree(vbp);
  463. up(&s_vpu_sem);
  464. return -EFAULT;
  465. }
  466. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  467. if (ret == -1) {
  468. ret = -ENOMEM;
  469. kfree(vbp);
  470. up(&s_vpu_sem);
  471. break;
  472. }
  473. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  474. if (ret) {
  475. kfree(vbp);
  476. ret = -EFAULT;
  477. up(&s_vpu_sem);
  478. break;
  479. }
  480. vbp->filp = filp;
  481. spin_lock(&s_vpu_lock);
  482. list_add(&vbp->list, &s_vbp_head);
  483. spin_unlock(&s_vpu_lock);
  484. up(&s_vpu_sem);
  485. }
  486. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  487. }
  488. break;
  489. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  490. {
  491. vpudrv_buffer_pool_t *vbp, *n;
  492. vpudrv_buffer_t vb;
  493. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  494. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  495. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  496. if (ret) {
  497. up(&s_vpu_sem);
  498. return -EACCES;
  499. }
  500. if (vb.base)
  501. vpu_free_dma_buffer(&vb);
  502. spin_lock(&s_vpu_lock);
  503. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  504. {
  505. if (vbp->vb.base == vb.base) {
  506. list_del(&vbp->list);
  507. kfree(vbp);
  508. break;
  509. }
  510. }
  511. spin_unlock(&s_vpu_lock);
  512. up(&s_vpu_sem);
  513. }
  514. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  515. }
  516. break;
  517. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  518. {
  519. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  520. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  521. if (s_video_memory.base != 0) {
  522. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  523. if (ret != 0)
  524. ret = -EFAULT;
  525. } else {
  526. ret = -EFAULT;
  527. }
  528. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  529. #endif
  530. }
  531. break;
  532. case VDI_IOCTL_WAIT_INTERRUPT:
  533. {
  534. vpudrv_intr_info_t info;
  535. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  536. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  537. if (ret != 0)
  538. return -EFAULT;
  539. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  540. if (!ret) {
  541. ret = -ETIME;
  542. break;
  543. }
  544. if (signal_pending(current)) {
  545. ret = -ERESTARTSYS;
  546. break;
  547. }
  548. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  549. info.intr_reason = dev->interrupt_reason;
  550. s_interrupt_flag = 0;
  551. dev->interrupt_reason = 0;
  552. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  553. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  554. if (ret != 0)
  555. return -EFAULT;
  556. }
  557. break;
  558. case VDI_IOCTL_SET_CLOCK_GATE:
  559. {
  560. u32 clkgate;
  561. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  562. if (get_user(clkgate, (u32 __user *) arg))
  563. return -EFAULT;
  564. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  565. if (clkgate)
  566. vpu_clk_enable(s_vpu_clk);
  567. else
  568. vpu_clk_disable(s_vpu_clk);
  569. #endif
  570. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  571. }
  572. break;
  573. case VDI_IOCTL_GET_INSTANCE_POOL:
  574. {
  575. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  576. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  577. if (s_instance_pool.base != 0) {
  578. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  579. if (ret != 0)
  580. ret = -EFAULT;
  581. } else {
  582. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  583. if (ret == 0) {
  584. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  585. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  586. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  587. s_instance_pool.phys_addr = s_instance_pool.base;
  588. if (s_instance_pool.base != 0)
  589. #else
  590. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  591. #endif
  592. {
  593. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  594. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  595. if (ret == 0) {
  596. /* success to get memory for instance pool */
  597. up(&s_vpu_sem);
  598. break;
  599. }
  600. }
  601. }
  602. ret = -EFAULT;
  603. }
  604. up(&s_vpu_sem);
  605. }
  606. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  607. }
  608. break;
  609. case VDI_IOCTL_GET_COMMON_MEMORY:
  610. {
  611. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  612. if (s_common_memory.base != 0) {
  613. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  614. if (ret != 0)
  615. ret = -EFAULT;
  616. } else {
  617. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  618. if (ret == 0) {
  619. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  620. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  621. if (ret == 0) {
  622. /* success to get memory for common memory */
  623. break;
  624. }
  625. }
  626. }
  627. ret = -EFAULT;
  628. }
  629. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  630. }
  631. break;
  632. case VDI_IOCTL_OPEN_INSTANCE:
  633. {
  634. vpudrv_inst_info_t inst_info;
  635. vpudrv_instanace_list_t *vil, *n;
  636. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  637. if (!vil)
  638. return -ENOMEM;
  639. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  640. return -EFAULT;
  641. vil->inst_idx = inst_info.inst_idx;
  642. vil->core_idx = inst_info.core_idx;
  643. vil->filp = filp;
  644. spin_lock(&s_vpu_lock);
  645. list_add(&vil->list, &s_inst_list_head);
  646. inst_info.inst_open_count = 0; /* counting the current open instance number */
  647. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  648. {
  649. if (vil->core_idx == inst_info.core_idx)
  650. inst_info.inst_open_count++;
  651. }
  652. spin_unlock(&s_vpu_lock);
  653. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  654. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  655. kfree(vil);
  656. return -EFAULT;
  657. }
  658. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  659. }
  660. break;
  661. case VDI_IOCTL_CLOSE_INSTANCE:
  662. {
  663. vpudrv_inst_info_t inst_info;
  664. vpudrv_instanace_list_t *vil, *n;
  665. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  666. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  667. return -EFAULT;
  668. spin_lock(&s_vpu_lock);
  669. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  670. {
  671. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  672. list_del(&vil->list);
  673. kfree(vil);
  674. break;
  675. }
  676. }
  677. inst_info.inst_open_count = 0; /* counting the current open instance number */
  678. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  679. {
  680. if (vil->core_idx == inst_info.core_idx)
  681. inst_info.inst_open_count++;
  682. }
  683. spin_unlock(&s_vpu_lock);
  684. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  685. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  686. return -EFAULT;
  687. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  688. }
  689. break;
  690. case VDI_IOCTL_GET_INSTANCE_NUM:
  691. {
  692. vpudrv_inst_info_t inst_info;
  693. vpudrv_instanace_list_t *vil, *n;
  694. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  695. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  696. if (ret != 0)
  697. break;
  698. inst_info.inst_open_count = 0;
  699. spin_lock(&s_vpu_lock);
  700. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  701. {
  702. if (vil->core_idx == inst_info.core_idx)
  703. inst_info.inst_open_count++;
  704. }
  705. spin_unlock(&s_vpu_lock);
  706. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  707. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  708. }
  709. break;
  710. case VDI_IOCTL_RESET:
  711. {
  712. vpu_hw_reset();
  713. }
  714. break;
  715. case VDI_IOCTL_GET_REGISTER_INFO:
  716. {
  717. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  718. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  719. if (ret != 0)
  720. ret = -EFAULT;
  721. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  722. }
  723. break;
  724. case VDI_IOCTL_FLUSH_DCACHE:
  725. {
  726. vpudrv_flush_cache_t cache_info;
  727. DPRINTK("[JPUDRV][+]VDI_IOCTL_FLUSH_DCACHE\n");
  728. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  729. if (ret != 0)
  730. ret = -EFAULT;
  731. if(cache_info.flag)
  732. starfive_flush_dcache(cache_info.start,cache_info.size);
  733. DPRINTK("[JPUDRV][-]VDI_IOCTL_FLUSH_DCACHE\n");
  734. break;
  735. }
  736. case VDI_IOCTL_DEVFREQ_SET:
  737. {
  738. vpudrv_devfreq_info_t devfreq_info;
  739. ret = copy_from_user(&devfreq_info, (vpudrv_devfreq_info_t *)arg, sizeof(vpudrv_devfreq_info_t));
  740. if (ret != 0)
  741. ret = -EFAULT;
  742. vpu_devfreq_select(&devfreq_info);
  743. break;
  744. }
  745. default:
  746. {
  747. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  748. }
  749. break;
  750. }
  751. return ret;
  752. }
  753. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  754. {
  755. return -1;
  756. }
  757. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  758. {
  759. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  760. if (!buf) {
  761. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  762. return -EFAULT;
  763. }
  764. if (len == sizeof(vpu_bit_firmware_info_t)) {
  765. vpu_bit_firmware_info_t *bit_firmware_info;
  766. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  767. if (!bit_firmware_info) {
  768. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  769. return -EFAULT;
  770. }
  771. if (copy_from_user(bit_firmware_info, buf, len)) {
  772. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  773. return -EFAULT;
  774. }
  775. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  776. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  777. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  778. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  779. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  780. return -ENODEV;
  781. }
  782. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  783. kfree(bit_firmware_info);
  784. return len;
  785. }
  786. kfree(bit_firmware_info);
  787. }
  788. return -1;
  789. }
  790. static int vpu_release(struct inode *inode, struct file *filp)
  791. {
  792. int ret = 0;
  793. DPRINTK("[VPUDRV] vpu_release\n");
  794. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  795. /* found and free the not handled buffer by user applications */
  796. vpu_free_buffers(filp);
  797. /* found and free the not closed instance by user applications */
  798. vpu_free_instances(filp);
  799. s_vpu_drv_context.open_count--;
  800. if (s_vpu_drv_context.open_count == 0) {
  801. if (s_instance_pool.base) {
  802. DPRINTK("[VPUDRV] free instance pool\n");
  803. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  804. vfree((const void *)s_instance_pool.base);
  805. #else
  806. vpu_free_dma_buffer(&s_instance_pool);
  807. #endif
  808. s_instance_pool.base = 0;
  809. }
  810. if (s_common_memory.base) {
  811. DPRINTK("[VPUDRV] free common memory\n");
  812. vpu_free_dma_buffer(&s_common_memory);
  813. s_common_memory.base = 0;
  814. }
  815. }
  816. }
  817. up(&s_vpu_sem);
  818. pm_runtime_put_sync(s_vpu_clk->dev);
  819. return 0;
  820. }
  821. static int vpu_fasync(int fd, struct file *filp, int mode)
  822. {
  823. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  824. return fasync_helper(fd, filp, mode, &dev->async_queue);
  825. }
  826. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  827. {
  828. unsigned long pfn;
  829. vm->vm_flags |= VM_IO | VM_RESERVED;
  830. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  831. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  832. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  833. }
  834. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  835. {
  836. vm->vm_flags |= VM_IO | VM_RESERVED;
  837. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  838. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  839. }
  840. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  841. {
  842. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  843. int ret;
  844. long length = vm->vm_end - vm->vm_start;
  845. unsigned long start = vm->vm_start;
  846. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  847. unsigned long pfn;
  848. vm->vm_flags |= VM_RESERVED;
  849. /* loop over all pages, map it page individually */
  850. while (length > 0)
  851. {
  852. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  853. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  854. return ret;
  855. }
  856. start += PAGE_SIZE;
  857. vmalloc_area_ptr += PAGE_SIZE;
  858. length -= PAGE_SIZE;
  859. }
  860. return 0;
  861. #else
  862. vm->vm_flags |= VM_RESERVED;
  863. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  864. #endif
  865. }
  866. /*!
  867. * @brief memory map interface for vpu file operation
  868. * @return 0 on success or negative error code on error
  869. */
  870. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  871. {
  872. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  873. if (vm->vm_pgoff == 0)
  874. return vpu_map_to_instance_pool_memory(fp, vm);
  875. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  876. return vpu_map_to_register(fp, vm);
  877. return vpu_map_to_physical_memory(fp, vm);
  878. #else
  879. if (vm->vm_pgoff) {
  880. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  881. return vpu_map_to_instance_pool_memory(fp, vm);
  882. return vpu_map_to_physical_memory(fp, vm);
  883. } else {
  884. return vpu_map_to_register(fp, vm);
  885. }
  886. #endif
  887. }
  888. struct file_operations vpu_fops = {
  889. .owner = THIS_MODULE,
  890. .open = vpu_open,
  891. .read = vpu_read,
  892. .write = vpu_write,
  893. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  894. .unlocked_ioctl = vpu_ioctl,
  895. .release = vpu_release,
  896. .fasync = vpu_fasync,
  897. .mmap = vpu_mmap,
  898. };
  899. static int vpu_probe(struct platform_device *pdev)
  900. {
  901. int err = 0;
  902. struct resource *res = NULL;
  903. struct device *devices;
  904. int irq = -1;
  905. DPRINTK("[VPUDRV] vpu_probe\n");
  906. if(pdev){
  907. vpu_dev = &pdev->dev;
  908. vpu_dev->coherent_dma_mask = 0xffffffff;
  909. }
  910. if (pdev)
  911. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  912. if (res) {/* if platform driver is implemented */
  913. s_vpu_register.phys_addr = res->start;
  914. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  915. s_vpu_register.size = res->end - res->start;
  916. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  917. } else {
  918. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  919. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  920. s_vpu_register.size = VPU_REG_SIZE;
  921. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  922. }
  923. /* get the major number of the character device */
  924. if ((alloc_chrdev_region(&s_vpu_devt, 0, 1, VPU_DEV_NAME)) < 0) {
  925. err = -EBUSY;
  926. printk(KERN_ERR "could not allocate major number\n");
  927. goto ERROR_PROVE_DEVICE;
  928. }
  929. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  930. s_vpu_major = MAJOR(s_vpu_devt);
  931. /* initialize the device structure and register the device with the kernel */
  932. cdev_init(&s_vpu_cdev, &vpu_fops);
  933. if ((cdev_add(&s_vpu_cdev, s_vpu_devt, 1)) < 0) {
  934. err = -EBUSY;
  935. printk(KERN_ERR "could not allocate chrdev\n");
  936. goto ERROR_PROVE_DEVICE;
  937. }
  938. s_vpu_class = class_create(THIS_MODULE, VPU_DEV_NAME);
  939. if (IS_ERR(s_vpu_class)) {
  940. dev_err(vpu_dev, "class creat error.\n");
  941. goto ERROR_CRART_CLASS;
  942. }
  943. devices = device_create(s_vpu_class, 0, MKDEV(s_vpu_major, 0),
  944. NULL, VPU_DEV_NAME);
  945. if (IS_ERR(devices)) {
  946. dev_err(vpu_dev, "device creat error.\n");
  947. goto ERROR_CREAT_DEVICE;
  948. }
  949. if (pdev)
  950. s_vpu_clk = vpu_clk_get(pdev);
  951. else
  952. s_vpu_clk = vpu_clk_get(NULL);
  953. if (!s_vpu_clk)
  954. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  955. else
  956. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  957. vpu_pmu_enable(s_vpu_clk->dev);
  958. vpu_clk_enable(s_vpu_clk);
  959. reset_control_deassert(s_vpu_clk->resets);
  960. #ifdef VPU_SUPPORT_ISR
  961. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  962. if (pdev)
  963. irq = platform_get_irq(pdev, 0);
  964. if (irq >= 0) {/* if platform driver is implemented */
  965. s_vpu_irq = irq;
  966. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  967. } else {
  968. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  969. }
  970. #else
  971. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  972. #endif
  973. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, "VPU_CODEC_IRQ", (void *)(&s_vpu_drv_context));
  974. if (err) {
  975. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  976. goto ERROR_PROVE_DEVICE;
  977. }
  978. #endif
  979. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  980. s_video_memory.size = VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE;
  981. s_video_memory.phys_addr = VPU_DRAM_PHYSICAL_BASE;
  982. s_video_memory.base = (unsigned long)ioremap_nocache(s_video_memory.phys_addr, PAGE_ALIGN(s_video_memory.size));
  983. if (!s_video_memory.base) {
  984. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr==0x%lx, base==0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  985. goto ERROR_PROVE_DEVICE;
  986. }
  987. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  988. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  989. goto ERROR_PROVE_DEVICE;
  990. }
  991. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr==0x%lx, base = =0x%lx\n", s_video_memory.phys_addr, s_video_memory.base);
  992. #else
  993. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  994. #endif
  995. return 0;
  996. ERROR_CREAT_DEVICE:
  997. class_destroy(s_vpu_class);
  998. ERROR_CRART_CLASS:
  999. cdev_del(&s_vpu_cdev);
  1000. ERROR_PROVE_DEVICE:
  1001. if (s_vpu_major)
  1002. unregister_chrdev_region(s_vpu_major, 1);
  1003. if (s_vpu_register.virt_addr)
  1004. iounmap((void *)s_vpu_register.virt_addr);
  1005. return err;
  1006. }
  1007. static int vpu_remove(struct platform_device *pdev)
  1008. {
  1009. DPRINTK("[VPUDRV] vpu_remove\n");
  1010. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1011. if (s_instance_pool.base) {
  1012. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1013. vfree((const void *)s_instance_pool.base);
  1014. #else
  1015. vpu_free_dma_buffer(&s_instance_pool);
  1016. #endif
  1017. s_instance_pool.base = 0;
  1018. }
  1019. if (s_common_memory.base) {
  1020. vpu_free_dma_buffer(&s_common_memory);
  1021. s_common_memory.base = 0;
  1022. }
  1023. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1024. if (s_video_memory.base) {
  1025. iounmap((void *)s_video_memory.base);
  1026. s_video_memory.base = 0;
  1027. vmem_exit(&s_vmem);
  1028. }
  1029. #endif
  1030. if (s_vpu_major > 0) {
  1031. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1032. class_destroy(s_vpu_class);
  1033. cdev_del(&s_vpu_cdev);
  1034. unregister_chrdev_region(s_vpu_devt, 1);
  1035. s_vpu_major = 0;
  1036. }
  1037. #ifdef VPU_SUPPORT_ISR
  1038. if (s_vpu_irq)
  1039. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1040. #endif
  1041. if (s_vpu_register.virt_addr)
  1042. iounmap((void *)s_vpu_register.virt_addr);
  1043. vpu_clk_put(s_vpu_clk);
  1044. vpu_pmu_disable(&pdev->dev);
  1045. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1046. return 0;
  1047. }
  1048. #ifdef CONFIG_PM
  1049. #define W4_MAX_CODE_BUF_SIZE (512*1024)
  1050. #define W4_CMD_INIT_VPU (0x0001)
  1051. #define W4_CMD_SLEEP_VPU (0x0400)
  1052. #define W4_CMD_WAKEUP_VPU (0x0800)
  1053. #define W5_CMD_SLEEP_VPU (0x0004)
  1054. #define W5_CMD_WAKEUP_VPU (0x0002)
  1055. static void Wave4BitIssueCommand(int core, u32 cmd)
  1056. {
  1057. WriteVpuRegister(W4_VPU_BUSY_STATUS, 1);
  1058. WriteVpuRegister(W4_CORE_INDEX, 0);
  1059. /* coreIdx = ReadVpuRegister(W4_VPU_BUSY_STATUS);*/
  1060. /* coreIdx = 0;*/
  1061. /* WriteVpuRegister(W4_INST_INDEX, (instanceIndex&0xffff)|(codecMode<<16));*/
  1062. WriteVpuRegister(W4_COMMAND, cmd);
  1063. WriteVpuRegister(W4_VPU_HOST_INT_REQ, 1);
  1064. return;
  1065. }
  1066. static int __maybe_unused vpu_runtime_suspend(struct device *dev)
  1067. {
  1068. reset_control_assert(s_vpu_clk->resets);
  1069. vpu_clk_disable(s_vpu_clk);
  1070. return 0;
  1071. }
  1072. static int __maybe_unused vpu_runtime_resume(struct device *dev)
  1073. {
  1074. vpu_clk_enable(s_vpu_clk);
  1075. return reset_control_deassert(s_vpu_clk->resets);
  1076. }
  1077. #ifdef CONFIG_PM_SLEEP
  1078. static int __maybe_unused vpu_suspend(struct device *dev)
  1079. {
  1080. int i;
  1081. int core;
  1082. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1083. int product_code;
  1084. DPRINTK("[VPUDRV] vpu_suspend\n");
  1085. pm_runtime_get_sync(dev);
  1086. if (s_vpu_open_ref_count > 0) {
  1087. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1088. if (s_bit_firmware_info[core].size == 0)
  1089. continue;
  1090. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1091. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1092. unsigned long cmd_reg = W4_CMD_SLEEP_VPU;
  1093. unsigned long suc_reg = W4_RET_SUCCESS;
  1094. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1095. if (time_after(jiffies, timeout)) {
  1096. DPRINTK("SLEEP_VPU BUSY timeout");
  1097. goto DONE_SUSPEND;
  1098. }
  1099. }
  1100. if (product_code == WAVE512_CODE || product_code == WAVE520_CODE) {
  1101. cmd_reg = W5_CMD_SLEEP_VPU;
  1102. suc_reg = W5_RET_SUCCESS;
  1103. }
  1104. Wave4BitIssueCommand(core, cmd_reg);
  1105. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1106. if (time_after(jiffies, timeout)) {
  1107. DPRINTK("SLEEP_VPU BUSY timeout");
  1108. goto DONE_SUSPEND;
  1109. }
  1110. }
  1111. if (ReadVpuRegister(suc_reg) == 0) {
  1112. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W4_RET_FAIL_REASON));
  1113. goto DONE_SUSPEND;
  1114. }
  1115. }
  1116. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1117. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1118. if (time_after(jiffies, timeout))
  1119. goto DONE_SUSPEND;
  1120. }
  1121. for (i = 0; i < 64; i++)
  1122. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1123. }
  1124. else {
  1125. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1126. goto DONE_SUSPEND;
  1127. }
  1128. }
  1129. }
  1130. DONE_SUSPEND:
  1131. pm_runtime_put_sync(dev);
  1132. pm_runtime_force_suspend(dev);
  1133. return 0;
  1134. }
  1135. static int __maybe_unused vpu_resume(struct device *dev)
  1136. {
  1137. int i;
  1138. int core;
  1139. u32 val;
  1140. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1141. int product_code;
  1142. unsigned long code_base;
  1143. u32 code_size;
  1144. u32 remap_size;
  1145. int regVal;
  1146. u32 hwOption = 0;
  1147. DPRINTK("[VPUDRV] vpu_resume\n");
  1148. pm_runtime_force_resume(dev);
  1149. pm_runtime_get_sync(dev);
  1150. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1151. if (s_bit_firmware_info[core].size == 0) {
  1152. continue;
  1153. }
  1154. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1155. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1156. unsigned long addr_code_base_reg = W4_ADDR_CODE_BASE;
  1157. unsigned long code_size_reg = W4_CODE_SIZE;
  1158. unsigned long code_param_reg = W4_CODE_PARAM;
  1159. unsigned long timeout_cnt_reg = W4_INIT_VPU_TIME_OUT_CNT;
  1160. unsigned long hw_opt_reg = W4_HW_OPTION;
  1161. unsigned long suc_reg = W4_RET_SUCCESS;
  1162. if (product_code == WAVE512_CODE || product_code == WAVE520_CODE) {
  1163. addr_code_base_reg = W5_ADDR_CODE_BASE;
  1164. code_size_reg = W5_CODE_SIZE;
  1165. code_param_reg = W5_CODE_PARAM;
  1166. timeout_cnt_reg = W5_INIT_VPU_TIME_OUT_CNT;
  1167. hw_opt_reg = W5_HW_OPTION;
  1168. suc_reg = W5_RET_SUCCESS;
  1169. }
  1170. code_base = s_common_memory.phys_addr;
  1171. /* ALIGN TO 4KB */
  1172. code_size = (W4_MAX_CODE_BUF_SIZE&~0xfff);
  1173. if (code_size < s_bit_firmware_info[core].size*2) {
  1174. goto DONE_WAKEUP;
  1175. }
  1176. regVal = 0;
  1177. WriteVpuRegister(W4_PO_CONF, regVal);
  1178. /* Reset All blocks */
  1179. regVal = 0x7ffffff;
  1180. WriteVpuRegister(W4_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1181. /* Waiting reset done */
  1182. while (ReadVpuRegister(W4_VPU_RESET_STATUS)) {
  1183. if (time_after(jiffies, timeout))
  1184. goto DONE_WAKEUP;
  1185. }
  1186. WriteVpuRegister(W4_VPU_RESET_REQ, 0);
  1187. /* remap page size */
  1188. remap_size = (code_size >> 12) & 0x1ff;
  1189. regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1190. WriteVpuRegister(W4_VPU_REMAP_CTRL, regVal);
  1191. WriteVpuRegister(W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  1192. WriteVpuRegister(W4_VPU_REMAP_PADDR, code_base);
  1193. WriteVpuRegister(addr_code_base_reg, code_base);
  1194. WriteVpuRegister(code_size_reg, code_size);
  1195. WriteVpuRegister(code_param_reg, 0);
  1196. WriteVpuRegister(timeout_cnt_reg, timeout);
  1197. WriteVpuRegister(hw_opt_reg, hwOption);
  1198. /* Interrupt */
  1199. if (product_code == WAVE512_CODE) {
  1200. // decoder
  1201. regVal = (1<<W5_INT_INIT_SEQ);
  1202. regVal |= (1<<W5_INT_DEC_PIC);
  1203. regVal |= (1<<W5_INT_BSBUF_EMPTY);
  1204. }
  1205. else if (product_code == WAVE520_CODE) {
  1206. regVal = (1<<W5_INT_ENC_SET_PARAM);
  1207. regVal |= (1<<W5_INT_ENC_PIC);
  1208. }
  1209. else {
  1210. regVal = (1<<W4_INT_DEC_PIC_HDR);
  1211. regVal |= (1<<W4_INT_DEC_PIC);
  1212. regVal |= (1<<W4_INT_QUERY_DEC);
  1213. regVal |= (1<<W4_INT_SLEEP_VPU);
  1214. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  1215. }
  1216. WriteVpuRegister(W4_VPU_VINT_ENABLE, regVal);
  1217. Wave4BitIssueCommand(core, W4_CMD_INIT_VPU);
  1218. WriteVpuRegister(W4_VPU_REMAP_CORE_START, 1);
  1219. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1220. if (time_after(jiffies, timeout))
  1221. goto DONE_WAKEUP;
  1222. }
  1223. if (ReadVpuRegister(suc_reg) == 0) {
  1224. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W4_RET_FAIL_REASON));
  1225. goto DONE_WAKEUP;
  1226. }
  1227. }
  1228. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1229. WriteVpuRegister(BIT_CODE_RUN, 0);
  1230. /*---- LOAD BOOT CODE*/
  1231. for (i = 0; i < 512; i++) {
  1232. val = s_bit_firmware_info[core].bit_code[i];
  1233. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1234. }
  1235. for (i = 0 ; i < 64 ; i++)
  1236. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1237. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1238. WriteVpuRegister(BIT_CODE_RESET, 1);
  1239. WriteVpuRegister(BIT_CODE_RUN, 1);
  1240. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1241. if (time_after(jiffies, timeout))
  1242. goto DONE_WAKEUP;
  1243. }
  1244. }
  1245. else {
  1246. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1247. goto DONE_WAKEUP;
  1248. }
  1249. }
  1250. DONE_WAKEUP:
  1251. pm_runtime_put_sync(dev);
  1252. return 0;
  1253. }
  1254. #endif /* CONFIG_PM_SLEEP */
  1255. #endif /* CONFIG_PM */
  1256. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1257. static const struct of_device_id vpu_of_id_table[] = {
  1258. { .compatible = "cnm,cnm420l-vpu" },
  1259. { .compatible = "starfive,venc" },
  1260. {}
  1261. };
  1262. MODULE_DEVICE_TABLE(of, vpu_of_id_table);
  1263. static const struct dev_pm_ops cm_vpu_pm_ops = {
  1264. SET_RUNTIME_PM_OPS(vpu_runtime_suspend,
  1265. vpu_runtime_resume, NULL)
  1266. SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
  1267. };
  1268. static struct platform_driver vpu_driver = {
  1269. .driver = {
  1270. .name = VPU_PLATFORM_DEVICE_NAME,
  1271. .of_match_table = of_match_ptr(vpu_of_id_table),
  1272. .pm = &cm_vpu_pm_ops,
  1273. },
  1274. .probe = vpu_probe,
  1275. .remove = vpu_remove,
  1276. };
  1277. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1278. static int __init vpu_init(void)
  1279. {
  1280. int res;
  1281. DPRINTK("[VPUDRV] begin vpu_init\n");
  1282. init_waitqueue_head(&s_interrupt_wait_q);
  1283. s_common_memory.base = 0;
  1284. s_instance_pool.base = 0;
  1285. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1286. res = platform_driver_register(&vpu_driver);
  1287. #else
  1288. res = vpu_probe(NULL);
  1289. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1290. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1291. return res;
  1292. }
  1293. static void __exit vpu_exit(void)
  1294. {
  1295. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1296. DPRINTK("[VPUDRV] vpu_exit\n");
  1297. platform_driver_unregister(&vpu_driver);
  1298. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1299. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1300. #else
  1301. vpu_clk_disable(s_vpu_clk);
  1302. #endif
  1303. vpu_clk_put(s_vpu_clk);
  1304. if (s_instance_pool.base) {
  1305. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1306. vfree((const void *)s_instance_pool.base);
  1307. #else
  1308. vpu_free_dma_buffer(&s_instance_pool);
  1309. #endif
  1310. s_instance_pool.base = 0;
  1311. }
  1312. if (s_common_memory.base) {
  1313. vpu_free_dma_buffer(&s_common_memory);
  1314. s_common_memory.base = 0;
  1315. }
  1316. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1317. if (s_video_memory.base) {
  1318. iounmap((void *)s_video_memory.base);
  1319. s_video_memory.base = 0;
  1320. vmem_exit(&s_vmem);
  1321. }
  1322. #endif
  1323. if (s_vpu_major > 0) {
  1324. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1325. class_destroy(s_vpu_class);
  1326. cdev_del(&s_vpu_cdev);
  1327. unregister_chrdev_region(s_vpu_devt, 1);
  1328. s_vpu_major = 0;
  1329. }
  1330. #ifdef VPU_SUPPORT_ISR
  1331. if (s_vpu_irq)
  1332. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1333. #endif
  1334. if (s_vpu_register.virt_addr) {
  1335. iounmap((void *)s_vpu_register.virt_addr);
  1336. s_vpu_register.virt_addr = 0x00;
  1337. }
  1338. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1339. return;
  1340. }
  1341. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1342. MODULE_DESCRIPTION("VPU linux driver");
  1343. MODULE_LICENSE("Dual BSD/GPL");
  1344. module_init(vpu_init);
  1345. module_exit(vpu_exit);
  1346. static int vpu_pmu_enable(struct device *dev)
  1347. {
  1348. pm_runtime_set_active(dev);
  1349. pm_runtime_enable(dev);
  1350. return 0;
  1351. }
  1352. static void vpu_pmu_disable(struct device *dev)
  1353. {
  1354. pm_runtime_disable(dev);
  1355. pm_runtime_set_suspended(dev);
  1356. }
  1357. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1358. #define CLK_ENABLE_DATA 1
  1359. #define CLK_DISABLE_DATA 0
  1360. #define CLK_EN_SHIFT 31
  1361. #define CLK_EN_MASK 0x80000000U
  1362. #define SAIF_BD_APBS_BASE 0x13020000
  1363. #define WAVE420L_CLK_AXI_CTRL 0x138U
  1364. #define WAVE420L_CLK_BPU_CTRL 0x13cU
  1365. #define WAVE420L_CLK_VCE_CTRL 0x140U
  1366. #define WAVE420L_CLK_APB_CTRL 0x144U
  1367. #define WAVE420L_CLK_NOCBUS_CTRL 0x148U
  1368. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1369. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1370. #define RSTN_AXI_MASK (0x1 << 22)
  1371. #define RSTN_BPU_MASK (0x1 << 23)
  1372. #define RSTN_VCE_MASK (0x1 << 24)
  1373. #define RSTN_APB_MASK (0x1 << 25)
  1374. #define RSTN_128B_AXIMEM_MASK (0x1 << 26)
  1375. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1376. uint32_t shift, uint32_t mask)
  1377. {
  1378. uint32_t tmp;
  1379. tmp = readl(addr);
  1380. tmp &= ~mask;
  1381. tmp |= (data << shift) & mask;
  1382. writel(tmp, addr);
  1383. }
  1384. static void saif_assert_rst(volatile void __iomem *addr,
  1385. const volatile void __iomem *addr_status, uint32_t mask)
  1386. {
  1387. uint32_t tmp;
  1388. tmp = readl(addr);
  1389. tmp |= mask;
  1390. writel(tmp, addr);
  1391. do {
  1392. tmp = readl(addr_status);
  1393. } while ((tmp & mask) != 0);
  1394. }
  1395. static void saif_clear_rst(volatile void __iomem *addr,
  1396. const volatile void __iomem *addr_status, uint32_t mask)
  1397. {
  1398. uint32_t tmp;
  1399. tmp = readl(addr);
  1400. tmp &= ~mask;
  1401. writel(tmp, addr);
  1402. do {
  1403. tmp = readl(addr_status);
  1404. } while ((tmp & mask) != mask);
  1405. }
  1406. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1407. {
  1408. if (enable)
  1409. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1410. else
  1411. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1412. }
  1413. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1414. {
  1415. if (enable) {
  1416. /*enable*/
  1417. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1418. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1419. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1420. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1421. /*clr-reset*/
  1422. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1423. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1424. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1425. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1426. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1427. } else {
  1428. /*assert-reset*/
  1429. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1430. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1431. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1432. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1433. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1434. /*disable*/
  1435. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1436. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1437. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1438. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1439. }
  1440. }
  1441. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1442. {
  1443. if (!pdev)
  1444. return -ENXIO;
  1445. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1446. if (IS_ERR(vpu_clk->clkgen)) {
  1447. dev_err(dev, "ioremap clkgen failed.\n");
  1448. return PTR_ERR(vpu_clk->clkgen);
  1449. }
  1450. /* clkgen define */
  1451. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_AXI_CTRL;
  1452. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_BPU_CTRL;
  1453. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_VCE_CTRL;
  1454. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_APB_CTRL;
  1455. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE420L_CLK_NOCBUS_CTRL;
  1456. vpu_clk->en_mask = CLK_EN_MASK;
  1457. vpu_clk->en_shift = CLK_EN_SHIFT;
  1458. /* rstgen define */
  1459. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1460. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1461. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1462. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1463. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1464. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1465. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1466. if (device_property_read_bool(&pdev->dev, "starfive,venc_noc_ctrl"))
  1467. vpu_clk->noc_ctrl = true;
  1468. return 0;
  1469. }
  1470. static void vpu_clk_reset(vpu_clk_t *clk)
  1471. {
  1472. /*assert-reset*/
  1473. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1474. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1475. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1476. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1477. /*clr-reset*/
  1478. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1479. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1480. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1481. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1482. }
  1483. int vpu_hw_reset(void)
  1484. {
  1485. if (!s_vpu_clk)
  1486. return -1;
  1487. vpu_clk_reset(s_vpu_clk);
  1488. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1489. return 0;
  1490. }
  1491. struct vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1492. {
  1493. vpu_clk_t *vpu_clk;
  1494. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1495. if (!vpu_clk)
  1496. return NULL;
  1497. if (vpu_of_clk_get(dev, vpu_clk))
  1498. goto err_get_clk;
  1499. return vpu_clk;
  1500. err_get_clk:
  1501. devm_kfree(&pdev->dev, vpu_clk);
  1502. return NULL;
  1503. }
  1504. void vpu_clk_put(struct vpu_clk_t *clk)
  1505. {
  1506. if (clk->clkgen) {
  1507. iounmap(clk->clkgen);
  1508. clk->clkgen = NULL;
  1509. }
  1510. }
  1511. static int vpu_clk_enable(struct vpu_clk_t *clk)
  1512. {
  1513. if (clk == NULL || IS_ERR(clk))
  1514. return -1;
  1515. vpu_pmu_enable(clk->dev);
  1516. vpu_clk_control(clk, true);
  1517. if (clk->noc_ctrl == true)
  1518. vpu_noc_vdec_bus_control(clk, true);
  1519. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1520. return 0;
  1521. }
  1522. void vpu_clk_disable(struct vpu_clk_t *clk)
  1523. {
  1524. if (clk == NULL || IS_ERR(clk))
  1525. return;
  1526. vpu_clk_control(clk, false);
  1527. vpu_pmu_disable(clk->dev);
  1528. if (clk->noc_ctrl == true)
  1529. vpu_noc_vdec_bus_control(clk, false);
  1530. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1531. }
  1532. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1533. static const struct vpu_dev_freq_list wave420l_dev_freq_lists[MODE_MAX+1] = {
  1534. [MODE_480P_30F] = {
  1535. .mode = MODE_480P_30F,
  1536. .axi_rate = VPU_DEV_FREQ_80,
  1537. .bpu_rate = VPU_DEV_FREQ_80,
  1538. .vce_rate = VPU_DEV_FREQ_80,
  1539. },
  1540. [MODE_480P_60F] = {
  1541. .mode = MODE_480P_60F,
  1542. .axi_rate = VPU_DEV_FREQ_100,
  1543. .bpu_rate = VPU_DEV_FREQ_100,
  1544. .vce_rate = VPU_DEV_FREQ_100,
  1545. },
  1546. [MODE_720P_30F] = {
  1547. .mode = MODE_720P_30F,
  1548. .axi_rate = VPU_DEV_FREQ_150,
  1549. .bpu_rate = VPU_DEV_FREQ_150,
  1550. .vce_rate = VPU_DEV_FREQ_150,
  1551. },
  1552. [MODE_720P_60F] = {
  1553. .mode = MODE_720P_60F,
  1554. .axi_rate = VPU_DEV_FREQ_237,
  1555. .bpu_rate = VPU_DEV_FREQ_237,
  1556. .vce_rate = VPU_DEV_FREQ_237,
  1557. },
  1558. [MODE_1080P_30F] = {
  1559. .mode = MODE_1080P_30F,
  1560. .axi_rate = VPU_DEV_FREQ_300,
  1561. .bpu_rate = VPU_DEV_FREQ_300,
  1562. .vce_rate = VPU_DEV_FREQ_300,
  1563. },
  1564. [MODE_MAX] = {
  1565. .mode = MODE_MAX,
  1566. .axi_rate = VPU_DEV_FREQ_MAX,
  1567. .bpu_rate = VPU_DEV_FREQ_MAX,
  1568. .vce_rate = VPU_DEV_FREQ_MAX,
  1569. },
  1570. };
  1571. static int vpu_devfreq_init(vpu_clk_t *vpu_clk)
  1572. {
  1573. struct vpu_devfreq_t *dev_freq = &vpu_clk->vpu_devfreq;
  1574. dev_freq->axi_clk = devm_clk_get_optional(vpu_clk->dev, "axi_clk");
  1575. if (IS_ERR(dev_freq->axi_clk))
  1576. return PTR_ERR(dev_freq->axi_clk);
  1577. dev_freq->bpu_clk = devm_clk_get_optional(vpu_clk->dev, "bpu_clk");
  1578. if (IS_ERR(dev_freq->bpu_clk))
  1579. return PTR_ERR(dev_freq->bpu_clk);
  1580. dev_freq->vce_clk = devm_clk_get_optional(vpu_clk->dev, "vce_clk");
  1581. if (IS_ERR(dev_freq->vce_clk))
  1582. return PTR_ERR(dev_freq->vce_clk);
  1583. return 0;
  1584. }
  1585. static int vpu_devfreq_set(vpu_clk_t *vpu_clk, const struct vpu_dev_freq_list *freq_list)
  1586. {
  1587. struct vpu_devfreq_t *dev_freq = &vpu_clk->vpu_devfreq;
  1588. int ret;
  1589. dev_dbg(vpu_clk->dev, "axi_clk:%ld bpu_clk:%ld vce_clk:%ld\n",
  1590. freq_list->axi_rate, freq_list->bpu_rate, freq_list->vce_rate);
  1591. ret = clk_set_rate(dev_freq->axi_clk, freq_list->axi_rate);
  1592. if (ret)
  1593. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1594. ret = clk_set_rate(dev_freq->bpu_clk, freq_list->bpu_rate);
  1595. if (ret)
  1596. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1597. ret = clk_set_rate(dev_freq->vce_clk, freq_list->vce_rate);
  1598. if (ret)
  1599. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1600. return ret;
  1601. }
  1602. static int vpu_devfreq_select(struct vpudrv_devfreq_info_t *info)
  1603. {
  1604. unsigned long framsize = info->picWidth*info->picHeight;
  1605. int frameRateInfo = info->frameRateInfo;
  1606. int mode;
  1607. if (frameRateInfo <= 30) {
  1608. if (framsize <= FRAMSIZE_480P)
  1609. mode = MODE_480P_30F;
  1610. else if (framsize <= FRAMSIZE_720P)
  1611. mode = MODE_720P_30F;
  1612. else if (framsize <= FRAMSIZE_1080P)
  1613. mode = MODE_1080P_30F;
  1614. else
  1615. mode = MODE_MAX;
  1616. } else {
  1617. if (framsize <= FRAMSIZE_480P)
  1618. mode = MODE_480P_60F;
  1619. else if (framsize <= FRAMSIZE_720P)
  1620. mode = MODE_720P_60F;
  1621. else
  1622. mode = MODE_MAX;
  1623. }
  1624. return vpu_devfreq_set(s_vpu_clk, &wave420l_dev_freq_lists[mode]);
  1625. }
  1626. int vpu_hw_reset(void)
  1627. {
  1628. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1629. /* sram do not need reset */
  1630. return reset_control_reset(s_vpu_clk->resets);
  1631. }
  1632. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1633. {
  1634. struct device *dev = &pdev->dev;
  1635. int ret;
  1636. vpu_clk->dev = dev;
  1637. vpu_clk->clks = vpu_clks;
  1638. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  1639. vpu_clk->resets = devm_reset_control_array_get_exclusive(dev);
  1640. if (IS_ERR(vpu_clk->resets)) {
  1641. ret = PTR_ERR(vpu_clk->resets);
  1642. dev_err(dev, "faied to get vpu reset controls\n");
  1643. }
  1644. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  1645. if (ret)
  1646. dev_err(dev, "faied to get vpu clk controls\n");
  1647. if (device_property_read_bool(dev, "starfive,venc_noc_ctrl"))
  1648. vpu_clk->noc_ctrl = true;
  1649. return 0;
  1650. }
  1651. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1652. {
  1653. vpu_clk_t *vpu_clk;
  1654. if (!pdev)
  1655. return NULL;
  1656. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1657. if (!vpu_clk)
  1658. return NULL;
  1659. if (vpu_of_clk_get(pdev, vpu_clk))
  1660. goto err_of_clk_get;
  1661. vpu_devfreq_init(vpu_clk);
  1662. return vpu_clk;
  1663. err_of_clk_get:
  1664. devm_kfree(&pdev->dev, vpu_clk);
  1665. return NULL;
  1666. }
  1667. static void vpu_clk_put(vpu_clk_t *clk)
  1668. {
  1669. clk_bulk_put(clk->nr_clks, clk->clks);
  1670. }
  1671. static int vpu_clk_enable(vpu_clk_t *clk)
  1672. {
  1673. int ret;
  1674. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1675. if (ret)
  1676. dev_err(clk->dev, "enable clk error.\n");
  1677. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1678. return ret;
  1679. }
  1680. static void vpu_clk_disable(vpu_clk_t *clk)
  1681. {
  1682. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  1683. }
  1684. #endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/