jpu.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. //--=========================================================================--
  3. // This file is linux device driver for JPU.
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2016 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. // Copyright (C) 2022 StarFive Technology Co., Ltd.
  16. //--=========================================================================-
  17. #include <linux/kernel.h>
  18. #include <linux/device.h>
  19. #include <linux/mm.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/ioport.h>
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/of.h>
  26. #include <linux/of_address.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/wait.h>
  29. #include <linux/list.h>
  30. #include <linux/clk.h>
  31. #include <linux/delay.h>
  32. #include <linux/uaccess.h>
  33. #include <linux/cdev.h>
  34. #include <linux/slab.h>
  35. #include <linux/sched.h>
  36. #include <linux/sched/signal.h>
  37. #include <linux/reset.h>
  38. #include <linux/version.h>
  39. #include "../../../jpuapi/jpuconfig.h"
  40. #include "jpu.h"
  41. extern void sifive_ccache_flush_range(phys_addr_t start, size_t len);
  42. //#define ENABLE_DEBUG_MSG
  43. #ifdef ENABLE_DEBUG_MSG
  44. #define DPRINTK(args...) printk(KERN_INFO args);
  45. #else
  46. #define DPRINTK(args...)
  47. #endif
  48. /* definitions to be changed as customer configuration */
  49. /* if you want to have clock gating scheme frame by frame */
  50. //#define JPU_SUPPORT_CLOCK_CONTROL
  51. #define JPU_SUPPORT_ISR
  52. //#define JPU_IRQ_CONTROL
  53. /* if clktree is work,try this...*/
  54. #define STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  55. /* if the platform driver knows the name of this driver */
  56. /* JPU_PLATFORM_DEVICE_NAME */
  57. #define JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  58. /* if this driver knows the dedicated video memory address */
  59. //#define JPU_SUPPORT_RESERVED_VIDEO_MEMORY //if this driver knows the dedicated video memory address
  60. #define JPU_PLATFORM_DEVICE_NAME "cnm_jpu"
  61. #define JPU_CLK_NAME "jpege"
  62. #define JPU_DEV_NAME "jpu"
  63. #define JPU_REG_BASE_ADDR 0x11900000
  64. #define JPU_REG_SIZE 0x300
  65. #ifdef JPU_SUPPORT_ISR
  66. #define JPU_IRQ_NUM 24
  67. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  68. /*#define JPU_IRQ_CONTROL*/
  69. #endif
  70. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  71. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  72. #endif
  73. struct device *jpu_dev;
  74. typedef struct jpu_drv_context_t {
  75. struct fasync_struct *async_queue;
  76. u32 open_count; /*!<< device reference count. Not instance count */
  77. u32 interrupt_reason[MAX_NUM_INSTANCE];
  78. } jpu_drv_context_t;
  79. /* To track the allocated memory buffer */
  80. typedef struct jpudrv_buffer_pool_t {
  81. struct list_head list;
  82. struct jpudrv_buffer_t jb;
  83. struct file* filp;
  84. } jpudrv_buffer_pool_t;
  85. /* To track the instance index and buffer in instance pool */
  86. typedef struct jpudrv_instance_list_t {
  87. struct list_head list;
  88. unsigned long inst_idx;
  89. struct file* filp;
  90. } jpudrv_instance_list_t;
  91. typedef struct jpudrv_instance_pool_t {
  92. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  93. } jpudrv_instance_pool_t;
  94. #ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  95. typedef struct jpu_clkgen_t {
  96. void __iomem *en_ctrl;
  97. uint32_t rst_mask;
  98. } jpu_clkgen_t;
  99. #endif
  100. struct clk_bulk_data jpu_clks[] = {
  101. { .id = "axi_clk" },
  102. { .id = "core_clk" },
  103. { .id = "apb_clk" },
  104. { .id = "noc_bus" },
  105. };
  106. typedef struct jpu_clk_t {
  107. #ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  108. void __iomem *clkgen;
  109. void __iomem *rst_ctrl;
  110. void __iomem *rst_status;
  111. uint32_t en_shift;
  112. uint32_t en_mask;
  113. jpu_clkgen_t apb_clk;
  114. jpu_clkgen_t axi_clk;
  115. jpu_clkgen_t core_clk;
  116. #else
  117. struct clk_bulk_data *clks;
  118. struct reset_control *resets;
  119. int nr_clks;
  120. #endif
  121. struct device *dev;
  122. } jpu_clk_t;
  123. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  124. #include "jmm.h"
  125. static jpu_mm_t s_jmem;
  126. static jpudrv_buffer_t s_video_memory = {0};
  127. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  128. static int jpu_hw_reset(void);
  129. static void jpu_clk_disable(jpu_clk_t *clk);
  130. static int jpu_clk_enable(jpu_clk_t *clk);
  131. static jpu_clk_t *jpu_clk_get(struct platform_device *pdev);
  132. static void jpu_clk_put(jpu_clk_t *clk);
  133. static int jpu_pmu_enable(struct device *dev);
  134. static void jpu_pmu_disable(struct device *dev);
  135. // end customer definition
  136. static jpudrv_buffer_t s_instance_pool = {0};
  137. static jpu_drv_context_t s_jpu_drv_context;
  138. static dev_t s_jpu_devt;
  139. static int s_jpu_major;
  140. static struct cdev s_jpu_cdev;
  141. static struct class *s_jpu_class;
  142. static jpu_clk_t *s_jpu_clk;
  143. static int s_jpu_open_ref_count;
  144. #ifdef JPU_SUPPORT_ISR
  145. static int s_jpu_irq = JPU_IRQ_NUM;
  146. #endif
  147. static jpudrv_buffer_t s_jpu_register = {0};
  148. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  149. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  150. static spinlock_t s_jpu_lock = __SPIN_LOCK_UNLOCKED(s_jpu_lock);
  151. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  152. static DECLARE_MUTEX(s_jpu_sem);
  153. #else
  154. static DEFINE_SEMAPHORE(s_jpu_sem);
  155. #endif
  156. static struct list_head s_jbp_head = LIST_HEAD_INIT(s_jbp_head);
  157. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  158. #ifdef CONFIG_PM
  159. /* implement to power management functions */
  160. #endif
  161. #define NPT_BASE 0x0000
  162. #define NPT_REG_SIZE 0x300
  163. #define MJPEG_PIC_STATUS_REG(_inst_no) (NPT_BASE + (_inst_no*NPT_REG_SIZE) + 0x004)
  164. #define ReadJpuRegister(addr) *(volatile unsigned int *)(s_jpu_register.virt_addr + addr)
  165. #define WriteJpuRegister(addr, val) *(volatile unsigned int *)(s_jpu_register.virt_addr + addr) = (unsigned int)val
  166. #define WriteJpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  167. static void starfive_flush_dcache(phys_addr_t start, size_t len)
  168. {
  169. #ifdef ARCH_HAS_SYNC_DMA_FOR_DEVICE
  170. dma_sync_single_for_device(jpu_dev, start, len, DMA_FROM_DEVICE);
  171. #else
  172. sifive_ccache_flush_range(start, len);
  173. #endif
  174. }
  175. static int jpu_alloc_dma_buffer(jpudrv_buffer_t *jb)
  176. {
  177. if (!jb)
  178. return -1;
  179. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  180. jb->phys_addr = (unsigned long long)jmem_alloc(&s_jmem, jb->size, 0);
  181. if ((unsigned long)jb->phys_addr == (unsigned long)-1) {
  182. printk(KERN_ERR "[JPUDRV] Physical memory allocation error size=%d\n", jb->size);
  183. return -1;
  184. }
  185. jb->base = (unsigned long)(s_video_memory.base + (jb->phys_addr - s_video_memory.phys_addr));
  186. #else
  187. jb->base = (unsigned long)dma_alloc_coherent(jpu_dev, PAGE_ALIGN(jb->size), (dma_addr_t *) (&jb->phys_addr), GFP_DMA | GFP_KERNEL);
  188. if ((void *)(jb->base) == NULL) {
  189. printk(KERN_ERR "[JPUDRV] Physical memory allocation error size=%d\n", jb->size);
  190. return -1;
  191. }
  192. starfive_flush_dcache(jb->phys_addr,PAGE_ALIGN(jb->size));
  193. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  194. return 0;
  195. }
  196. static void jpu_free_dma_buffer(jpudrv_buffer_t *jb)
  197. {
  198. if (!jb) {
  199. return;
  200. }
  201. if (jb->base)
  202. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  203. jmem_free(&s_jmem, jb->phys_addr, 0);
  204. #else
  205. dma_free_coherent(jpu_dev, PAGE_ALIGN(jb->size), (void *)jb->base, jb->phys_addr);
  206. #endif /* JPUR_SUPPORT_RESERVED_VIDEO_MEMORY */
  207. }
  208. static int jpu_free_instances(struct file *filp)
  209. {
  210. jpudrv_instance_list_t *vil, *n;
  211. jpudrv_instance_pool_t *vip;
  212. void *vip_base;
  213. int instance_pool_size_per_core;
  214. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  215. void *jdi_mutexes_base;
  216. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  217. #endif
  218. DPRINTK("[JPUDRV] jpu_free_instances\n");
  219. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_JPU_CORE); /* s_instance_pool.size assigned to the size of all core once call JDI_IOCTL_GET_INSTANCE_POOL by user. */
  220. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  221. {
  222. if (vil->filp == filp) {
  223. vip_base = (void *)(s_instance_pool.base + instance_pool_size_per_core);
  224. DPRINTK("[JPUDRV] jpu_free_instances detect instance crash instIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, vip_base, (int)instance_pool_size_per_core);
  225. vip = (jpudrv_instance_pool_t *)vip_base;
  226. if (vip) {
  227. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in jpuapi) to free the corresponding instance. */
  228. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  229. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  230. jdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  231. DPRINTK("[JPUDRV] jpu_free_instances : force to destroy jdi_mutexes_base=%p in userspace \n", jdi_mutexes_base);
  232. if (jdi_mutexes_base) {
  233. int i;
  234. for (i = 0; i < 4; i++) {
  235. memcpy(jdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  236. jdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  237. }
  238. }
  239. #endif
  240. }
  241. s_jpu_open_ref_count--;
  242. list_del(&vil->list);
  243. kfree(vil);
  244. }
  245. }
  246. return 1;
  247. }
  248. static int jpu_free_buffers(struct file *filp)
  249. {
  250. jpudrv_buffer_pool_t *pool, *n;
  251. jpudrv_buffer_t jb;
  252. DPRINTK("[JPUDRV] jpu_free_buffers\n");
  253. list_for_each_entry_safe(pool, n, &s_jbp_head, list)
  254. {
  255. if (pool->filp == filp) {
  256. jb = pool->jb;
  257. if (jb.base) {
  258. jpu_free_dma_buffer(&jb);
  259. list_del(&pool->list);
  260. kfree(pool);
  261. }
  262. }
  263. }
  264. return 0;
  265. }
  266. static irqreturn_t jpu_irq_handler(int irq, void *dev_id)
  267. {
  268. jpu_drv_context_t* dev = (jpu_drv_context_t *)dev_id;
  269. int i;
  270. u32 flag;
  271. DPRINTK("[JPUDRV][+]%s\n", __func__);
  272. #ifdef JPU_IRQ_CONTROL
  273. disable_irq_nosync(s_jpu_irq);
  274. #endif
  275. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  276. flag = ReadJpuRegister(MJPEG_PIC_STATUS_REG(i));
  277. if (flag != 0) {
  278. break;
  279. }
  280. }
  281. dev->interrupt_reason[i] = flag;
  282. s_interrupt_flag[i] = 1;
  283. DPRINTK("[JPUDRV][%d] INTERRUPT FLAG: %08x, %08x\n", i, dev->interrupt_reason[i], MJPEG_PIC_STATUS_REG(i));
  284. if (dev->async_queue)
  285. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); // notify the interrupt to userspace
  286. #ifndef JPU_IRQ_CONTROL
  287. WriteJpuRegister(MJPEG_PIC_STATUS_REG(i),flag); //clear interrut
  288. #endif
  289. wake_up_interruptible(&s_interrupt_wait_q[i]);
  290. DPRINTK("[JPUDRV][-]%s\n", __func__);
  291. return IRQ_HANDLED;
  292. }
  293. static int jpu_open(struct inode *inode, struct file *filp)
  294. {
  295. DPRINTK("[JPUDRV][+] %s\n", __func__);
  296. pm_runtime_get_sync(s_jpu_clk->dev);
  297. spin_lock(&s_jpu_lock);
  298. s_jpu_drv_context.open_count++;
  299. filp->private_data = (void *)(&s_jpu_drv_context);
  300. spin_unlock(&s_jpu_lock);
  301. DPRINTK("[JPUDRV][-] %s\n", __func__);
  302. return 0;
  303. }
  304. static long jpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  305. {
  306. int ret = 0;
  307. switch (cmd)
  308. {
  309. case JDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  310. {
  311. jpudrv_buffer_pool_t *jbp;
  312. DPRINTK("[JPUDRV][+]JDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  313. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  314. jbp = kzalloc(sizeof(jpudrv_buffer_pool_t), GFP_KERNEL);
  315. if (!jbp) {
  316. up(&s_jpu_sem);
  317. return -ENOMEM;
  318. }
  319. ret = copy_from_user(&(jbp->jb), (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  320. if (ret)
  321. {
  322. kfree(jbp);
  323. up(&s_jpu_sem);
  324. return -EFAULT;
  325. }
  326. ret = jpu_alloc_dma_buffer(&(jbp->jb));
  327. if (ret == -1)
  328. {
  329. ret = -ENOMEM;
  330. kfree(jbp);
  331. up(&s_jpu_sem);
  332. break;
  333. }
  334. ret = copy_to_user((void __user *)arg, &(jbp->jb), sizeof(jpudrv_buffer_t));
  335. if (ret)
  336. {
  337. kfree(jbp);
  338. ret = -EFAULT;
  339. up(&s_jpu_sem);
  340. break;
  341. }
  342. jbp->filp = filp;
  343. spin_lock(&s_jpu_lock);
  344. list_add(&jbp->list, &s_jbp_head);
  345. spin_unlock(&s_jpu_lock);
  346. up(&s_jpu_sem);
  347. }
  348. DPRINTK("[JPUDRV][-]JDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  349. }
  350. break;
  351. case JDI_IOCTL_GET_PHYSICAL_MEMORY:
  352. {
  353. jpudrv_buffer_pool_t *jbp = NULL;
  354. void *user_address = NULL;
  355. struct task_struct *my_struct = NULL;
  356. struct mm_struct *mm = NULL;
  357. unsigned long address = 0;
  358. pgd_t *pgd = NULL;
  359. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_PHYSICAL_MEMORY\n");
  360. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  361. jbp = kzalloc(sizeof(jpudrv_buffer_pool_t), GFP_KERNEL);
  362. if (!jbp) {
  363. up(&s_jpu_sem);
  364. return -ENOMEM;
  365. }
  366. ret = copy_from_user(&(jbp->jb), (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  367. if (ret)
  368. {
  369. kfree(jbp);
  370. up(&s_jpu_sem);
  371. return -EFAULT;
  372. }
  373. user_address = (void *)jbp->jb.virt_addr;
  374. my_struct = get_current();
  375. mm = my_struct->mm;
  376. address = (unsigned long)user_address;
  377. pgd = pgd_offset(mm, address);
  378. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  379. p4d_t *p4d = p4d_offset(pgd, address);
  380. pud_t *pud = pud_offset(p4d, address);
  381. if (!pud_none(*pud) && !pud_bad(*pud)) {
  382. pmd_t *pmd = pmd_offset(pud, address);
  383. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  384. pte_t *pte = pte_offset_map(pmd, address);
  385. if (!pte_none(*pte)) {
  386. struct page *pg = pte_page(*pte);
  387. unsigned long phys = page_to_phys(pg);
  388. unsigned long virt = (unsigned long)phys_to_virt(phys);
  389. printk("phy address = %lx, virt = %lx\r\n", phys, virt);
  390. jbp->jb.phys_addr = phys;
  391. jbp->jb.base = virt;
  392. }
  393. pte_unmap(pte);
  394. }
  395. }
  396. }
  397. ret = copy_to_user((void __user *)arg, &(jbp->jb), sizeof(jpudrv_buffer_t));
  398. if (ret)
  399. {
  400. kfree(jbp);
  401. ret = -EFAULT;
  402. up(&s_jpu_sem);
  403. break;
  404. }
  405. kfree(jbp);
  406. up(&s_jpu_sem);
  407. }
  408. DPRINTK("[JPUDRV][-]JDI_IOCTL_GET_PHYSICAL_MEMORY\n");
  409. }
  410. break;
  411. case JDI_IOCTL_FREE_PHYSICALMEMORY:
  412. {
  413. jpudrv_buffer_pool_t *jbp, *n;
  414. jpudrv_buffer_t jb;
  415. DPRINTK("[JPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  416. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  417. ret = copy_from_user(&jb, (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  418. if (ret) {
  419. up(&s_jpu_sem);
  420. return -EACCES;
  421. }
  422. if (jb.base)
  423. jpu_free_dma_buffer(&jb);
  424. spin_lock(&s_jpu_lock);
  425. list_for_each_entry_safe(jbp, n, &s_jbp_head, list) {
  426. if (jbp->jb.base == jb.base) {
  427. list_del(&jbp->list);
  428. kfree(jbp);
  429. break;
  430. }
  431. }
  432. spin_unlock(&s_jpu_lock);
  433. up(&s_jpu_sem);
  434. }
  435. DPRINTK("[JPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  436. }
  437. break;
  438. case JDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  439. {
  440. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  441. if (s_video_memory.base != 0) {
  442. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(jpudrv_buffer_t));
  443. if (ret != 0)
  444. ret = -EFAULT;
  445. } else {
  446. ret = -EFAULT;
  447. }
  448. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  449. }
  450. break;
  451. case JDI_IOCTL_WAIT_INTERRUPT:
  452. {
  453. jpudrv_intr_info_t info;
  454. struct jpu_drv_context_t *dev = (struct jpu_drv_context_t *)filp->private_data;
  455. u32 instance_no;
  456. DPRINTK("[JPUDRV][+]JDI_IOCTL_WAIT_INTERRUPT\n");
  457. ret = copy_from_user(&info, (jpudrv_intr_info_t *)arg, sizeof(jpudrv_intr_info_t));
  458. if (ret != 0)
  459. return -EFAULT;
  460. instance_no = info.inst_idx;
  461. DPRINTK("[JPUDRV] INSTANCE NO: %d\n", instance_no);
  462. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[instance_no], s_interrupt_flag[instance_no] != 0, msecs_to_jiffies(info.timeout));
  463. if (!ret) {
  464. DPRINTK("[JPUDRV] INSTANCE NO: %d ETIME\n", instance_no);
  465. ret = -ETIME;
  466. break;
  467. }
  468. if (signal_pending(current)) {
  469. ret = -ERESTARTSYS;
  470. DPRINTK("[JPUDRV] INSTANCE NO: %d ERESTARTSYS\n", instance_no);
  471. break;
  472. }
  473. DPRINTK("[JPUDRV] INST(%d) s_interrupt_flag(%d), reason(0x%08x)\n", instance_no, s_interrupt_flag[instance_no], dev->interrupt_reason[instance_no]);
  474. info.intr_reason = dev->interrupt_reason[instance_no];
  475. s_interrupt_flag[instance_no] = 0;
  476. dev->interrupt_reason[instance_no] = 0;
  477. ret = copy_to_user((void __user *)arg, &info, sizeof(jpudrv_intr_info_t));
  478. #ifdef JPU_IRQ_CONTROL
  479. enable_irq(s_jpu_irq);
  480. #endif
  481. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  482. if (ret != 0)
  483. return -EFAULT;
  484. }
  485. break;
  486. case JDI_IOCTL_SET_CLOCK_GATE:
  487. {
  488. u32 clkgate;
  489. if (get_user(clkgate, (u32 __user *) arg))
  490. return -EFAULT;
  491. #ifdef JPU_SUPPORT_CLOCK_CONTROL
  492. if (clkgate)
  493. jpu_clk_enable(s_jpu_clk);
  494. else
  495. jpu_clk_disable(s_jpu_clk);
  496. #endif /* JPU_SUPPORT_CLOCK_CONTROL */
  497. }
  498. break;
  499. case JDI_IOCTL_GET_INSTANCE_POOL:
  500. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_INSTANCE_POOL\n");
  501. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  502. if (s_instance_pool.base != 0) {
  503. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(jpudrv_buffer_t));
  504. } else {
  505. ret = copy_from_user(&s_instance_pool, (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  506. if (ret == 0) {
  507. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  508. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  509. s_instance_pool.phys_addr = s_instance_pool.base;
  510. if (s_instance_pool.base != 0) {
  511. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  512. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(jpudrv_buffer_t));
  513. if (ret == 0) {
  514. /* success to get memory for instance pool */
  515. up(&s_jpu_sem);
  516. break;
  517. }
  518. }
  519. ret = -EFAULT;
  520. }
  521. }
  522. up(&s_jpu_sem);
  523. }
  524. DPRINTK("[JPUDRV][-]JDI_IOCTL_GET_INSTANCE_POOL: %s base: %lx, size: %d\n",
  525. (ret==0 ? "OK" : "NG"), s_instance_pool.base, s_instance_pool.size);
  526. break;
  527. case JDI_IOCTL_OPEN_INSTANCE:
  528. {
  529. jpudrv_inst_info_t inst_info;
  530. if (copy_from_user(&inst_info, (jpudrv_inst_info_t *)arg, sizeof(jpudrv_inst_info_t)))
  531. return -EFAULT;
  532. spin_lock(&s_jpu_lock);
  533. s_jpu_open_ref_count++; /* flag just for that jpu is in opened or closed */
  534. inst_info.inst_open_count = s_jpu_open_ref_count;
  535. spin_unlock(&s_jpu_lock);
  536. if (copy_to_user((void __user *)arg, &inst_info, sizeof(jpudrv_inst_info_t))) {
  537. return -EFAULT;
  538. }
  539. DPRINTK("[JPUDRV] JDI_IOCTL_OPEN_INSTANCE inst_idx=%d, s_jpu_open_ref_count=%d, inst_open_count=%d\n",
  540. (int)inst_info.inst_idx, s_jpu_open_ref_count, inst_info.inst_open_count);
  541. }
  542. break;
  543. case JDI_IOCTL_CLOSE_INSTANCE:
  544. {
  545. jpudrv_inst_info_t inst_info;
  546. DPRINTK("[JPUDRV][+]JDI_IOCTL_CLOSE_INSTANCE\n");
  547. if (copy_from_user(&inst_info, (jpudrv_inst_info_t *)arg, sizeof(jpudrv_inst_info_t)))
  548. return -EFAULT;
  549. spin_lock(&s_jpu_lock);
  550. s_jpu_open_ref_count--; /* flag just for that jpu is in opened or closed */
  551. inst_info.inst_open_count = s_jpu_open_ref_count;
  552. spin_unlock(&s_jpu_lock);
  553. if (copy_to_user((void __user *)arg, &inst_info, sizeof(jpudrv_inst_info_t)))
  554. return -EFAULT;
  555. DPRINTK("[JPUDRV] JDI_IOCTL_CLOSE_INSTANCE inst_idx=%d, s_jpu_open_ref_count=%d, inst_open_count=%d\n",
  556. (int)inst_info.inst_idx, s_jpu_open_ref_count, inst_info.inst_open_count);
  557. }
  558. break;
  559. case JDI_IOCTL_GET_INSTANCE_NUM:
  560. {
  561. jpudrv_inst_info_t inst_info;
  562. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_INSTANCE_NUM\n");
  563. ret = copy_from_user(&inst_info, (jpudrv_inst_info_t *)arg, sizeof(jpudrv_inst_info_t));
  564. if (ret != 0)
  565. break;
  566. spin_lock(&s_jpu_lock);
  567. inst_info.inst_open_count = s_jpu_open_ref_count;
  568. spin_unlock(&s_jpu_lock);
  569. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(jpudrv_inst_info_t));
  570. DPRINTK("[JPUDRV] JDI_IOCTL_GET_INSTANCE_NUM inst_idx=%d, open_count=%d\n", (int)inst_info.inst_idx, inst_info.inst_open_count);
  571. }
  572. break;
  573. case JDI_IOCTL_RESET:
  574. jpu_hw_reset();
  575. break;
  576. case JDI_IOCTL_GET_REGISTER_INFO:
  577. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_REGISTER_INFO\n");
  578. ret = copy_to_user((void __user *)arg, &s_jpu_register, sizeof(jpudrv_buffer_t));
  579. if (ret != 0)
  580. ret = -EFAULT;
  581. DPRINTK("[JPUDRV][-]JDI_IOCTL_GET_REGISTER_INFO s_jpu_register.phys_addr=0x%lx, s_jpu_register.virt_addr=0x%lx, s_jpu_register.size=%d\n",
  582. s_jpu_register.phys_addr , s_jpu_register.virt_addr, s_jpu_register.size);
  583. break;
  584. case JDI_IOCTL_FLUSH_DCACHE:
  585. {
  586. jpudrv_flush_cache_t cache_info;
  587. //DPRINTK("[JPUDRV][+]JDI_IOCTL_FLUSH_DCACHE\n");
  588. ret = copy_from_user(&cache_info, (jpudrv_flush_cache_t *)arg, sizeof(jpudrv_flush_cache_t));
  589. if (ret != 0)
  590. ret = -EFAULT;
  591. if(cache_info.flag)
  592. starfive_flush_dcache(cache_info.start,cache_info.size);
  593. //DPRINTK("[JPUDRV][-]JDI_IOCTL_FLUSH_DCACHE\n");
  594. break;
  595. }
  596. default:
  597. {
  598. printk(KERN_ERR "No such IOCTL, cmd is %d\n", cmd);
  599. }
  600. break;
  601. }
  602. return ret;
  603. }
  604. static ssize_t jpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  605. {
  606. return -1;
  607. }
  608. static ssize_t jpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  609. {
  610. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  611. if (!buf) {
  612. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  613. return -EFAULT;
  614. }
  615. return -1;
  616. }
  617. static int jpu_release(struct inode *inode, struct file *filp)
  618. {
  619. int ret = 0;
  620. u32 open_count;
  621. DPRINTK("[JPUDRV][+] jpu_release\n");
  622. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  623. /* found and free the not handled buffer by user applications */
  624. jpu_free_buffers(filp);
  625. /* found and free the not closed instance by user applications */
  626. jpu_free_instances(filp);
  627. DPRINTK("[JPUDRV] open_count: %d\n", s_jpu_drv_context.open_count);
  628. spin_lock(&s_jpu_lock);
  629. s_jpu_drv_context.open_count--;
  630. open_count = s_jpu_drv_context.open_count;
  631. spin_unlock(&s_jpu_lock);
  632. if (open_count == 0) {
  633. if (s_instance_pool.base) {
  634. DPRINTK("[JPUDRV] free instance pool\n");
  635. vfree((const void *)s_instance_pool.base);
  636. s_instance_pool.base = 0;
  637. }
  638. }
  639. }
  640. up(&s_jpu_sem);
  641. DPRINTK("[JPUDRV][-] jpu_release\n");
  642. pm_runtime_put_sync(s_jpu_clk->dev);
  643. return 0;
  644. }
  645. static int jpu_fasync(int fd, struct file *filp, int mode)
  646. {
  647. struct jpu_drv_context_t *dev = (struct jpu_drv_context_t *)filp->private_data;
  648. return fasync_helper(fd, filp, mode, &dev->async_queue);
  649. }
  650. static int jpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  651. {
  652. unsigned long pfn;
  653. vm->vm_flags |= VM_IO | VM_RESERVED;
  654. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  655. pfn = s_jpu_register.phys_addr >> PAGE_SHIFT;
  656. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  657. }
  658. static int jpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  659. {
  660. vm->vm_flags |= VM_IO | VM_RESERVED;
  661. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  662. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  663. }
  664. static int jpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  665. {
  666. int ret;
  667. long length = vm->vm_end - vm->vm_start;
  668. unsigned long start = vm->vm_start;
  669. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  670. unsigned long pfn;
  671. vm->vm_flags |= VM_RESERVED;
  672. /* loop over all pages, map it page individually */
  673. while (length > 0) {
  674. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  675. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  676. return ret;
  677. }
  678. start += PAGE_SIZE;
  679. vmalloc_area_ptr += PAGE_SIZE;
  680. length -= PAGE_SIZE;
  681. }
  682. return 0;
  683. }
  684. /*!
  685. * @brief memory map interface for jpu file operation
  686. * @return 0 on success or negative error code on error
  687. */
  688. static int jpu_mmap(struct file *fp, struct vm_area_struct *vm)
  689. {
  690. if (vm->vm_pgoff == 0)
  691. return jpu_map_to_instance_pool_memory(fp, vm);
  692. if (vm->vm_pgoff == (s_jpu_register.phys_addr>>PAGE_SHIFT))
  693. return jpu_map_to_register(fp, vm);
  694. return jpu_map_to_physical_memory(fp, vm);
  695. }
  696. struct file_operations jpu_fops = {
  697. .owner = THIS_MODULE,
  698. .open = jpu_open,
  699. .read = jpu_read,
  700. .write = jpu_write,
  701. .unlocked_ioctl = jpu_ioctl,
  702. .release = jpu_release,
  703. .fasync = jpu_fasync,
  704. .mmap = jpu_mmap,
  705. };
  706. static int jpu_probe(struct platform_device *pdev)
  707. {
  708. int err = 0;
  709. struct resource *res = NULL;
  710. struct device *devices;
  711. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  712. struct resource res_cma;
  713. struct device_node *node;
  714. #endif
  715. int irq = -1;
  716. DPRINTK("[JPUDRV] jpu_probe\n");
  717. if (pdev) {
  718. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  719. }
  720. if (res) {/* if platform driver is implemented */
  721. s_jpu_register.phys_addr = res->start;
  722. s_jpu_register.virt_addr = (unsigned long)ioremap(res->start, res->end - res->start);
  723. s_jpu_register.size = res->end - res->start;
  724. DPRINTK("[JPUDRV] : jpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_jpu_register.phys_addr , s_jpu_register.virt_addr);
  725. } else {
  726. s_jpu_register.phys_addr = JPU_REG_BASE_ADDR;
  727. s_jpu_register.virt_addr = (unsigned long)ioremap(s_jpu_register.phys_addr, JPU_REG_SIZE);
  728. s_jpu_register.size = JPU_REG_SIZE;
  729. DPRINTK("[JPUDRV] : jpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_jpu_register.phys_addr, s_jpu_register.virt_addr);
  730. }
  731. if (pdev) {
  732. jpu_dev = &pdev->dev;
  733. //jpu_dev->dma_ops = NULL;
  734. dev_info(jpu_dev,"init device.\n");
  735. }
  736. /* get the major number of the character device */
  737. if ((alloc_chrdev_region(&s_jpu_devt, 0, 1, JPU_DEV_NAME)) < 0) {
  738. err = -EBUSY;
  739. printk(KERN_ERR "could not allocate major number\n");
  740. goto ERROR_PROVE_DEVICE;
  741. }
  742. s_jpu_major = MAJOR(s_jpu_devt);
  743. /* initialize the device structure and register the device with the kernel */
  744. cdev_init(&s_jpu_cdev, &jpu_fops);
  745. if ((cdev_add(&s_jpu_cdev, s_jpu_devt, 1)) < 0) {
  746. err = -EBUSY;
  747. printk(KERN_ERR "could not allocate chrdev\n");
  748. goto ERROR_PROVE_DEVICE;
  749. }
  750. s_jpu_class = class_create(THIS_MODULE, JPU_DEV_NAME);
  751. if (IS_ERR(s_jpu_class)) {
  752. dev_err(jpu_dev, "class creat error.\n");
  753. goto ERROR_CRART_CLASS;
  754. }
  755. devices = device_create(s_jpu_class, 0, MKDEV(s_jpu_major, 0),
  756. NULL, JPU_DEV_NAME);
  757. if (IS_ERR(devices)) {
  758. dev_err(jpu_dev, "device creat error.\n");
  759. goto ERROR_CREAT_DEVICE;
  760. }
  761. if (pdev)
  762. s_jpu_clk = jpu_clk_get(pdev);
  763. else
  764. s_jpu_clk = jpu_clk_get(NULL);
  765. if (!s_jpu_clk) {
  766. printk(KERN_ERR "[JPUDRV] : not support clock controller.\n");
  767. }
  768. else {
  769. DPRINTK("[JPUDRV] : get clock controller s_jpu_clk=%p\n", s_jpu_clk);
  770. }
  771. jpu_pmu_enable(s_jpu_clk->dev);
  772. jpu_clk_enable(s_jpu_clk);
  773. reset_control_deassert(s_jpu_clk->resets);
  774. #ifdef JPU_SUPPORT_ISR
  775. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  776. if(pdev)
  777. irq = platform_get_irq(pdev, 0);
  778. if (irq >= 0) {/* if platform driver is implemented */
  779. s_jpu_irq = irq;
  780. DPRINTK("[JPUDRV] : jpu irq number get from platform driver irq=0x%x\n", s_jpu_irq );
  781. } else {
  782. DPRINTK("[JPUDRV] : jpu irq number get from defined value irq=0x%x\n", s_jpu_irq );
  783. }
  784. #else
  785. DPRINTK("[JPUDRV] : jpu irq number get from defined value irq=0x%x\n", s_jpu_irq);
  786. #endif
  787. err = request_irq(s_jpu_irq, jpu_irq_handler, 0, "JPU_CODEC_IRQ", (void *)(&s_jpu_drv_context));
  788. if (err) {
  789. printk(KERN_ERR "[JPUDRV] : fail to register interrupt handler\n");
  790. goto ERROR_PROVE_DEVICE;
  791. }
  792. #endif
  793. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  794. node = of_parse_phandle(jpu_dev->of_node, "memory-region", 0);
  795. if(node){
  796. dev_info(jpu_dev, "Get mem form memory-region\n");
  797. of_address_to_resource(node, 0, &res_cma);
  798. s_video_memory.size = resource_size(&res_cma);
  799. s_video_memory.phys_addr = res_cma.start;
  800. }else{
  801. dev_info(jpu_dev, "Get mem form reserved memory failed.please check the dts file.\n");
  802. return 0;
  803. }
  804. s_video_memory.base = (unsigned long)ioremap(MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  805. if (!s_video_memory.base) {
  806. printk(KERN_ERR "[JPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", MEM2SYS(s_video_memory.phys_addr), s_video_memory.base, s_video_memory.size);
  807. goto ERROR_PROVE_DEVICE;
  808. }
  809. if (jmem_init(&s_jmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  810. printk(KERN_ERR "[JPUDRV] : fail to init vmem system\n");
  811. goto ERROR_PROVE_DEVICE;
  812. }
  813. DPRINTK("[JPUDRV] success to probe jpu device with reserved video memory phys_addr=0x%lx, base=0x%lx\n", s_video_memory.phys_addr, s_video_memory.base);
  814. #else
  815. DPRINTK("[JPUDRV] success to probe jpu device with non reserved video memory\n");
  816. #endif
  817. return 0;
  818. ERROR_CREAT_DEVICE:
  819. class_destroy(s_jpu_class);
  820. ERROR_CRART_CLASS:
  821. cdev_del(&s_jpu_cdev);
  822. ERROR_PROVE_DEVICE:
  823. if (s_jpu_major)
  824. unregister_chrdev_region(s_jpu_major, 1);
  825. if (s_jpu_register.virt_addr)
  826. iounmap((void *)s_jpu_register.virt_addr);
  827. return err;
  828. }
  829. static int jpu_remove(struct platform_device *pdev)
  830. {
  831. DPRINTK("[JPUDRV] jpu_remove\n");
  832. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  833. if (s_instance_pool.base) {
  834. vfree((const void *)s_instance_pool.base);
  835. s_instance_pool.base = 0;
  836. }
  837. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  838. if (s_video_memory.base) {
  839. iounmap((void *)s_video_memory.base);
  840. s_video_memory.base = 0;
  841. jmem_exit(&s_jmem);
  842. }
  843. #endif
  844. if (s_jpu_major > 0) {
  845. device_destroy(s_jpu_class, MKDEV(s_jpu_major, 0));
  846. class_destroy(s_jpu_class);
  847. cdev_del(&s_jpu_cdev);
  848. unregister_chrdev_region(s_jpu_devt, 1);
  849. s_jpu_major = 0;
  850. }
  851. #ifdef JPU_SUPPORT_ISR
  852. if (s_jpu_irq)
  853. free_irq(s_jpu_irq, &s_jpu_drv_context);
  854. #endif
  855. if (s_jpu_register.virt_addr)
  856. iounmap((void*)s_jpu_register.virt_addr);
  857. jpu_clk_put(s_jpu_clk);
  858. jpu_pmu_disable(&pdev->dev);
  859. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  860. return 0;
  861. }
  862. #ifdef CONFIG_PM
  863. static int __maybe_unused jpu_runtime_suspend(struct device *dev)
  864. {
  865. reset_control_assert(s_jpu_clk->resets);
  866. jpu_clk_disable(s_jpu_clk);
  867. return 0;
  868. }
  869. static int __maybe_unused jpu_runtime_resume(struct device *dev)
  870. {
  871. jpu_clk_enable(s_jpu_clk);
  872. return reset_control_deassert(s_jpu_clk->resets);
  873. }
  874. #endif /* CONFIG_PM */
  875. #ifdef CONFIG_PM_SLEEP
  876. static int __maybe_unused jpu_suspend(struct device *dev)
  877. {
  878. pm_runtime_force_suspend(dev);
  879. return 0;
  880. }
  881. static int __maybe_unused jpu_resume(struct device *dev)
  882. {
  883. pm_runtime_force_resume(dev);
  884. return 0;
  885. }
  886. #endif /* CONFIG_PM_SLEEP */
  887. static const struct dev_pm_ops cm_jpu_pm_ops = {
  888. SET_RUNTIME_PM_OPS(jpu_runtime_suspend,
  889. jpu_runtime_resume, NULL)
  890. SET_SYSTEM_SLEEP_PM_OPS(jpu_suspend, jpu_resume)
  891. };
  892. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  893. static const struct of_device_id jpu_of_id_table[] = {
  894. { .compatible = "cm,codaj12-jpu-1" },
  895. { .compatible = "starfive,jpu" },
  896. {}
  897. };
  898. MODULE_DEVICE_TABLE(of, jpu_of_id_table);
  899. static struct platform_driver jpu_driver = {
  900. .driver = {
  901. .name = JPU_PLATFORM_DEVICE_NAME,
  902. .of_match_table = of_match_ptr(jpu_of_id_table),
  903. .pm = &cm_jpu_pm_ops,
  904. },
  905. .probe = jpu_probe,
  906. .remove = jpu_remove,
  907. };
  908. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  909. static int __init jpu_init(void)
  910. {
  911. int res = 0;
  912. u32 i;
  913. DPRINTK("[JPUDRV] begin jpu_init\n");
  914. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  915. init_waitqueue_head(&s_interrupt_wait_q[i]);
  916. }
  917. s_instance_pool.base = 0;
  918. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  919. res = platform_driver_register(&jpu_driver);
  920. #else
  921. res = jpu_probe(NULL);
  922. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  923. DPRINTK("[JPUDRV] end jpu_init result=0x%x\n", res);
  924. return res;
  925. }
  926. static void __exit jpu_exit(void)
  927. {
  928. DPRINTK("[JPUDRV] [+]jpu_exit\n");
  929. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  930. platform_driver_unregister(&jpu_driver);
  931. #else /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  932. #ifdef JPU_SUPPORT_CLOCK_CONTROL
  933. #else
  934. jpu_clk_disable(s_jpu_clk);
  935. #endif /* JPU_SUPPORT_CLOCK_CONTROL */
  936. jpu_clk_put(s_jpu_clk);
  937. if (s_instance_pool.base) {
  938. vfree((const void *)s_instance_pool.base);
  939. s_instance_pool.base = 0;
  940. }
  941. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  942. if (s_video_memory.base) {
  943. iounmap((void *)s_video_memory.base);
  944. s_video_memory.base = 0;
  945. jmem_exit(&s_jmem);
  946. }
  947. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  948. if (s_jpu_major > 0) {
  949. device_destroy(s_jpu_class, MKDEV(s_jpu_major, 0));
  950. class_destroy(s_jpu_class);
  951. cdev_del(&s_jpu_cdev);
  952. unregister_chrdev_region(s_jpu_devt, 1);
  953. s_jpu_major = 0;
  954. }
  955. #ifdef JPU_SUPPORT_ISR
  956. if (s_jpu_irq)
  957. free_irq(s_jpu_irq, &s_jpu_drv_context);
  958. #endif /* JPU_SUPPORT_ISR */
  959. if (s_jpu_register.virt_addr) {
  960. iounmap((void *)s_jpu_register.virt_addr);
  961. s_jpu_register.virt_addr = 0x00;
  962. }
  963. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  964. DPRINTK("[JPUDRV] [-]jpu_exit\n");
  965. return;
  966. }
  967. MODULE_AUTHOR("A customer using C&M JPU, Inc.");
  968. MODULE_DESCRIPTION("JPU linux driver");
  969. MODULE_LICENSE("Dual BSD/GPL");
  970. module_init(jpu_init);
  971. module_exit(jpu_exit);
  972. static int jpu_pmu_enable(struct device *dev)
  973. {
  974. pm_runtime_set_active(dev);
  975. pm_runtime_enable(dev);
  976. return 0;
  977. }
  978. static void jpu_pmu_disable(struct device *dev)
  979. {
  980. pm_runtime_disable(dev);
  981. pm_runtime_set_suspended(dev);
  982. }
  983. #ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  984. #define CLK_ENABLE_DATA 1
  985. #define CLK_DISABLE_DATA 0
  986. #define CLK_EN_SHIFT 31
  987. #define CLK_EN_MASK 0x80000000U
  988. #define SAIF_BD_APBS_BASE 0x13020000
  989. #define CODAJ12_CLK_AXI_CTRL 0x108U
  990. #define CODAJ12_CLK_APB_CTRL 0x110U
  991. #define CODAJ12_CLK_CORE_CTRL 0x10cU
  992. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  993. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  994. #define RSTN_AXI_MASK (0x1 << 12)
  995. #define RSTN_CORE_MASK (0x1 << 13)
  996. #define RSTN_APB_MASK (0x1 << 14)
  997. static __maybe_unused uint32_t saif_get_reg(
  998. const volatile void __iomem *addr,
  999. uint32_t shift, uint32_t mask)
  1000. {
  1001. u32 tmp;
  1002. tmp = readl(addr);
  1003. tmp = (tmp & mask) >> shift;
  1004. return tmp;
  1005. }
  1006. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1007. uint32_t shift, uint32_t mask)
  1008. {
  1009. uint32_t tmp;
  1010. tmp = readl(addr);
  1011. tmp &= ~mask;
  1012. tmp |= (data << shift) & mask;
  1013. writel(tmp, addr);
  1014. }
  1015. static void saif_assert_rst(volatile void __iomem *addr,
  1016. const volatile void __iomem *addr_status, uint32_t mask)
  1017. {
  1018. uint32_t tmp;
  1019. tmp = readl(addr);
  1020. tmp |= mask;
  1021. writel(tmp, addr);
  1022. do {
  1023. tmp = readl(addr_status);
  1024. } while ((tmp & mask) != 0);
  1025. }
  1026. static void saif_clear_rst(volatile void __iomem *addr,
  1027. const volatile void __iomem *addr_status, uint32_t mask)
  1028. {
  1029. uint32_t tmp;
  1030. tmp = readl(addr);
  1031. tmp &= ~mask;
  1032. writel(tmp, addr);
  1033. do {
  1034. tmp = readl(addr_status);
  1035. } while ((tmp & mask) != mask);
  1036. }
  1037. static void jpu_clk_control(jpu_clk_t *clk, bool enable)
  1038. {
  1039. if (enable) {
  1040. /*enable*/
  1041. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1042. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1043. saif_set_reg(clk->core_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1044. /*clr-reset*/
  1045. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1046. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1047. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1048. } else {
  1049. /*assert-reset*/
  1050. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1051. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1052. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1053. /*disable*/
  1054. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1055. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1056. saif_set_reg(clk->core_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1057. }
  1058. }
  1059. static void jpu_clk_reset(jpu_clk_t *clk)
  1060. {
  1061. /*assert-reset*/
  1062. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1063. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1064. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1065. /*clr-reset*/
  1066. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1067. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1068. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1069. }
  1070. int jpu_hw_reset(void)
  1071. {
  1072. if (!s_jpu_clk)
  1073. return -1;
  1074. jpu_clk_reset(s_jpu_clk);
  1075. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1076. return 0;
  1077. }
  1078. static int jpu_of_clk_get(struct platform_device *pdev, jpu_clk_t *jpu_clk)
  1079. {
  1080. if (!pdev)
  1081. return -ENXIO;
  1082. jpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1083. if (IS_ERR(jpu_clk->clkgen)) {
  1084. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1085. return PTR_ERR(jpu_clk->clkgen);
  1086. }
  1087. /* clkgen define */
  1088. jpu_clk->axi_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_AXI_CTRL;
  1089. jpu_clk->apb_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_APB_CTRL;
  1090. jpu_clk->core_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_CORE_CTRL;
  1091. jpu_clk->en_mask = CLK_EN_MASK;
  1092. jpu_clk->en_shift = CLK_EN_SHIFT;
  1093. /* rstgen define */
  1094. jpu_clk->rst_ctrl = jpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1095. jpu_clk->rst_status = jpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1096. jpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1097. jpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1098. jpu_clk->core_clk.rst_mask = RSTN_CORE_MASK;
  1099. return 0;
  1100. }
  1101. static jpu_clk_t *jpu_clk_get(struct platform_device *pdev)
  1102. {
  1103. jpu_clk_t *jpu_clk;
  1104. jpu_clk = devm_kzalloc(&pdev->dev, sizeof(*jpu_clk), GFP_KERNEL);
  1105. if (!jpu_clk)
  1106. return NULL;
  1107. if (jpu_of_clk_get(pdev, jpu_clk))
  1108. goto err_get_clk;
  1109. return jpu_clk;
  1110. err_get_clk:
  1111. devm_kfree(&pdev->dev, jpu_clk);
  1112. return NULL;
  1113. }
  1114. static void jpu_clk_put(jpu_clk_t *clk)
  1115. {
  1116. if (clk->clkgen) {
  1117. iounmap(clk->clkgen);
  1118. clk->clkgen = NULL;
  1119. }
  1120. }
  1121. static int jpu_clk_enable(jpu_clk_t *clk)
  1122. {
  1123. if (clk == NULL || IS_ERR(clk))
  1124. return -1;
  1125. jpu_pmu_enable(clk->dev);
  1126. jpu_clk_control(clk, true);
  1127. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1128. return 0;
  1129. }
  1130. static void jpu_clk_disable(jpu_clk_t *clk)
  1131. {
  1132. if (clk == NULL || IS_ERR(clk))
  1133. return;
  1134. jpu_clk_control(clk, false);
  1135. jpu_pmu_disable(clk->dev);
  1136. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1137. }
  1138. #else /* STARFIVE_JPU_SUPPORT_CLOCK_CONTROL */
  1139. static int jpu_hw_reset(void)
  1140. {
  1141. return reset_control_reset(s_jpu_clk->resets);
  1142. }
  1143. static int jpu_of_clk_get(struct platform_device *pdev, jpu_clk_t *jpu_clk)
  1144. {
  1145. struct device *dev = &pdev->dev;
  1146. int ret;
  1147. jpu_clk->dev = dev;
  1148. jpu_clk->clks = jpu_clks;
  1149. jpu_clk->nr_clks = ARRAY_SIZE(jpu_clks);
  1150. jpu_clk->resets = devm_reset_control_array_get_shared(dev);
  1151. if (IS_ERR(jpu_clk->resets)) {
  1152. ret = PTR_ERR(jpu_clk->resets);
  1153. dev_err(dev, "faied to get jpu reset controls\n");
  1154. }
  1155. ret = devm_clk_bulk_get(dev, jpu_clk->nr_clks, jpu_clk->clks);
  1156. if (ret)
  1157. dev_err(dev, "faied to get jpu clk controls\n");
  1158. return 0;
  1159. }
  1160. static jpu_clk_t *jpu_clk_get(struct platform_device *pdev)
  1161. {
  1162. jpu_clk_t *jpu_clk;
  1163. if (!pdev)
  1164. return NULL;
  1165. jpu_clk = devm_kzalloc(&pdev->dev, sizeof(*jpu_clk), GFP_KERNEL);
  1166. if (!jpu_clk)
  1167. return NULL;
  1168. if (jpu_of_clk_get(pdev, jpu_clk))
  1169. goto err_of_clk_get;
  1170. return jpu_clk;
  1171. err_of_clk_get:
  1172. devm_kfree(&pdev->dev, jpu_clk);
  1173. return NULL;
  1174. }
  1175. static void jpu_clk_put(jpu_clk_t *clk)
  1176. {
  1177. clk_bulk_put(clk->nr_clks, clk->clks);
  1178. }
  1179. static int jpu_clk_enable(jpu_clk_t *clk)
  1180. {
  1181. int ret;
  1182. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1183. if (ret)
  1184. dev_err(clk->dev, "enable clk error.\n");
  1185. DPRINTK("[VPUDRV] jpu_clk_enable\n");
  1186. return ret;
  1187. }
  1188. static void jpu_clk_disable(jpu_clk_t *clk)
  1189. {
  1190. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  1191. }
  1192. #endif /* STARFIVE_JPU_SUPPORT_CLOCK_CONTROL */