vdi.c 64 KB

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  1. // SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. //------------------------------------------------------------------------------
  3. // File: vdi.c
  4. //
  5. // Copyright (c) 2006, Chips & Media. All rights reserved.
  6. //------------------------------------------------------------------------------
  7. #if defined(linux) || defined(__linux) || defined(ANDROID)
  8. #include <ctype.h>
  9. #include <stdio.h>
  10. #include <stdlib.h>
  11. #include <string.h>
  12. #include <unistd.h>
  13. #ifdef _KERNEL_
  14. #include <linux/delay.h>
  15. #endif
  16. #include <signal.h> /* SIGIO */
  17. #include <fcntl.h> /* fcntl */
  18. #include <pthread.h>
  19. #include <sys/mman.h> /* mmap */
  20. #include <sys/ioctl.h> /* fopen/fread */
  21. #include <sys/errno.h> /* fopen/fread */
  22. #include <sys/types.h>
  23. #include <sys/time.h>
  24. #include "driver/vpu.h"
  25. #include "../vdi.h"
  26. #include "../vdi_osal.h"
  27. #include "coda9/coda9_regdefine.h"
  28. #include "wave/common/common_regdefine.h"
  29. #include "wave/wave4/wave4_regdefine.h"
  30. #include "wave/coda7q/coda7q_regdefine.h"
  31. #define VPU_DEVICE_NAME "/dev/venc"
  32. #define VPU_MUTEX_NAME "/vencmutex"
  33. static int mutex_fd = -1;
  34. typedef pthread_mutex_t MUTEX_HANDLE;
  35. # define SUPPORT_INTERRUPT
  36. # define VPU_BIT_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  37. # define VDI_SRAM_BASE_ADDR 0x00000000 // if we can know the sram address in SOC directly for vdi layer. it is possible to set in vdi layer without allocation from driver
  38. # define VDI_WAVE410_SRAM_SIZE 0x25000 // 8Kx8K MAIN10 MAX size
  39. # define VDI_WAVE412_SRAM_SIZE 0x80000
  40. # define VDI_WAVE512_SRAM_SIZE 0x80000
  41. # define VDI_WAVE515_SRAM_SIZE 0x80000
  42. # define VDI_WAVE520_SRAM_SIZE 0x25000 // 8Kx8X MAIN10 MAX size
  43. # define VDI_WAVE420_SRAM_SIZE 0x2E000 // 8Kx8X MAIN10 MAX size
  44. # define VDI_WAVE420L_SRAM_SIZE 0x2E000 // 8Kx8X MAIN10 MAX size
  45. # define VDI_CODA9_SRAM_SIZE 0x34600 // FHD MAX size, 0x17D00 4K MAX size 0x34600
  46. # define VDI_SYSTEM_ENDIAN VDI_LITTLE_ENDIAN
  47. # define VDI_128BIT_BUS_SYSTEM_ENDIAN VDI_128BIT_LITTLE_ENDIAN
  48. #define VDI_NUM_LOCK_HANDLES 4
  49. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  50. #define VPU_CORE_BASE_OFFSET 0x4000
  51. #endif
  52. typedef struct vpudrv_buffer_pool_t
  53. {
  54. vpudrv_buffer_t vdb;
  55. int inuse;
  56. } vpudrv_buffer_pool_t;
  57. typedef struct {
  58. unsigned long core_idx;
  59. unsigned int product_code;
  60. int vpu_fd;
  61. vpu_instance_pool_t *pvip;
  62. int task_num;
  63. int clock_state;
  64. vpudrv_buffer_t vdb_register;
  65. vpu_buffer_t vpu_common_memory;
  66. vpudrv_buffer_pool_t vpu_buffer_pool[MAX_VPU_BUFFER_POOL];
  67. int vpu_buffer_pool_count;
  68. void* vpu_mutex;
  69. void* vpu_omx_mutex;
  70. void* vpu_disp_mutex;
  71. } vdi_info_t;
  72. static vdi_info_t s_vdi_info[MAX_NUM_VPU_CORE];
  73. static int swap_endian(unsigned long core_idx, unsigned char *data, int len, int endian);
  74. static int allocate_common_memory(unsigned long core_idx);
  75. void vdi_flush_ddr(unsigned long core_idx,unsigned long start,unsigned long size,unsigned char flag)
  76. {
  77. vdi_info_t *vdi;
  78. vpudrv_flush_cache_t cache_info;
  79. vdi = &s_vdi_info[core_idx];
  80. cache_info.start = start;
  81. cache_info.size = size;
  82. cache_info.flag = flag;
  83. ioctl(vdi->vpu_fd, VDI_IOCTL_FLUSH_DCACHE, &cache_info);
  84. }
  85. void vdi_devfreq_set(unsigned long core_idx, int picHeight, int picWidth, int frameRateInfo)
  86. {
  87. vdi_info_t *vdi;
  88. vpudrv_devfreq_info_t devfreq_info;
  89. vdi = &s_vdi_info[core_idx];
  90. devfreq_info.picHeight = picHeight;
  91. devfreq_info.picWidth = picWidth;
  92. devfreq_info.frameRateInfo = frameRateInfo;
  93. ioctl(vdi->vpu_fd, VDI_IOCTL_DEVFREQ_SET, &devfreq_info);
  94. }
  95. int vdi_probe(unsigned long core_idx)
  96. {
  97. int ret;
  98. ret = vdi_init(core_idx);
  99. vdi_release(core_idx);
  100. return ret;
  101. }
  102. int vdi_init(unsigned long core_idx)
  103. {
  104. vdi_info_t *vdi;
  105. int i;
  106. if (core_idx >= MAX_NUM_VPU_CORE)
  107. return 0;
  108. vdi = &s_vdi_info[core_idx];
  109. if (vdi->vpu_fd != -1 && vdi->vpu_fd != 0x00)
  110. {
  111. vdi->task_num++;
  112. return 0;
  113. }
  114. vdi->vpu_fd = open(VPU_DEVICE_NAME, O_RDWR); // if this API supports VPU parallel processing using multi VPU. the driver should be made to open multiple times.
  115. if (vdi->vpu_fd < 0) {
  116. VLOG(ERR, "[VDI] Can't open vpu driver. [error=%s]. try to load vpu driver first \n", strerror(errno));
  117. return -1;
  118. }
  119. memset(&vdi->vpu_buffer_pool, 0x00, sizeof(vpudrv_buffer_pool_t)*MAX_VPU_BUFFER_POOL);
  120. if (!vdi_get_instance_pool(core_idx))
  121. {
  122. VLOG(INFO, "[VDI] fail to create shared info for saving context \n");
  123. goto ERR_VDI_INIT;
  124. }
  125. if (vdi->pvip->instance_pool_inited == FALSE)
  126. {
  127. int* pCodecInst;
  128. pthread_mutexattr_t mutexattr;
  129. pthread_mutexattr_init(&mutexattr);
  130. pthread_mutexattr_setpshared(&mutexattr, PTHREAD_PROCESS_SHARED);
  131. #if defined(ANDROID) || !defined(PTHREAD_MUTEX_ROBUST_NP)
  132. #else
  133. /* If a process or a thread is terminated abnormally,
  134. * pthread_mutexattr_setrobust_np(attr, PTHREAD_MUTEX_ROBUST_NP) makes
  135. * next onwer call pthread_mutex_lock() without deadlock.
  136. */
  137. pthread_mutexattr_setrobust(&mutexattr, PTHREAD_MUTEX_ROBUST);
  138. #endif
  139. pthread_mutex_init((MUTEX_HANDLE *)vdi->vpu_mutex, &mutexattr);
  140. pthread_mutex_init((MUTEX_HANDLE *)vdi->vpu_disp_mutex, &mutexattr);
  141. for( i = 0; i < MAX_NUM_INSTANCE; i++) {
  142. pCodecInst = (int *)vdi->pvip->codecInstPool[i];
  143. pCodecInst[1] = i; // indicate instIndex of CodecInst
  144. pCodecInst[0] = 0; // indicate inUse of CodecInst
  145. }
  146. vdi->pvip->instance_pool_inited = TRUE;
  147. pthread_mutexattr_destroy(&mutexattr);
  148. }
  149. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  150. if (ioctl(vdi->vpu_fd, VDI_IOCTL_GET_REGISTER_INFO, &vdi->vdb_register) < 0)
  151. {
  152. VLOG(ERR, "[VDI] fail to get host interface register\n");
  153. goto ERR_VDI_INIT;
  154. }
  155. #endif
  156. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  157. vdi->vdb_register.virt_addr = (unsigned long)mmap(NULL, vdi->vdb_register.size, PROT_READ | PROT_WRITE, MAP_SHARED, vdi->vpu_fd, vdi->vdb_register.phys_addr);
  158. #else
  159. vdi->vdb_register.size = VPU_BIT_REG_SIZE;
  160. vdi->vdb_register.virt_addr = (unsigned long)mmap(NULL, vdi->vdb_register.size, PROT_READ | PROT_WRITE, MAP_SHARED, vdi->vpu_fd, 0);
  161. #endif
  162. if ((void *)vdi->vdb_register.virt_addr == MAP_FAILED)
  163. {
  164. VLOG(ERR, "[VDI] fail to map vpu registers \n");
  165. goto ERR_VDI_INIT;
  166. }
  167. VLOG(INFO, "[VDI] map vdb_register core_idx=%d, virtaddr=0x%lx, size=%d\n", core_idx, vdi->vdb_register.virt_addr, vdi->vdb_register.size);
  168. vdi_set_clock_gate(core_idx, 1);
  169. vdi->product_code = vdi_read_register(core_idx, VPU_PRODUCT_CODE_REGISTER);
  170. if (PRODUCT_CODE_W_SERIES(vdi->product_code))
  171. {
  172. if (vdi_read_register(core_idx, W4_VCPU_CUR_PC) == 0) // if BIT processor is not running.
  173. {
  174. for (i=0; i<64; i++)
  175. vdi_write_register(core_idx, (i*4) + 0x100, 0x0);
  176. }
  177. }
  178. else if (PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) // CODA9XX
  179. {
  180. if (vdi_read_register(core_idx, BIT_CUR_PC) == 0) // if BIT processor is not running.
  181. {
  182. for (i=0; i<64; i++)
  183. vdi_write_register(core_idx, (i*4) + 0x100, 0x0);
  184. }
  185. }
  186. else {
  187. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  188. goto ERR_VDI_INIT;
  189. }
  190. if (vdi_lock(core_idx) < 0)
  191. {
  192. VLOG(ERR, "[VDI] fail to handle lock function\n");
  193. goto ERR_VDI_INIT;
  194. }
  195. if (allocate_common_memory(core_idx) < 0)
  196. {
  197. VLOG(ERR, "[VDI] fail to get vpu common buffer from driver\n");
  198. goto ERR_VDI_INIT;
  199. }
  200. vdi->core_idx = core_idx;
  201. vdi->task_num++;
  202. vdi_unlock(core_idx);
  203. VLOG(INFO, "[VDI] success to init driver \n");
  204. return 0;
  205. ERR_VDI_INIT:
  206. vdi_unlock(core_idx);
  207. vdi_release(core_idx);
  208. return -1;
  209. }
  210. int vdi_set_bit_firmware_to_pm(unsigned long core_idx, const unsigned short *code)
  211. {
  212. int i;
  213. vpu_bit_firmware_info_t bit_firmware_info;
  214. vdi_info_t *vdi;
  215. if (core_idx >= MAX_NUM_VPU_CORE)
  216. return 0;
  217. vdi = &s_vdi_info[core_idx];
  218. if (!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  219. return 0;
  220. bit_firmware_info.size = sizeof(vpu_bit_firmware_info_t);
  221. bit_firmware_info.core_idx = core_idx;
  222. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  223. bit_firmware_info.reg_base_offset = (core_idx*VPU_CORE_BASE_OFFSET);
  224. #else
  225. bit_firmware_info.reg_base_offset = 0;
  226. #endif
  227. for (i=0; i<512; i++)
  228. bit_firmware_info.bit_code[i] = code[i];
  229. if (write(vdi->vpu_fd, &bit_firmware_info, bit_firmware_info.size) < 0)
  230. {
  231. VLOG(ERR, "[VDI] fail to vdi_set_bit_firmware core=%d\n", bit_firmware_info.core_idx);
  232. return -1;
  233. }
  234. return 0;
  235. }
  236. int vdi_release(unsigned long core_idx)
  237. {
  238. int i;
  239. vpudrv_buffer_t vdb;
  240. vdi_info_t *vdi;
  241. if (core_idx >= MAX_NUM_VPU_CORE)
  242. return 0;
  243. vdi = &s_vdi_info[core_idx];
  244. if (!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  245. return 0;
  246. if (vdi_lock(core_idx) < 0)
  247. {
  248. VLOG(ERR, "[VDI] fail to handle lock function\n");
  249. return -1;
  250. }
  251. if (vdi->task_num > 1) // means that the opened instance remains
  252. {
  253. vdi->task_num--;
  254. vdi_unlock(core_idx);
  255. return 0;
  256. }
  257. if (vdi->vdb_register.virt_addr)
  258. munmap((void *)vdi->vdb_register.virt_addr, vdi->vdb_register.size);
  259. osal_memset(&vdi->vdb_register, 0x00, sizeof(vpudrv_buffer_t));
  260. vdb.size = 0;
  261. // get common memory information to free virtual address
  262. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  263. {
  264. if (vdi->vpu_common_memory.phys_addr >= vdi->vpu_buffer_pool[i].vdb.phys_addr &&
  265. vdi->vpu_common_memory.phys_addr < (vdi->vpu_buffer_pool[i].vdb.phys_addr + vdi->vpu_buffer_pool[i].vdb.size))
  266. {
  267. vdi->vpu_buffer_pool[i].inuse = 0;
  268. vdi->vpu_buffer_pool_count--;
  269. vdb = vdi->vpu_buffer_pool[i].vdb;
  270. break;
  271. }
  272. }
  273. vdi_unlock(core_idx);
  274. if (vdb.size > 0)
  275. {
  276. munmap((void *)vdb.virt_addr, vdb.size);
  277. memset(&vdi->vpu_common_memory, 0x00, sizeof(vpu_buffer_t));
  278. }
  279. vdi->task_num--;
  280. if (vdi->vpu_fd != -1 && vdi->vpu_fd != 0x00)
  281. {
  282. close(vdi->vpu_fd);
  283. vdi->vpu_fd = -1;
  284. }
  285. if(vdi->vpu_mutex)
  286. {
  287. munmap(vdi->vpu_mutex, sizeof(MUTEX_HANDLE) * VDI_NUM_LOCK_HANDLES);
  288. close(mutex_fd);
  289. vdi->vpu_mutex = NULL;
  290. vdi->vpu_disp_mutex = NULL;
  291. mutex_fd = -1;
  292. }
  293. memset(vdi, 0x00, sizeof(vdi_info_t));
  294. return 0;
  295. }
  296. int vdi_get_common_memory(unsigned long core_idx, vpu_buffer_t *vb)
  297. {
  298. vdi_info_t *vdi;
  299. if (core_idx >= MAX_NUM_VPU_CORE)
  300. return -1;
  301. vdi = &s_vdi_info[core_idx];
  302. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd==0x00)
  303. return -1;
  304. osal_memcpy(vb, &vdi->vpu_common_memory, sizeof(vpu_buffer_t));
  305. return 0;
  306. }
  307. int allocate_common_memory(unsigned long core_idx)
  308. {
  309. vdi_info_t *vdi = &s_vdi_info[core_idx];
  310. vpudrv_buffer_t vdb;
  311. int i;
  312. if (core_idx >= MAX_NUM_VPU_CORE)
  313. return -1;
  314. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd==0x00)
  315. return -1;
  316. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  317. vdb.size = SIZE_COMMON*MAX_NUM_VPU_CORE;
  318. if (ioctl(vdi->vpu_fd, VDI_IOCTL_GET_COMMON_MEMORY, &vdb) < 0)
  319. {
  320. VLOG(ERR, "[VDI] fail to vdi_allocate_dma_memory size=%d\n", vdb.size);
  321. return -1;
  322. }
  323. // vdb.virt_addr = (unsigned long)mmap(NULL, vdb.size, PROT_READ | PROT_WRITE, MAP_SHARED, vdi->vpu_fd, vdb.phys_addr);
  324. vdb.virt_addr = (unsigned long)mmap(NULL, vdb.size, PROT_READ | PROT_WRITE, MAP_SHARED, vdi->vpu_fd, DRAM_MEM2SYS(vdb.phys_addr));
  325. if ((void *)vdb.virt_addr == MAP_FAILED)
  326. {
  327. VLOG(ERR, "[VDI] fail to map common memory phyaddr=0x%lx, size = %d\n", (int)vdb.phys_addr, (int)vdb.size);
  328. return -1;
  329. }
  330. VLOG(INFO, "[VDI] allocate_common_memory, physaddr=0x%lx, virtaddr=0x%lx\n", (int)vdb.phys_addr, (int)vdb.virt_addr);
  331. // convert os driver buffer type to vpu buffer type
  332. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  333. vdi->pvip->vpu_common_buffer.size = SIZE_COMMON;
  334. vdi->pvip->vpu_common_buffer.phys_addr = (unsigned long)(vdb.phys_addr + (core_idx*SIZE_COMMON));
  335. vdi->pvip->vpu_common_buffer.base = (unsigned long)(vdb.base + (core_idx*SIZE_COMMON));
  336. vdi->pvip->vpu_common_buffer.virt_addr = (unsigned long)(vdb.virt_addr + (core_idx*SIZE_COMMON));
  337. #else
  338. vdi->pvip->vpu_common_buffer.size = SIZE_COMMON;
  339. vdi->pvip->vpu_common_buffer.phys_addr = (unsigned long)(vdb.phys_addr);
  340. vdi->pvip->vpu_common_buffer.base = (unsigned long)(vdb.base);
  341. vdi->pvip->vpu_common_buffer.virt_addr = (unsigned long)(vdb.virt_addr);
  342. #endif
  343. osal_memcpy(&vdi->vpu_common_memory, &vdi->pvip->vpu_common_buffer, sizeof(vpudrv_buffer_t));
  344. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  345. {
  346. if (vdi->vpu_buffer_pool[i].inuse == 0)
  347. {
  348. vdi->vpu_buffer_pool[i].vdb = vdb;
  349. vdi->vpu_buffer_pool_count++;
  350. vdi->vpu_buffer_pool[i].inuse = 1;
  351. break;
  352. }
  353. }
  354. VLOG(INFO, "[VDI] vdi_get_common_memory physaddr=0x%lx, size=%d, virtaddr=0x%lx\n", (int)vdi->vpu_common_memory.phys_addr, (int)vdi->vpu_common_memory.size, (int)vdi->vpu_common_memory.virt_addr);
  355. return 0;
  356. }
  357. vpu_instance_pool_t *vdi_get_instance_pool(unsigned long core_idx)
  358. {
  359. vdi_info_t *vdi;
  360. vpudrv_buffer_t vdb;
  361. if (core_idx >= MAX_NUM_VPU_CORE)
  362. return NULL;
  363. vdi = &s_vdi_info[core_idx];
  364. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00 )
  365. return NULL;
  366. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  367. if (!vdi->pvip)
  368. {
  369. void *mutex_addr = NULL;
  370. vdb.size = sizeof(vpu_instance_pool_t);
  371. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  372. vdb.size *= MAX_NUM_VPU_CORE;
  373. #endif
  374. if (ioctl(vdi->vpu_fd, VDI_IOCTL_GET_INSTANCE_POOL, &vdb) < 0)
  375. {
  376. VLOG(ERR, "[VDI] fail to allocate get instance pool physical space=%d\n", (int)vdb.size);
  377. return NULL;
  378. }
  379. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  380. vdb.virt_addr = (unsigned long)mmap(NULL, vdb.size, PROT_READ | PROT_WRITE, MAP_SHARED, vdi->vpu_fd, 0);
  381. #else
  382. vdb.virt_addr = (unsigned long)mmap(NULL, vdb.size, PROT_READ | PROT_WRITE, MAP_SHARED, vdi->vpu_fd, vdb.phys_addr);
  383. #endif
  384. if ((void *)vdb.virt_addr == MAP_FAILED)
  385. {
  386. VLOG(ERR, "[VDI] fail to map instance pool phyaddr=0x%lx, size = %d\n", (int)vdb.phys_addr, (int)vdb.size);
  387. return NULL;
  388. }
  389. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  390. vdi->pvip = (vpu_instance_pool_t *)(vdb.virt_addr + (core_idx*(sizeof(vpu_instance_pool_t))));
  391. #else
  392. vdi->pvip = (vpu_instance_pool_t *)(vdb.virt_addr);
  393. #endif
  394. if (vdi->pvip && (vdi->pvip->instance_pool_inited == FALSE)) {
  395. mutex_fd = shm_open(VPU_MUTEX_NAME, O_CREAT | O_RDWR | O_TRUNC, S_IRWXU | S_IRWXG);
  396. if (mutex_fd < 0)
  397. {
  398. VLOG(ERR, "[VDI] shm_open failed with %s\n", VPU_MUTEX_NAME);
  399. return NULL;
  400. }
  401. if (ftruncate(mutex_fd, sizeof(MUTEX_HANDLE) * VDI_NUM_LOCK_HANDLES) == -1)
  402. {
  403. shm_unlink(VPU_MUTEX_NAME);
  404. VLOG(ERR, "[VDI] ftruncate failed with %s\n" VPU_MUTEX_NAME);
  405. return NULL;
  406. }
  407. } else {
  408. mutex_fd = shm_open(VPU_MUTEX_NAME, O_RDWR, S_IRWXU | S_IRWXG);
  409. if (mutex_fd < 0)
  410. {
  411. VLOG(ERR, "[VDI] shm_open exist mutex failed with %s\n", VPU_MUTEX_NAME);
  412. return NULL;
  413. }
  414. }
  415. mutex_addr = mmap(NULL, sizeof(MUTEX_HANDLE) * VDI_NUM_LOCK_HANDLES, PROT_READ | PROT_WRITE, MAP_SHARED, mutex_fd, 0);
  416. if (mutex_addr == MAP_FAILED)
  417. {
  418. VLOG(ERR, "[VDI] mmap failed with %s\n", VPU_MUTEX_NAME);
  419. return NULL;
  420. }
  421. vdi->vpu_mutex = mutex_addr;
  422. vdi->vpu_disp_mutex = mutex_addr + sizeof(MUTEX_HANDLE);
  423. VLOG(INFO, "[VDI] instance pool physaddr=0x%lx, virtaddr=0x%lx, base=0x%lx, size=%ld\n", (int)vdb.phys_addr, (int)vdb.virt_addr, (int)vdb.base, (int)vdb.size);
  424. }
  425. return (vpu_instance_pool_t *)vdi->pvip;
  426. }
  427. int vdi_open_instance(unsigned long core_idx, unsigned long inst_idx)
  428. {
  429. vdi_info_t *vdi;
  430. vpudrv_inst_info_t inst_info;
  431. if (core_idx >= MAX_NUM_VPU_CORE)
  432. return -1;
  433. vdi = &s_vdi_info[core_idx];
  434. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  435. return -1;
  436. inst_info.core_idx = core_idx;
  437. inst_info.inst_idx = inst_idx;
  438. if (ioctl(vdi->vpu_fd, VDI_IOCTL_OPEN_INSTANCE, &inst_info) < 0)
  439. {
  440. VLOG(ERR, "[VDI] fail to deliver open instance num inst_idx=%d\n", (int)inst_idx);
  441. return -1;
  442. }
  443. vdi->pvip->vpu_instance_num = inst_info.inst_open_count;
  444. return 0;
  445. }
  446. int vdi_close_instance(unsigned long core_idx, unsigned long inst_idx)
  447. {
  448. vdi_info_t *vdi;
  449. vpudrv_inst_info_t inst_info;
  450. if (core_idx >= MAX_NUM_VPU_CORE)
  451. return -1;
  452. vdi = &s_vdi_info[core_idx];
  453. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  454. return -1;
  455. inst_info.core_idx = core_idx;
  456. inst_info.inst_idx = inst_idx;
  457. if (ioctl(vdi->vpu_fd, VDI_IOCTL_CLOSE_INSTANCE, &inst_info) < 0)
  458. {
  459. VLOG(ERR, "[VDI] fail to deliver open instance num inst_idx=%d\n", (int)inst_idx);
  460. return -1;
  461. }
  462. vdi->pvip->vpu_instance_num = inst_info.inst_open_count;
  463. return 0;
  464. }
  465. int vdi_get_instance_num(unsigned long core_idx)
  466. {
  467. vdi_info_t *vdi;
  468. if (core_idx >= MAX_NUM_VPU_CORE)
  469. return -1;
  470. vdi = &s_vdi_info[core_idx];
  471. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  472. return -1;
  473. return vdi->pvip->vpu_instance_num;
  474. }
  475. int vdi_hw_reset(unsigned long core_idx) // DEVICE_ADDR_SW_RESET
  476. {
  477. vdi_info_t *vdi;
  478. if (core_idx >= MAX_NUM_VPU_CORE)
  479. return -1;
  480. vdi = &s_vdi_info[core_idx];
  481. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  482. return -1;
  483. return ioctl(vdi->vpu_fd, VDI_IOCTL_RESET, 0);
  484. }
  485. #if defined(ANDROID) || !defined(PTHREAD_MUTEX_ROBUST_NP)
  486. static void restore_mutex_in_dead(MUTEX_HANDLE *mutex)
  487. {
  488. int mutex_value;
  489. if (!mutex)
  490. return;
  491. #if defined(ANDROID)
  492. mutex_value = mutex->value;
  493. #else
  494. memcpy(&mutex_value, mutex, sizeof(mutex_value));
  495. #endif
  496. if (mutex_value == (int)0xdead10cc) // destroy by device driver
  497. {
  498. pthread_mutexattr_t mutexattr;
  499. pthread_mutexattr_init(&mutexattr);
  500. pthread_mutexattr_setpshared(&mutexattr, PTHREAD_PROCESS_SHARED);
  501. pthread_mutex_init(mutex, &mutexattr);
  502. }
  503. }
  504. #endif
  505. int vdi_lock(unsigned long core_idx)
  506. {
  507. vdi_info_t *vdi;
  508. if (core_idx >= MAX_NUM_VPU_CORE)
  509. return -1;
  510. vdi = &s_vdi_info[core_idx];
  511. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  512. return -1;
  513. #if defined(ANDROID) || !defined(PTHREAD_MUTEX_ROBUST_NP)
  514. restore_mutex_in_dead((MUTEX_HANDLE *)vdi->vpu_mutex);
  515. pthread_mutex_lock((MUTEX_HANDLE*)vdi->vpu_mutex);
  516. #else
  517. int ret = -1;
  518. ret = pthread_mutex_lock((MUTEX_HANDLE *)vdi->vpu_mutex);
  519. if (ret != 0)
  520. {
  521. if (ret == EOWNERDEAD)
  522. ret = pthread_mutex_consistent((MUTEX_HANDLE *)vdi->vpu_mutex);
  523. if (ret != 0)
  524. {
  525. VLOG(ERR, "%s:%d failed to pthread_mutex_locK\n", __FUNCTION__, __LINE__);
  526. return -1;
  527. }
  528. }
  529. #endif
  530. return 0;
  531. }
  532. int vdi_lock_check(unsigned long core_idx)
  533. {
  534. vdi_info_t *vdi;
  535. int ret;
  536. if (core_idx >= MAX_NUM_VPU_CORE)
  537. return -1;
  538. vdi = &s_vdi_info[core_idx];
  539. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  540. return -1;
  541. ret = pthread_mutex_trylock((MUTEX_HANDLE *)vdi->vpu_mutex);
  542. if(ret == 0)
  543. {
  544. vdi_unlock(core_idx);
  545. return -1;
  546. }
  547. else
  548. {
  549. return 0;
  550. }
  551. }
  552. void vdi_unlock(unsigned long core_idx)
  553. {
  554. vdi_info_t *vdi;
  555. if (core_idx >= MAX_NUM_VPU_CORE)
  556. return;
  557. vdi = &s_vdi_info[core_idx];
  558. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  559. return;
  560. pthread_mutex_unlock((MUTEX_HANDLE *)vdi->vpu_mutex);
  561. }
  562. int vdi_disp_lock(unsigned long core_idx)
  563. {
  564. vdi_info_t *vdi;
  565. if (core_idx >= MAX_NUM_VPU_CORE)
  566. return -1;
  567. vdi = &s_vdi_info[core_idx];
  568. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  569. return -1;
  570. #if defined(ANDROID) || !defined(PTHREAD_MUTEX_ROBUST_NP)
  571. restore_mutex_in_dead((MUTEX_HANDLE *)vdi->vpu_disp_mutex);
  572. pthread_mutex_lock((MUTEX_HANDLE*)vdi->vpu_disp_mutex);
  573. #else
  574. int ret = -1;
  575. ret = pthread_mutex_lock((MUTEX_HANDLE *)vdi->vpu_disp_mutex);
  576. if (ret != 0)
  577. {
  578. if (ret == EOWNERDEAD)
  579. ret = pthread_mutex_consistent((MUTEX_HANDLE *)vdi->vpu_disp_mutex);
  580. if (ret != 0)
  581. {
  582. VLOG(ERR, "%s:%d failed to pthread_mutex_lock\n", __FUNCTION__, __LINE__);
  583. return -1;
  584. }
  585. }
  586. #endif /* ANDROID */
  587. return 0;
  588. }
  589. void vdi_disp_unlock(unsigned long core_idx)
  590. {
  591. vdi_info_t *vdi;
  592. if (core_idx >= MAX_NUM_VPU_CORE)
  593. return;
  594. vdi = &s_vdi_info[core_idx];
  595. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  596. return;
  597. pthread_mutex_unlock((MUTEX_HANDLE *)vdi->vpu_disp_mutex);
  598. }
  599. void vdi_write_register(unsigned long core_idx, unsigned int addr, unsigned int data)
  600. {
  601. vdi_info_t *vdi;
  602. unsigned long *reg_addr;
  603. if (core_idx >= MAX_NUM_VPU_CORE)
  604. return;
  605. vdi = &s_vdi_info[core_idx];
  606. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  607. return;
  608. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  609. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr + (core_idx*VPU_CORE_BASE_OFFSET));
  610. #else
  611. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr);
  612. #endif
  613. *(volatile unsigned int *)reg_addr = data;
  614. }
  615. unsigned int vdi_read_register(unsigned long core_idx, unsigned int addr)
  616. {
  617. vdi_info_t *vdi;
  618. unsigned long *reg_addr;
  619. if (core_idx >= MAX_NUM_VPU_CORE)
  620. return (unsigned int)-1;
  621. vdi = &s_vdi_info[core_idx];
  622. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  623. return (unsigned int)-1;
  624. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  625. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr + (core_idx*VPU_CORE_BASE_OFFSET));
  626. #else
  627. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr);
  628. #endif
  629. return *(volatile unsigned int *)reg_addr;
  630. }
  631. #define FIO_TIMEOUT 100
  632. unsigned int vdi_fio_read_register(unsigned long core_idx, unsigned int addr)
  633. {
  634. unsigned int ctrl;
  635. unsigned int count = 0;
  636. unsigned int data = 0xffffffff;
  637. ctrl = (addr&0xffff);
  638. ctrl |= (0<<16); /* read operation */
  639. vdi_write_register(core_idx, W4_VPU_FIO_CTRL_ADDR, ctrl);
  640. count = FIO_TIMEOUT;
  641. while (count--) {
  642. ctrl = vdi_read_register(core_idx, W4_VPU_FIO_CTRL_ADDR);
  643. if (ctrl & 0x80000000) {
  644. data = vdi_read_register(core_idx, W4_VPU_FIO_DATA);
  645. break;
  646. }
  647. }
  648. return data;
  649. }
  650. void vdi_fio_write_register(unsigned long core_idx, unsigned int addr, unsigned int data)
  651. {
  652. unsigned int ctrl;
  653. vdi_write_register(core_idx, W4_VPU_FIO_DATA, data);
  654. ctrl = (addr&0xffff);
  655. ctrl |= (1<<16); /* write operation */
  656. vdi_write_register(core_idx, W4_VPU_FIO_CTRL_ADDR, ctrl);
  657. }
  658. #define VCORE_DBG_ADDR(__vCoreIdx) 0x8000+(0x1000*__vCoreIdx) + 0x300
  659. #define VCORE_DBG_DATA(__vCoreIdx) 0x8000+(0x1000*__vCoreIdx) + 0x304
  660. #define VCORE_DBG_READY(__vCoreIdx) 0x8000+(0x1000*__vCoreIdx) + 0x308
  661. static void UNREFERENCED_FUNCTION write_vce_register(
  662. unsigned int core_idx,
  663. unsigned int vce_core_idx,
  664. unsigned int vce_addr,
  665. unsigned int udata
  666. )
  667. {
  668. int vcpu_reg_addr;
  669. vdi_fio_write_register(core_idx, VCORE_DBG_READY(vce_core_idx),0);
  670. vcpu_reg_addr = vce_addr >> 2;
  671. vdi_fio_write_register(core_idx, VCORE_DBG_DATA(vce_core_idx),udata);
  672. vdi_fio_write_register(core_idx, VCORE_DBG_ADDR(vce_core_idx),(vcpu_reg_addr) & 0x00007FFF);
  673. while (vdi_fio_read_register(0, VCORE_DBG_READY(vce_core_idx)) < 0) {
  674. VLOG(ERR, "failed to write VCE register: 0x%04x\n", vce_addr);
  675. }
  676. }
  677. static unsigned int read_vce_register(
  678. unsigned int core_idx,
  679. unsigned int vce_core_idx,
  680. unsigned int vce_addr
  681. )
  682. {
  683. int vcpu_reg_addr;
  684. int udata;
  685. int vce_core_base = 0x8000 + 0x1000*vce_core_idx;
  686. vdi_fio_write_register(core_idx, VCORE_DBG_READY(vce_core_idx), 0);
  687. vcpu_reg_addr = vce_addr >> 2;
  688. vdi_fio_write_register(core_idx, VCORE_DBG_ADDR(vce_core_idx),vcpu_reg_addr + vce_core_base);
  689. while (TRUE) {
  690. if (vdi_fio_read_register(0, VCORE_DBG_READY(vce_core_idx)) == 1) {
  691. udata= vdi_fio_read_register(0, VCORE_DBG_DATA(vce_core_idx));
  692. break;
  693. }
  694. }
  695. return udata;
  696. }
  697. int vdi_clear_memory(unsigned long core_idx, unsigned int addr, int len, int endian)
  698. {
  699. vdi_info_t *vdi;
  700. vpudrv_buffer_t vdb;
  701. unsigned long offset;
  702. int i;
  703. Uint8* zero;
  704. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  705. core_idx = 0;
  706. #endif
  707. if (core_idx >= MAX_NUM_VPU_CORE)
  708. return -1;
  709. vdi = &s_vdi_info[core_idx];
  710. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  711. return -1;
  712. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  713. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  714. {
  715. if (vdi->vpu_buffer_pool[i].inuse == 1)
  716. {
  717. vdb = vdi->vpu_buffer_pool[i].vdb;
  718. if (addr >= vdb.phys_addr && addr < (vdb.phys_addr + vdb.size))
  719. break;
  720. }
  721. }
  722. if (!vdb.size) {
  723. VLOG(ERR, "address 0x%08x is not mapped address!!!\n", (int)addr);
  724. return -1;
  725. }
  726. zero = (Uint8*)osal_malloc(len);
  727. osal_memset((void*)zero, 0x00, len);
  728. offset = addr - (unsigned long)vdb.phys_addr;
  729. vdi_flush_ddr(core_idx,(unsigned long )(vdb.phys_addr+offset),len,1); //invalid cache before clear
  730. osal_memcpy((void *)((unsigned long)vdb.virt_addr+offset), zero, len);
  731. osal_free(zero);
  732. return len;
  733. }
  734. void vdi_set_sdram(unsigned long coreIdx, unsigned int addr, int len, unsigned char data, int endian)
  735. {
  736. vdi_info_t *vdi = &s_vdi_info[coreIdx];
  737. unsigned char *buf;
  738. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  739. return ;
  740. buf = (unsigned char *)osal_malloc(len);
  741. memset(buf, 0x00, len);
  742. vdi_write_memory(coreIdx, addr, buf, len, endian);
  743. free(buf);
  744. }
  745. int vdi_write_memory(unsigned long core_idx, unsigned int addr, unsigned char *data, int len, int endian)
  746. {
  747. vdi_info_t *vdi;
  748. vpudrv_buffer_t vdb;
  749. unsigned long offset;
  750. int i;
  751. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  752. core_idx = 0;
  753. #endif
  754. if (core_idx >= MAX_NUM_VPU_CORE)
  755. return -1;
  756. vdi = &s_vdi_info[core_idx];
  757. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  758. return -1;
  759. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  760. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  761. {
  762. if (vdi->vpu_buffer_pool[i].inuse == 1)
  763. {
  764. vdb = vdi->vpu_buffer_pool[i].vdb;
  765. if (addr >= vdb.phys_addr && addr < (vdb.phys_addr + vdb.size)) {
  766. break;
  767. }
  768. }
  769. }
  770. if (!vdb.size) {
  771. VLOG(ERR, "address 0x%08x is not mapped address!!!\n", (int)addr);
  772. return -1;
  773. }
  774. offset = addr - (unsigned long)vdb.phys_addr;
  775. swap_endian(core_idx, data, len, endian);
  776. osal_memcpy((void *)((unsigned long)vdb.virt_addr+offset), data, len);
  777. return len;
  778. }
  779. int vdi_read_memory(unsigned long core_idx, unsigned int addr, unsigned char *data, int len, int endian)
  780. {
  781. vdi_info_t *vdi;
  782. vpudrv_buffer_t vdb;
  783. unsigned long offset;
  784. int i;
  785. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  786. core_idx = 0;
  787. #endif
  788. if (core_idx >= MAX_NUM_VPU_CORE)
  789. return -1;
  790. vdi = &s_vdi_info[core_idx];
  791. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  792. return -1;
  793. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  794. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  795. {
  796. if (vdi->vpu_buffer_pool[i].inuse == 1)
  797. {
  798. vdb = vdi->vpu_buffer_pool[i].vdb;
  799. if (addr >= vdb.phys_addr && addr < (vdb.phys_addr + vdb.size))
  800. break;
  801. }
  802. }
  803. if (!vdb.size)
  804. {
  805. return -1;
  806. }
  807. offset = addr - (unsigned long)vdb.phys_addr;
  808. osal_memcpy(data, (const void *)((unsigned long)vdb.virt_addr+offset), len);
  809. swap_endian(core_idx, data, len, endian);
  810. return len;
  811. }
  812. int vdi_allocate_dma_memory(unsigned long core_idx, vpu_buffer_t *vb)
  813. {
  814. vdi_info_t *vdi;
  815. int i;
  816. vpudrv_buffer_t vdb;
  817. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  818. core_idx = 0;
  819. #endif
  820. if (core_idx >= MAX_NUM_VPU_CORE)
  821. return -1;
  822. vdi = &s_vdi_info[core_idx];
  823. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  824. return -1;
  825. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  826. vdb.size = vb->size;
  827. if (ioctl(vdi->vpu_fd, VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY, &vdb) < 0)
  828. {
  829. VLOG(ERR, "[VDI] fail to vdi_allocate_dma_memory size=%d\n", vb->size);
  830. return -1;
  831. }
  832. vb->phys_addr = (unsigned long)vdb.phys_addr;
  833. vb->base = (unsigned long)vdb.base;
  834. //map to virtual address
  835. //vdb.virt_addr = (unsigned long)mmap(NULL, vdb.size, PROT_READ | PROT_WRITE,
  836. // MAP_SHARED, vdi->vpu_fd, vdb.phys_addr);
  837. vdb.virt_addr = (unsigned long)mmap(NULL, vdb.size, PROT_READ | PROT_WRITE,
  838. MAP_SHARED, vdi->vpu_fd, DRAM_MEM2SYS(vdb.phys_addr));
  839. if ((void *)vdb.virt_addr == MAP_FAILED)
  840. {
  841. memset(vb, 0x00, sizeof(vpu_buffer_t));
  842. return -1;
  843. }
  844. vb->virt_addr = vdb.virt_addr;
  845. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  846. {
  847. if (vdi->vpu_buffer_pool[i].inuse == 0)
  848. {
  849. vdi->vpu_buffer_pool[i].vdb = vdb;
  850. vdi->vpu_buffer_pool_count++;
  851. vdi->vpu_buffer_pool[i].inuse = 1;
  852. break;
  853. }
  854. }
  855. VLOG(INFO, "[VDI] vdi_allocate_dma_memory, physaddr=%p, virtaddr=%p~%p, size=%d\n",
  856. vb->phys_addr, vb->virt_addr, vb->virt_addr + vb->size, vb->size);
  857. return 0;
  858. }
  859. int vdi_attach_dma_memory(unsigned long core_idx, vpu_buffer_t *vb)
  860. {
  861. vdi_info_t *vdi;
  862. int i;
  863. vpudrv_buffer_t vdb;
  864. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  865. core_idx = 0;
  866. #endif
  867. if (core_idx >= MAX_NUM_VPU_CORE)
  868. return -1;
  869. vdi = &s_vdi_info[core_idx];
  870. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  871. return -1;
  872. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  873. vdb.size = vb->size;
  874. vdb.phys_addr = vb->phys_addr;
  875. vdb.base = vb->base;
  876. vdb.virt_addr = vb->virt_addr;
  877. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  878. {
  879. if (vdi->vpu_buffer_pool[i].vdb.phys_addr == vb->phys_addr)
  880. {
  881. vdi->vpu_buffer_pool[i].vdb = vdb;
  882. vdi->vpu_buffer_pool[i].inuse = 1;
  883. break;
  884. }
  885. else
  886. {
  887. if (vdi->vpu_buffer_pool[i].inuse == 0)
  888. {
  889. vdi->vpu_buffer_pool[i].vdb = vdb;
  890. vdi->vpu_buffer_pool_count++;
  891. vdi->vpu_buffer_pool[i].inuse = 1;
  892. break;
  893. }
  894. }
  895. }
  896. //VLOG(INFO, "[VDI] vdi_attach_dma_memory, physaddr=0x%lx, virtaddr=0x%lx, size=%d, index=%d\n", vb->phys_addr, vb->virt_addr, vb->size, i);
  897. return 0;
  898. }
  899. int vdi_dettach_dma_memory(unsigned long core_idx, vpu_buffer_t *vb)
  900. {
  901. vdi_info_t *vdi;
  902. int i;
  903. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  904. core_idx = 0;
  905. #endif
  906. if (core_idx >= MAX_NUM_VPU_CORE)
  907. return -1;
  908. vdi = &s_vdi_info[core_idx];
  909. if(!vb || !vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  910. return -1;
  911. if (vb->size == 0)
  912. return -1;
  913. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  914. {
  915. if (vdi->vpu_buffer_pool[i].vdb.phys_addr == vb->phys_addr)
  916. {
  917. vdi->vpu_buffer_pool[i].inuse = 0;
  918. vdi->vpu_buffer_pool_count--;
  919. break;
  920. }
  921. }
  922. return 0;
  923. }
  924. void vdi_free_dma_memory(unsigned long core_idx, vpu_buffer_t *vb)
  925. {
  926. vdi_info_t *vdi;
  927. int i;
  928. vpudrv_buffer_t vdb;
  929. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  930. core_idx = 0;
  931. #endif
  932. if (core_idx >= MAX_NUM_VPU_CORE)
  933. return;
  934. vdi = &s_vdi_info[core_idx];
  935. if(!vb || !vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  936. return;
  937. if (vb->size == 0)
  938. return ;
  939. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  940. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  941. {
  942. if (vdi->vpu_buffer_pool[i].vdb.phys_addr == vb->phys_addr)
  943. {
  944. vdi->vpu_buffer_pool[i].inuse = 0;
  945. vdi->vpu_buffer_pool_count--;
  946. vdb = vdi->vpu_buffer_pool[i].vdb;
  947. break;
  948. }
  949. }
  950. if (!vdb.size)
  951. {
  952. VLOG(ERR, "[VDI] invalid buffer to free address = 0x%lx\n", (int)vdb.virt_addr);
  953. return ;
  954. }
  955. ioctl(vdi->vpu_fd, VDI_IOCTL_FREE_PHYSICALMEMORY, &vdb);
  956. if (munmap((void *)vdb.virt_addr, vdb.size) != 0)
  957. {
  958. VLOG(ERR, "[VDI] fail to vdi_free_dma_memory virtial address = 0x%lx\n", (int)vdb.virt_addr);
  959. }
  960. osal_memset(vb, 0, sizeof(vpu_buffer_t));
  961. }
  962. int vdi_get_sram_memory(unsigned long core_idx, vpu_buffer_t *vb)
  963. {
  964. vdi_info_t *vdi = NULL;
  965. vpudrv_buffer_t vdb;
  966. unsigned int sram_size = 0;
  967. if (core_idx >= MAX_NUM_VPU_CORE)
  968. return -1;
  969. vdi = &s_vdi_info[core_idx];
  970. if(!vb || !vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  971. return -1;
  972. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  973. switch (vdi->product_code) {
  974. case WAVE410_CODE:
  975. case WAVE4102_CODE:
  976. case WAVE510_CODE:
  977. sram_size = VDI_WAVE410_SRAM_SIZE; break;
  978. case WAVE420_CODE:
  979. sram_size = VDI_WAVE420_SRAM_SIZE; break;
  980. case WAVE420L_CODE:
  981. sram_size = VDI_WAVE420L_SRAM_SIZE; break;
  982. case BODA7503_CODE:
  983. case CODA7542_CODE:
  984. case BODA950_CODE:
  985. case CODA960_CODE:
  986. case CODA980_CODE:
  987. case WAVE320_CODE:
  988. case CODA7Q_CODE:
  989. sram_size = VDI_CODA9_SRAM_SIZE; break;
  990. case WAVE412_CODE:
  991. sram_size = VDI_WAVE412_SRAM_SIZE; break;
  992. case WAVE512_CODE:
  993. sram_size = VDI_WAVE512_SRAM_SIZE; break;
  994. case WAVE515_CODE:
  995. sram_size = VDI_WAVE515_SRAM_SIZE; break;
  996. case WAVE520_CODE:
  997. sram_size = VDI_WAVE520_SRAM_SIZE; break;
  998. default:
  999. VLOG(ERR, "Check SRAM_SIZE(%d)\n", vdi->product_code);
  1000. break;
  1001. }
  1002. if (sram_size > 0) // if we can know the sram address directly in vdi layer, we use it first for sdram address
  1003. {
  1004. vb->phys_addr = VDI_SRAM_BASE_ADDR+(core_idx*sram_size); // HOST can set DRAM base addr to VDI_SRAM_BASE_ADDR.
  1005. vb->size = sram_size;
  1006. return 0;
  1007. }
  1008. return 0;
  1009. }
  1010. int vdi_set_clock_gate(unsigned long core_idx, int enable)
  1011. {
  1012. vdi_info_t *vdi = NULL;
  1013. int ret;
  1014. if (core_idx >= MAX_NUM_VPU_CORE)
  1015. return -1;
  1016. vdi = &s_vdi_info[core_idx];
  1017. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  1018. return -1;
  1019. if (vdi->product_code == WAVE510_CODE || vdi->product_code == WAVE512_CODE || vdi->product_code == WAVE515_CODE) {
  1020. return 0;
  1021. }
  1022. vdi->clock_state = enable;
  1023. ret = ioctl(vdi->vpu_fd, VDI_IOCTL_SET_CLOCK_GATE, &enable);
  1024. return ret;
  1025. }
  1026. int vdi_get_clock_gate(unsigned long core_idx)
  1027. {
  1028. vdi_info_t *vdi;
  1029. int ret;
  1030. if (core_idx >= MAX_NUM_VPU_CORE)
  1031. return -1;
  1032. vdi = &s_vdi_info[core_idx];
  1033. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  1034. return -1;
  1035. ret = vdi->clock_state;
  1036. return ret;
  1037. }
  1038. int vdi_wait_bus_busy(unsigned long core_idx, int timeout, unsigned int gdi_busy_flag)
  1039. {
  1040. Int64 elapse, cur;
  1041. struct timeval tv;
  1042. vdi_info_t *vdi;
  1043. vdi = &s_vdi_info[core_idx];
  1044. tv.tv_sec = 0;
  1045. tv.tv_usec = 0;
  1046. gettimeofday(&tv, NULL);
  1047. elapse = tv.tv_sec*1000 + tv.tv_usec/1000;
  1048. while(1)
  1049. {
  1050. if (vdi->product_code == WAVE420L_CODE) {
  1051. if (vdi_fio_read_register(core_idx, gdi_busy_flag) == 0) {
  1052. break;
  1053. }
  1054. }
  1055. else if (vdi->product_code == WAVE520_CODE) {
  1056. if (vdi_fio_read_register(core_idx, gdi_busy_flag) == 0x3f) break;
  1057. }
  1058. else if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  1059. if (vdi_fio_read_register(core_idx, gdi_busy_flag) == 0x738) break;
  1060. }
  1061. else if (PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  1062. if (vdi_read_register(core_idx, gdi_busy_flag) == 0x77) break;
  1063. }
  1064. else {
  1065. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1066. return -1;
  1067. }
  1068. if (timeout > 0) {
  1069. gettimeofday(&tv, NULL);
  1070. cur = tv.tv_sec * 1000 + tv.tv_usec / 1000;
  1071. if ((cur - elapse) > timeout) {
  1072. VLOG(ERR, "[VDI] vdi_wait_bus_busy timeout, PC=0x%lx\n", vdi_read_register(core_idx, 0x018));
  1073. return -1;
  1074. }
  1075. }
  1076. }
  1077. return 0;
  1078. }
  1079. int vdi_wait_vpu_busy(unsigned long core_idx, int timeout, unsigned int addr_bit_busy_flag)
  1080. {
  1081. Int64 elapse, cur;
  1082. struct timeval tv;
  1083. Uint32 pc;
  1084. Uint32 code, normalReg = TRUE;
  1085. tv.tv_sec = 0;
  1086. tv.tv_usec = 0;
  1087. gettimeofday(&tv, NULL);
  1088. elapse = tv.tv_sec*1000 + tv.tv_usec/1000;
  1089. code = vdi_read_register(core_idx, VPU_PRODUCT_CODE_REGISTER); /* read product code */
  1090. if (PRODUCT_CODE_W_SERIES(code)) {
  1091. pc = W4_VCPU_CUR_PC;
  1092. if (addr_bit_busy_flag&0x8000) normalReg = FALSE;
  1093. }
  1094. else if (PRODUCT_CODE_NOT_W_SERIES(code)) {
  1095. pc = BIT_CUR_PC;
  1096. }
  1097. else {
  1098. VLOG(ERR, "Unknown product id : %08x\n", code);
  1099. return -1;
  1100. }
  1101. while(1)
  1102. {
  1103. if (normalReg == TRUE) {
  1104. if (vdi_read_register(core_idx, addr_bit_busy_flag) == 0) break;
  1105. }
  1106. else {
  1107. if (vdi_fio_read_register(core_idx, addr_bit_busy_flag) == 0) break;
  1108. }
  1109. if (timeout > 0) {
  1110. gettimeofday(&tv, NULL);
  1111. cur = tv.tv_sec * 1000 + tv.tv_usec / 1000;
  1112. if ((cur - elapse) > timeout) {
  1113. Uint32 index;
  1114. for (index=0; index<50; index++) {
  1115. VLOG(ERR, "[VDI] vdi_wait_vpu_busy timeout, PC=0x%lx\n", vdi_read_register(core_idx, pc));
  1116. }
  1117. return -1;
  1118. }
  1119. }
  1120. }
  1121. return 0;
  1122. }
  1123. int vdi_wait_interrupt(unsigned long coreIdx, int timeout, unsigned int addr_bit_int_reason)
  1124. {
  1125. int intr_reason = 0;
  1126. int ret;
  1127. vdi_info_t *vdi;
  1128. vpudrv_intr_info_t intr_info;
  1129. if (coreIdx >= MAX_NUM_VPU_CORE)
  1130. return -1;
  1131. vdi = &s_vdi_info[coreIdx];
  1132. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  1133. return -1;
  1134. #ifdef SUPPORT_INTERRUPT
  1135. intr_info.timeout = timeout;
  1136. intr_info.intr_reason = 0;
  1137. ret = ioctl(vdi->vpu_fd, VDI_IOCTL_WAIT_INTERRUPT, (void*)&intr_info);
  1138. if (ret != 0)
  1139. return -1;
  1140. intr_reason = intr_info.intr_reason;
  1141. #else
  1142. struct timeval tv = {0};
  1143. Uint32 intrStatusReg;
  1144. Uint32 pc;
  1145. Int32 startTime, endTime, elaspedTime;
  1146. UNREFERENCED_PARAMETER(intr_info);
  1147. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  1148. pc = W4_VCPU_CUR_PC;
  1149. intrStatusReg = W4_VPU_VPU_INT_STS;
  1150. }
  1151. else if (PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  1152. pc = BIT_CUR_PC;
  1153. intrStatusReg = BIT_INT_STS;
  1154. }
  1155. else {
  1156. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1157. return -1;
  1158. }
  1159. gettimeofday(&tv, NULL);
  1160. startTime = tv.tv_sec*1000 + tv.tv_usec/1000;
  1161. while (TRUE) {
  1162. if (vdi_read_register(coreIdx, intrStatusReg)) {
  1163. if ((intr_reason=vdi_read_register(coreIdx, addr_bit_int_reason)))
  1164. break;
  1165. }
  1166. gettimeofday(&tv, NULL);
  1167. endTime = tv.tv_sec*1000 + tv.tv_usec/1000;
  1168. if (timeout > 0 && (endTime-startTime) >= timeout) {
  1169. return -1;
  1170. }
  1171. }
  1172. #endif
  1173. return intr_reason;
  1174. }
  1175. static int read_pinfo_buffer(int core_idx, int addr)
  1176. {
  1177. int ack;
  1178. int rdata;
  1179. #define VDI_LOG_GDI_PINFO_ADDR (0x1068)
  1180. #define VDI_LOG_GDI_PINFO_REQ (0x1060)
  1181. #define VDI_LOG_GDI_PINFO_ACK (0x1064)
  1182. #define VDI_LOG_GDI_PINFO_DATA (0x106c)
  1183. //------------------------------------------
  1184. // read pinfo - indirect read
  1185. // 1. set read addr (GDI_PINFO_ADDR)
  1186. // 2. send req (GDI_PINFO_REQ)
  1187. // 3. wait until ack==1 (GDI_PINFO_ACK)
  1188. // 4. read data (GDI_PINFO_DATA)
  1189. //------------------------------------------
  1190. vdi_write_register(core_idx, VDI_LOG_GDI_PINFO_ADDR, addr);
  1191. vdi_write_register(core_idx, VDI_LOG_GDI_PINFO_REQ, 1);
  1192. ack = 0;
  1193. while (ack == 0)
  1194. {
  1195. ack = vdi_read_register(core_idx, VDI_LOG_GDI_PINFO_ACK);
  1196. }
  1197. rdata = vdi_read_register(core_idx, VDI_LOG_GDI_PINFO_DATA);
  1198. //printf("[READ PINFO] ADDR[%x], DATA[%x]", addr, rdata);
  1199. return rdata;
  1200. }
  1201. enum {
  1202. VDI_PRODUCT_ID_980,
  1203. VDI_PRODUCT_ID_960
  1204. };
  1205. static void printf_gdi_info(int core_idx, int num, int reset)
  1206. {
  1207. int i;
  1208. int bus_info_addr;
  1209. int tmp;
  1210. int val;
  1211. int productId;
  1212. val = vdi_read_register(core_idx, VPU_PRODUCT_CODE_REGISTER);
  1213. if ((val&0xff00) == 0x3200) val = 0x3200;
  1214. if (PRODUCT_CODE_W_SERIES(val)) {
  1215. return;
  1216. }
  1217. else if (PRODUCT_CODE_NOT_W_SERIES(val)) {
  1218. if (val == CODA960_CODE || val == BODA950_CODE)
  1219. productId = VDI_PRODUCT_ID_960;
  1220. else if (val == CODA980_CODE || val == WAVE320_CODE)
  1221. productId = VDI_PRODUCT_ID_980;
  1222. }
  1223. else {
  1224. VLOG(ERR, "Unknown product id : %08x\n", val);
  1225. return;
  1226. }
  1227. if (productId == VDI_PRODUCT_ID_980)
  1228. VLOG(INFO, "\n**GDI information for GDI_20\n");
  1229. else
  1230. VLOG(INFO, "\n**GDI information for GDI_10\n");
  1231. for (i=0; i < num; i++)
  1232. {
  1233. #define VDI_LOG_GDI_INFO_CONTROL 0x1400
  1234. if (productId == VDI_PRODUCT_ID_980)
  1235. bus_info_addr = VDI_LOG_GDI_INFO_CONTROL + i*(0x20);
  1236. else
  1237. bus_info_addr = VDI_LOG_GDI_INFO_CONTROL + i*0x14;
  1238. if (reset)
  1239. {
  1240. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1241. bus_info_addr += 4;
  1242. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1243. bus_info_addr += 4;
  1244. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1245. bus_info_addr += 4;
  1246. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1247. bus_info_addr += 4;
  1248. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1249. if (productId == VDI_PRODUCT_ID_980)
  1250. {
  1251. bus_info_addr += 4;
  1252. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1253. bus_info_addr += 4;
  1254. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1255. bus_info_addr += 4;
  1256. vdi_write_register(core_idx, bus_info_addr, 0x00);
  1257. }
  1258. }
  1259. else
  1260. {
  1261. VLOG(INFO, "index = %02d", i);
  1262. tmp = read_pinfo_buffer(core_idx, bus_info_addr); //TiledEn<<20 ,GdiFormat<<17,IntlvCbCr,<<16 GdiYuvBufStride
  1263. VLOG(INFO, " control = 0x%08x", tmp);
  1264. bus_info_addr += 4;
  1265. tmp = read_pinfo_buffer(core_idx, bus_info_addr);
  1266. VLOG(INFO, " pic_size = 0x%08x", tmp);
  1267. bus_info_addr += 4;
  1268. tmp = read_pinfo_buffer(core_idx, bus_info_addr);
  1269. VLOG(INFO, " y-top = 0x%08x", tmp);
  1270. bus_info_addr += 4;
  1271. tmp = read_pinfo_buffer(core_idx, bus_info_addr);
  1272. VLOG(INFO, " cb-top = 0x%08x", tmp);
  1273. bus_info_addr += 4;
  1274. tmp = read_pinfo_buffer(core_idx, bus_info_addr);
  1275. VLOG(INFO, " cr-top = 0x%08x", tmp);
  1276. if (productId == VDI_PRODUCT_ID_980)
  1277. {
  1278. bus_info_addr += 4;
  1279. tmp = read_pinfo_buffer(core_idx, bus_info_addr);
  1280. VLOG(INFO, " y-bot = 0x%08x", tmp);
  1281. bus_info_addr += 4;
  1282. tmp = read_pinfo_buffer(core_idx, bus_info_addr);
  1283. VLOG(INFO, " cb-bot = 0x%08x", tmp);
  1284. bus_info_addr += 4;
  1285. tmp = read_pinfo_buffer(core_idx, bus_info_addr);
  1286. VLOG(INFO, " cr-bot = 0x%08x", tmp);
  1287. }
  1288. VLOG(INFO, "\n");
  1289. }
  1290. }
  1291. }
  1292. void vdi_print_vpu_status(unsigned long coreIdx)
  1293. {
  1294. unsigned int product_code;
  1295. product_code = vdi_read_register(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  1296. if (PRODUCT_CODE_W_SERIES(product_code))
  1297. {
  1298. int rd, wr;
  1299. unsigned int tq, ip, mc, lf;
  1300. unsigned int avail_cu, avail_tu, avail_tc, avail_lf, avail_ip;
  1301. unsigned int ctu_fsm, nb_fsm, cabac_fsm, cu_info, mvp_fsm, tc_busy, lf_fsm, bs_data, bbusy, fv;
  1302. unsigned int reg_val;
  1303. unsigned int index;
  1304. unsigned int vcpu_reg[31]= {0,};
  1305. printf("-------------------------------------------------------------------------------\n");
  1306. printf("------ VCPU STATUS -----\n");
  1307. printf("-------------------------------------------------------------------------------\n");
  1308. rd = VpuReadReg(coreIdx, W4_BS_RD_PTR);
  1309. wr = VpuReadReg(coreIdx, W4_BS_WR_PTR);
  1310. printf("RD_PTR: 0x%08x WR_PTR: 0x%08x BS_OPT: 0x%08x BS_PARAM: 0x%08x\n",
  1311. rd, wr, VpuReadReg(coreIdx, W4_BS_OPTION), VpuReadReg(coreIdx, W4_BS_PARAM));
  1312. // --------- VCPU register Dump
  1313. printf("[+] VCPU REG Dump\n");
  1314. for (index = 0; index < 25; index++) {
  1315. VpuWriteReg (coreIdx, 0x14, (1<<9) | (index & 0xff));
  1316. vcpu_reg[index] = VpuReadReg (coreIdx, 0x1c);
  1317. if (index < 16) {
  1318. printf("0x%08x\t", vcpu_reg[index]);
  1319. if ((index % 4) == 3) printf("\n");
  1320. }
  1321. else {
  1322. switch (index) {
  1323. case 16: printf("CR0: 0x%08x\t", vcpu_reg[index]); break;
  1324. case 17: printf("CR1: 0x%08x\n", vcpu_reg[index]); break;
  1325. case 18: printf("ML: 0x%08x\t", vcpu_reg[index]); break;
  1326. case 19: printf("MH: 0x%08x\n", vcpu_reg[index]); break;
  1327. case 21: printf("LR: 0x%08x\n", vcpu_reg[index]); break;
  1328. case 22: printf("PC: 0x%08x\n", vcpu_reg[index]);break;
  1329. case 23: printf("SR: 0x%08x\n", vcpu_reg[index]);break;
  1330. case 24: printf("SSP: 0x%08x\n", vcpu_reg[index]);break;
  1331. }
  1332. }
  1333. }
  1334. printf("[-] VCPU REG Dump\n");
  1335. // --------- BIT register Dump
  1336. printf("[+] BPU REG Dump\n");
  1337. printf("BITPC = 0x%08x\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x18)));
  1338. printf("BIT START=0x%08x, BIT END=0x%08x\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x11c)),
  1339. vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x120)) );
  1340. if (product_code == WAVE410_CODE )
  1341. printf("BIT COMMAND 0x%x\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x100)));
  1342. if (product_code == WAVE4102_CODE || product_code == WAVE510_CODE)
  1343. printf("BIT COMMAND 0x%x\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x1FC)));
  1344. printf("CODE_BASE %x \n", vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x7000 + 0x18)));
  1345. printf("VCORE_REINIT_FLAG %x \n", vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x7000 + 0x0C)));
  1346. // --------- BIT HEVC Status Dump
  1347. ctu_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x48));
  1348. nb_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x4c));
  1349. cabac_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x50));
  1350. cu_info = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x54));
  1351. mvp_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x58));
  1352. tc_busy = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x5c));
  1353. lf_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x60));
  1354. bs_data = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x64));
  1355. bbusy = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x68));
  1356. fv = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x6C));
  1357. printf("[DEBUG-BPUHEVC] CTU_X: %4d, CTU_Y: %4d\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x40)), vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x44)));
  1358. printf("[DEBUG-BPUHEVC] CTU_FSM> Main: 0x%02x, FIFO: 0x%1x, NB: 0x%02x, DBK: 0x%1x\n", ((ctu_fsm >> 24) & 0xff), ((ctu_fsm >> 16) & 0xff), ((ctu_fsm >> 8) & 0xff), (ctu_fsm & 0xff));
  1359. printf("[DEBUG-BPUHEVC] NB_FSM: 0x%02x\n", nb_fsm & 0xff);
  1360. printf("[DEBUG-BPUHEVC] CABAC_FSM> SAO: 0x%02x, CU: 0x%02x, PU: 0x%02x, TU: 0x%02x, EOS: 0x%02x\n", ((cabac_fsm>>25) & 0x3f), ((cabac_fsm>>19) & 0x3f), ((cabac_fsm>>13) & 0x3f), ((cabac_fsm>>6) & 0x7f), (cabac_fsm & 0x3f));
  1361. printf("[DEBUG-BPUHEVC] CU_INFO value = 0x%04x \n\t\t(l2cb: 0x%1x, cux: %1d, cuy; %1d, pred: %1d, pcm: %1d, wr_done: %1d, par_done: %1d, nbw_done: %1d, dec_run: %1d)\n", cu_info,
  1362. ((cu_info>> 16) & 0x3), ((cu_info>> 13) & 0x7), ((cu_info>> 10) & 0x7), ((cu_info>> 9) & 0x3), ((cu_info>> 8) & 0x1), ((cu_info>> 6) & 0x3), ((cu_info>> 4) & 0x3), ((cu_info>> 2) & 0x3), (cu_info & 0x3));
  1363. printf("[DEBUG-BPUHEVC] MVP_FSM> 0x%02x\n", mvp_fsm & 0xf);
  1364. printf("[DEBUG-BPUHEVC] TC_BUSY> tc_dec_busy: %1d, tc_fifo_busy: 0x%02x\n", ((tc_busy >> 3) & 0x1), (tc_busy & 0x7));
  1365. printf("[DEBUG-BPUHEVC] LF_FSM> SAO: 0x%1x, LF: 0x%1x\n", ((lf_fsm >> 4) & 0xf), (lf_fsm & 0xf));
  1366. printf("[DEBUG-BPUHEVC] BS_DATA> ExpEnd=%1d, bs_valid: 0x%03x, bs_data: 0x%03x\n", ((bs_data >> 31) & 0x1), ((bs_data >> 16) & 0xfff), (bs_data & 0xfff));
  1367. printf("[DEBUG-BPUHEVC] BUS_BUSY> mib_wreq_done: %1d, mib_busy: %1d, sdma_bus: %1d\n", ((bbusy >> 2) & 0x1), ((bbusy >> 1) & 0x1) , (bbusy & 0x1));
  1368. printf("[DEBUG-BPUHEVC] FIFO_VALID> cu: %1d, tu: %1d, iptu: %1d, lf: %1d, coff: %1d\n\n", ((fv >> 4) & 0x1), ((fv >> 3) & 0x1), ((fv >> 2) & 0x1), ((fv >> 1) & 0x1), (fv & 0x1));
  1369. printf("[-] BPU REG Dump\n");
  1370. // --------- VCE register Dump
  1371. printf("[+] VCE REG Dump\n");
  1372. tq = read_vce_register(0, 0, 0xd0);
  1373. ip = read_vce_register(0, 0, 0xd4);
  1374. mc = read_vce_register(0, 0, 0xd8);
  1375. lf = read_vce_register(0, 0, 0xdc);
  1376. avail_cu = (read_vce_register(0, 0, 0x11C)>>16) - (read_vce_register(0, 0, 0x110)>>16);
  1377. avail_tu = (read_vce_register(0, 0, 0x11C)&0xFFFF) - (read_vce_register(0, 0, 0x110)&0xFFFF);
  1378. avail_tc = (read_vce_register(0, 0, 0x120)>>16) - (read_vce_register(0, 0, 0x114)>>16);
  1379. avail_lf = (read_vce_register(0, 0, 0x120)&0xFFFF) - (read_vce_register(0, 0, 0x114)&0xFFFF);
  1380. avail_ip = (read_vce_register(0, 0, 0x124)>>16) - (read_vce_register(0, 0, 0x118)>>16);
  1381. printf(" TQ IP MC LF GDI_EMPTY ROOM \n");
  1382. printf("------------------------------------------------------------------------------------------------------------\n");
  1383. printf("| %d %04d %04d | %d %04d %04d | %d %04d %04d | %d %04d %04d | 0x%08x | CU(%d) TU(%d) TC(%d) LF(%d) IP(%d)\n",
  1384. (tq>>22)&0x07, (tq>>11)&0x3ff, tq&0x3ff,
  1385. (ip>>22)&0x07, (ip>>11)&0x3ff, ip&0x3ff,
  1386. (mc>>22)&0x07, (mc>>11)&0x3ff, mc&0x3ff,
  1387. (lf>>22)&0x07, (lf>>11)&0x3ff, lf&0x3ff,
  1388. vdi_fio_read_register(0, 0x88f4), /* GDI empty */
  1389. avail_cu, avail_tu, avail_tc, avail_lf, avail_ip);
  1390. /* CU/TU Queue count */
  1391. reg_val = read_vce_register(0, 0, 0x12C);
  1392. printf("[DCIDEBUG] QUEUE COUNT: CU(%5d) TU(%5d) ", (reg_val>>16)&0xffff, reg_val&0xffff);
  1393. reg_val = read_vce_register(0, 0, 0x1A0);
  1394. printf("TC(%5d) IP(%5d) ", (reg_val>>16)&0xffff, reg_val&0xffff);
  1395. reg_val = read_vce_register(0, 0, 0x1A4);
  1396. printf("LF(%5d)\n", (reg_val>>16)&0xffff);
  1397. printf("VALID SIGNAL : CU0(%d) CU1(%d) CU2(%d) TU(%d) TC(%d) IP(%5d) LF(%5d)\n"
  1398. " DCI_FALSE_RUN(%d) VCE_RESET(%d) CORE_INIT(%d) SET_RUN_CTU(%d) \n",
  1399. (reg_val>>6)&1, (reg_val>>5)&1, (reg_val>>4)&1, (reg_val>>3)&1,
  1400. (reg_val>>2)&1, (reg_val>>1)&1, (reg_val>>0)&1,
  1401. (reg_val>>10)&1, (reg_val>>9)&1, (reg_val>>8)&1, (reg_val>>7)&1);
  1402. printf("State TQ: 0x%08x IP: 0x%08x MC: 0x%08x LF: 0x%08x\n",
  1403. read_vce_register(0, 0, 0xd0), read_vce_register(0, 0, 0xd4), read_vce_register(0, 0, 0xd8), read_vce_register(0, 0, 0xdc));
  1404. printf("BWB[1]: RESPONSE_CNT(0x%08x) INFO(0x%08x)\n", read_vce_register(0, 0, 0x194), read_vce_register(0, 0, 0x198));
  1405. printf("BWB[2]: RESPONSE_CNT(0x%08x) INFO(0x%08x)\n", read_vce_register(0, 0, 0x194), read_vce_register(0, 0, 0x198));
  1406. printf("DCI INFO\n");
  1407. printf("READ_CNT_0 : 0x%08x\n", read_vce_register(0, 0, 0x110));
  1408. printf("READ_CNT_1 : 0x%08x\n", read_vce_register(0, 0, 0x114));
  1409. printf("READ_CNT_2 : 0x%08x\n", read_vce_register(0, 0, 0x118));
  1410. printf("WRITE_CNT_0: 0x%08x\n", read_vce_register(0, 0, 0x11c));
  1411. printf("WRITE_CNT_1: 0x%08x\n", read_vce_register(0, 0, 0x120));
  1412. printf("WRITE_CNT_2: 0x%08x\n", read_vce_register(0, 0, 0x124));
  1413. reg_val = read_vce_register(0, 0, 0x128);
  1414. printf("LF_DEBUG_PT: 0x%08x\n", reg_val & 0xffffffff);
  1415. printf("cur_main_state %2d, r_lf_pic_deblock_disable %1d, r_lf_pic_sao_disable %1d\n",
  1416. (reg_val >> 16) & 0x1f,
  1417. (reg_val >> 15) & 0x1,
  1418. (reg_val >> 14) & 0x1);
  1419. printf("para_load_done %1d, i_rdma_ack_wait %1d, i_sao_intl_col_done %1d, i_sao_outbuf_full %1d\n",
  1420. (reg_val >> 13) & 0x1,
  1421. (reg_val >> 12) & 0x1,
  1422. (reg_val >> 11) & 0x1,
  1423. (reg_val >> 10) & 0x1);
  1424. printf("lf_sub_done %1d, i_wdma_ack_wait %1d, lf_all_sub_done %1d, cur_ycbcr %1d, sub8x8_done %2d\n",
  1425. (reg_val >> 9) & 0x1,
  1426. (reg_val >> 8) & 0x1,
  1427. (reg_val >> 6) & 0x1,
  1428. (reg_val >> 4) & 0x1,
  1429. reg_val & 0xf);
  1430. printf("[-] VCE REG Dump\n");
  1431. printf("[-] VCE REG Dump\n");
  1432. printf("-------------------------------------------------------------------------------\n");
  1433. }
  1434. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1435. }
  1436. else {
  1437. VLOG(ERR, "Unknown product id : %08x\n", product_code);
  1438. }
  1439. }
  1440. void vdi_make_log(unsigned long core_idx, const char *str, int step)
  1441. {
  1442. int val;
  1443. val = VpuReadReg(core_idx, W4_INST_INDEX);
  1444. val &= 0xffff;
  1445. if (step == 1)
  1446. VLOG(INFO, "\n**%s start(%d)\n", str, val);
  1447. else if (step == 2) //
  1448. VLOG(INFO, "\n**%s timeout(%d)\n", str, val);
  1449. else
  1450. VLOG(INFO, "\n**%s end(%d)\n", str, val);
  1451. }
  1452. void vdi_log(unsigned long core_idx, int cmd, int step)
  1453. {
  1454. vdi_info_t *vdi;
  1455. int i;
  1456. // BIT_RUN command
  1457. enum {
  1458. SEQ_INIT = 1,
  1459. SEQ_END = 2,
  1460. PIC_RUN = 3,
  1461. SET_FRAME_BUF = 4,
  1462. ENCODE_HEADER = 5,
  1463. ENC_PARA_SET = 6,
  1464. DEC_PARA_SET = 7,
  1465. DEC_BUF_FLUSH = 8,
  1466. RC_CHANGE_PARAMETER = 9,
  1467. VPU_SLEEP = 10,
  1468. VPU_WAKE = 11,
  1469. ENC_ROI_INIT = 12,
  1470. FIRMWARE_GET = 0xf,
  1471. VPU_RESET = 0x10,
  1472. };
  1473. if (core_idx >= MAX_NUM_VPU_CORE)
  1474. return ;
  1475. vdi = &s_vdi_info[core_idx];
  1476. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0)
  1477. return ;
  1478. if (PRODUCT_CODE_W_SERIES(vdi->product_code))
  1479. {
  1480. switch(cmd)
  1481. {
  1482. case INIT_VPU:
  1483. vdi_make_log(core_idx, "INIT_VPU", step);
  1484. break;
  1485. case DEC_PIC_HDR: //SET_PARAM for ENC
  1486. vdi_make_log(core_idx, "SET_PARAM(ENC), DEC_PIC_HDR(DEC)", step);
  1487. break;
  1488. case FINI_SEQ:
  1489. vdi_make_log(core_idx, "FINI_SEQ", step);
  1490. break;
  1491. case DEC_PIC://ENC_PIC for ENC
  1492. vdi_make_log(core_idx, "DEC_PIC, ENC_PIC", step);
  1493. break;
  1494. case SET_FRAMEBUF:
  1495. vdi_make_log(core_idx, "SET_FRAMEBUF", step);
  1496. break;
  1497. case FLUSH_DECODER:
  1498. vdi_make_log(core_idx, "FLUSH_DECODER", step);
  1499. break;
  1500. case GET_FW_VERSION:
  1501. vdi_make_log(core_idx, "GET_FW_VERSION", step);
  1502. break;
  1503. case QUERY_DECODER:
  1504. vdi_make_log(core_idx, "QUERY_DECODER", step);
  1505. break;
  1506. case SLEEP_VPU:
  1507. vdi_make_log(core_idx, "SLEEP_VPU", step);
  1508. break;
  1509. case CREATE_INSTANCE:
  1510. vdi_make_log(core_idx, "CREATE_INSTANCE", step);
  1511. break;
  1512. case RESET_VPU:
  1513. vdi_make_log(core_idx, "RESET_VPU", step);
  1514. break;
  1515. default:
  1516. vdi_make_log(core_idx, "ANY_CMD", step);
  1517. break;
  1518. }
  1519. }
  1520. else if (PRODUCT_CODE_NOT_W_SERIES(vdi->product_code))
  1521. {
  1522. switch(cmd)
  1523. {
  1524. case SEQ_INIT:
  1525. vdi_make_log(core_idx, "SEQ_INIT", step);
  1526. break;
  1527. case SEQ_END:
  1528. vdi_make_log(core_idx, "SEQ_END", step);
  1529. break;
  1530. case PIC_RUN:
  1531. vdi_make_log(core_idx, "PIC_RUN", step);
  1532. break;
  1533. case SET_FRAME_BUF:
  1534. vdi_make_log(core_idx, "SET_FRAME_BUF", step);
  1535. break;
  1536. case ENCODE_HEADER:
  1537. vdi_make_log(core_idx, "ENCODE_HEADER", step);
  1538. break;
  1539. case RC_CHANGE_PARAMETER:
  1540. vdi_make_log(core_idx, "RC_CHANGE_PARAMETER", step);
  1541. break;
  1542. case DEC_BUF_FLUSH:
  1543. vdi_make_log(core_idx, "DEC_BUF_FLUSH", step);
  1544. break;
  1545. case FIRMWARE_GET:
  1546. vdi_make_log(core_idx, "FIRMWARE_GET", step);
  1547. break;
  1548. case VPU_RESET:
  1549. vdi_make_log(core_idx, "VPU_RESET", step);
  1550. break;
  1551. case ENC_PARA_SET:
  1552. vdi_make_log(core_idx, "ENC_PARA_SET", step);
  1553. break;
  1554. case DEC_PARA_SET:
  1555. vdi_make_log(core_idx, "DEC_PARA_SET", step);
  1556. break;
  1557. default:
  1558. vdi_make_log(core_idx, "ANY_CMD", step);
  1559. break;
  1560. }
  1561. }
  1562. else {
  1563. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1564. return;
  1565. }
  1566. for (i=0; i<0x200; i=i+16)
  1567. {
  1568. VLOG(INFO, "0x%04xh: 0x%08x 0x%08x 0x%08x 0x%08x\n", i,
  1569. vdi_read_register(core_idx, i), vdi_read_register(core_idx, i+4),
  1570. vdi_read_register(core_idx, i+8), vdi_read_register(core_idx, i+0xc));
  1571. }
  1572. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) // WAVE4xx
  1573. {
  1574. if (cmd == INIT_VPU || cmd == VPU_RESET || cmd == CREATE_INSTANCE)
  1575. {
  1576. vdi_print_vpu_status(core_idx);
  1577. }
  1578. }
  1579. else if (PRODUCT_CODE_NOT_W_SERIES(vdi->product_code))
  1580. {
  1581. //if ((cmd == PIC_RUN && step== 0) || cmd == VPU_RESET)
  1582. if (cmd == VPU_RESET)
  1583. {
  1584. printf_gdi_info(core_idx, 32, 0);
  1585. #define VDI_LOG_MBC_BUSY 0x0440
  1586. #define VDI_LOG_MC_BASE 0x0C00
  1587. #define VDI_LOG_MC_BUSY 0x0C04
  1588. #define VDI_LOG_GDI_BUS_STATUS (0x10F4)
  1589. #define VDI_LOG_ROT_SRC_IDX (0x400 + 0x10C)
  1590. #define VDI_LOG_ROT_DST_IDX (0x400 + 0x110)
  1591. VLOG(INFO, "MBC_BUSY = %x\n", vdi_read_register(core_idx, VDI_LOG_MBC_BUSY));
  1592. VLOG(INFO, "MC_BUSY = %x\n", vdi_read_register(core_idx, VDI_LOG_MC_BUSY));
  1593. VLOG(INFO, "MC_MB_XY_DONE=(y:%d, x:%d)\n", (vdi_read_register(core_idx, VDI_LOG_MC_BASE) >> 20) & 0x3F, (vdi_read_register(core_idx, VDI_LOG_MC_BASE) >> 26) & 0x3F);
  1594. VLOG(INFO, "GDI_BUS_STATUS = %x\n", vdi_read_register(core_idx, VDI_LOG_GDI_BUS_STATUS));
  1595. VLOG(INFO, "ROT_SRC_IDX = %x\n", vdi_read_register(core_idx, VDI_LOG_ROT_SRC_IDX));
  1596. VLOG(INFO, "ROT_DST_IDX = %x\n", vdi_read_register(core_idx, VDI_LOG_ROT_DST_IDX));
  1597. VLOG(INFO, "P_MC_PIC_INDEX_0 = %x\n", vdi_read_register(core_idx, MC_BASE+0x200));
  1598. VLOG(INFO, "P_MC_PIC_INDEX_1 = %x\n", vdi_read_register(core_idx, MC_BASE+0x20c));
  1599. VLOG(INFO, "P_MC_PIC_INDEX_2 = %x\n", vdi_read_register(core_idx, MC_BASE+0x218));
  1600. VLOG(INFO, "P_MC_PIC_INDEX_3 = %x\n", vdi_read_register(core_idx, MC_BASE+0x230));
  1601. VLOG(INFO, "P_MC_PIC_INDEX_3 = %x\n", vdi_read_register(core_idx, MC_BASE+0x23C));
  1602. VLOG(INFO, "P_MC_PIC_INDEX_4 = %x\n", vdi_read_register(core_idx, MC_BASE+0x248));
  1603. VLOG(INFO, "P_MC_PIC_INDEX_5 = %x\n", vdi_read_register(core_idx, MC_BASE+0x254));
  1604. VLOG(INFO, "P_MC_PIC_INDEX_6 = %x\n", vdi_read_register(core_idx, MC_BASE+0x260));
  1605. VLOG(INFO, "P_MC_PIC_INDEX_7 = %x\n", vdi_read_register(core_idx, MC_BASE+0x26C));
  1606. VLOG(INFO, "P_MC_PIC_INDEX_8 = %x\n", vdi_read_register(core_idx, MC_BASE+0x278));
  1607. VLOG(INFO, "P_MC_PIC_INDEX_9 = %x\n", vdi_read_register(core_idx, MC_BASE+0x284));
  1608. VLOG(INFO, "P_MC_PIC_INDEX_a = %x\n", vdi_read_register(core_idx, MC_BASE+0x290));
  1609. VLOG(INFO, "P_MC_PIC_INDEX_b = %x\n", vdi_read_register(core_idx, MC_BASE+0x29C));
  1610. VLOG(INFO, "P_MC_PIC_INDEX_c = %x\n", vdi_read_register(core_idx, MC_BASE+0x2A8));
  1611. VLOG(INFO, "P_MC_PIC_INDEX_d = %x\n", vdi_read_register(core_idx, MC_BASE+0x2B4));
  1612. VLOG(INFO, "P_MC_PICIDX_0 = %x\n", vdi_read_register(core_idx, MC_BASE+0x028));
  1613. VLOG(INFO, "P_MC_PICIDX_1 = %x\n", vdi_read_register(core_idx, MC_BASE+0x02C));
  1614. }
  1615. }
  1616. else {
  1617. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1618. return;
  1619. }
  1620. }
  1621. static void byte_swap(unsigned char* data, int len)
  1622. {
  1623. Uint8 temp;
  1624. Int32 i;
  1625. for (i=0; i<len; i+=2) {
  1626. temp = data[i];
  1627. data[i] = data[i+1];
  1628. data[i+1] = temp;
  1629. }
  1630. }
  1631. static void word_swap(unsigned char* data, int len)
  1632. {
  1633. Uint16 temp;
  1634. Uint16* ptr = (Uint16*)data;
  1635. Int32 i, size = len/sizeof(Uint16);
  1636. for (i=0; i<size; i+=2) {
  1637. temp = ptr[i];
  1638. ptr[i] = ptr[i+1];
  1639. ptr[i+1] = temp;
  1640. }
  1641. }
  1642. static void dword_swap(unsigned char* data, int len)
  1643. {
  1644. Uint32 temp;
  1645. Uint32* ptr = (Uint32*)data;
  1646. Int32 i, size = len/sizeof(Uint32);
  1647. for (i=0; i<size; i+=2) {
  1648. temp = ptr[i];
  1649. ptr[i] = ptr[i+1];
  1650. ptr[i+1] = temp;
  1651. }
  1652. }
  1653. static void lword_swap(unsigned char* data, int len)
  1654. {
  1655. Uint64 temp;
  1656. Uint64* ptr = (Uint64*)data;
  1657. Int32 i, size = len/sizeof(Uint64);
  1658. for (i=0; i<size; i+=2) {
  1659. temp = ptr[i];
  1660. ptr[i] = ptr[i+1];
  1661. ptr[i+1] = temp;
  1662. }
  1663. }
  1664. int vdi_get_system_endian(unsigned long core_idx)
  1665. {
  1666. vdi_info_t *vdi;
  1667. if (core_idx >= MAX_NUM_VPU_CORE)
  1668. return -1;
  1669. vdi = &s_vdi_info[core_idx];
  1670. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  1671. return -1;
  1672. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  1673. return VDI_128BIT_BUS_SYSTEM_ENDIAN;
  1674. }
  1675. else if(PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  1676. return VDI_SYSTEM_ENDIAN;
  1677. }
  1678. else {
  1679. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1680. return -1;
  1681. }
  1682. }
  1683. int vdi_convert_endian(unsigned long core_idx, unsigned int endian)
  1684. {
  1685. vdi_info_t *vdi;
  1686. if (core_idx >= MAX_NUM_VPU_CORE)
  1687. return -1;
  1688. vdi = &s_vdi_info[core_idx];
  1689. if(!vdi || !vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  1690. return -1;
  1691. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  1692. switch (endian) {
  1693. case VDI_LITTLE_ENDIAN: endian = 0x00; break;
  1694. case VDI_BIG_ENDIAN: endian = 0x0f; break;
  1695. case VDI_32BIT_LITTLE_ENDIAN: endian = 0x04; break;
  1696. case VDI_32BIT_BIG_ENDIAN: endian = 0x03; break;
  1697. }
  1698. }
  1699. else if(PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  1700. }
  1701. else {
  1702. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1703. return -1;
  1704. }
  1705. return (endian&0x0f);
  1706. }
  1707. static Uint32 convert_endian_coda9_to_wave4(Uint32 endian)
  1708. {
  1709. Uint32 converted_endian = endian;
  1710. switch(endian) {
  1711. case VDI_LITTLE_ENDIAN: converted_endian = 0; break;
  1712. case VDI_BIG_ENDIAN: converted_endian = 7; break;
  1713. case VDI_32BIT_LITTLE_ENDIAN: converted_endian = 4; break;
  1714. case VDI_32BIT_BIG_ENDIAN: converted_endian = 3; break;
  1715. }
  1716. return converted_endian;
  1717. }
  1718. int swap_endian(unsigned long core_idx, unsigned char *data, int len, int endian)
  1719. {
  1720. vdi_info_t *vdi;
  1721. int changes;
  1722. int sys_endian;
  1723. BOOL byteChange, wordChange, dwordChange, lwordChange;
  1724. if (core_idx >= MAX_NUM_VPU_CORE)
  1725. return -1;
  1726. vdi = &s_vdi_info[core_idx];
  1727. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  1728. return -1;
  1729. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  1730. sys_endian = VDI_128BIT_BUS_SYSTEM_ENDIAN;
  1731. }
  1732. else if(PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  1733. sys_endian = VDI_SYSTEM_ENDIAN;
  1734. }
  1735. else {
  1736. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1737. return -1;
  1738. }
  1739. endian = vdi_convert_endian(core_idx, endian);
  1740. sys_endian = vdi_convert_endian(core_idx, sys_endian);
  1741. if (endian == sys_endian)
  1742. return 0;
  1743. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  1744. }
  1745. else if (PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  1746. endian = convert_endian_coda9_to_wave4(endian);
  1747. sys_endian = convert_endian_coda9_to_wave4(sys_endian);
  1748. }
  1749. else {
  1750. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  1751. return -1;
  1752. }
  1753. changes = endian ^ sys_endian;
  1754. byteChange = changes&0x01;
  1755. wordChange = ((changes&0x02) == 0x02);
  1756. dwordChange = ((changes&0x04) == 0x04);
  1757. lwordChange = ((changes&0x08) == 0x08);
  1758. if (byteChange) byte_swap(data, len);
  1759. if (wordChange) word_swap(data, len);
  1760. if (dwordChange) dword_swap(data, len);
  1761. if (lwordChange) lword_swap(data, len);
  1762. return 1;
  1763. }
  1764. #endif //#if defined(linux) || defined(__linux) || defined(ANDROID)