venc.c 57 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044
  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. //--=========================================================================--
  3. // This file is linux device driver for VPU.
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2015 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================-
  17. #include <linux/kernel.h>
  18. #include <linux/mm.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ioport.h>
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/wait.h>
  25. #include <linux/list.h>
  26. #include <linux/clk.h>
  27. #include <linux/delay.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/cdev.h>
  30. #include <linux/slab.h>
  31. #include <linux/sched.h>
  32. #include <linux/reset.h>
  33. #include <linux/version.h>
  34. #include <linux/of.h>
  35. #include <linux/pm_runtime.h>
  36. #include <soc/sifive/sifive_l2_cache.h>
  37. #include "../../../vpuapi/vpuconfig.h"
  38. #include "vpu.h"
  39. #ifndef CONFIG_PM
  40. #define CONFIG_PM
  41. #endif
  42. //#define ENABLE_DEBUG_MSG
  43. #ifdef ENABLE_DEBUG_MSG
  44. #define DPRINTK(args...) printk(KERN_INFO args);
  45. #else
  46. #define DPRINTK(args...)
  47. #endif
  48. /* definitions to be changed as customer configuration */
  49. /* if you want to have clock gating scheme frame by frame */
  50. #define VPU_SUPPORT_CLOCK_CONTROL
  51. /* if clktree is work,try this...*/
  52. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  53. /* if the driver want to use interrupt service from kernel ISR */
  54. #define VPU_SUPPORT_ISR
  55. /* if the platform driver knows the name of this driver */
  56. /* VPU_PLATFORM_DEVICE_NAME */
  57. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  58. /* if this driver knows the dedicated video memory address */
  59. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  60. static void starfive_flush_dcache(unsigned long start, unsigned long len)
  61. {
  62. sifive_l2_flush64_range(start, len);
  63. }
  64. #define VPU_PLATFORM_DEVICE_NAME "venc"
  65. #define VPU_CLK_NAME "vcoenc"
  66. #define VPU_DEV_NAME "venc"
  67. /* if the platform driver knows this driver */
  68. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  69. //#define VPU_REG_BASE_ADDR 0x75000000
  70. #define VPU_REG_BASE_ADDR 0x130B0000
  71. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  72. #ifdef VPU_SUPPORT_ISR
  73. #define VPU_IRQ_NUM (15)
  74. #endif
  75. /* this definition is only for chipsnmedia FPGA board env */
  76. /* so for SOC env of customers can be ignored */
  77. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  78. # define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  79. #endif
  80. #ifdef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  81. typedef struct vpu_clkgen_t {
  82. void __iomem *en_ctrl;
  83. uint32_t rst_mask;
  84. } vpu_clkgen_t;
  85. struct clk_bulk_data vpu_clks[] = {
  86. { .id = "apb_clk" },
  87. { .id = "axi_clk" },
  88. { .id = "bpu_clk" },
  89. { .id = "vce_clk" },
  90. { .id = "noc_bus" },
  91. };
  92. #define FRAMSIZE_1080P (1920*1080)
  93. #define FRAMSIZE_720P (1280*720)
  94. #define FRAMSIZE_480P (720*480)
  95. struct vpu_devfreq_t {
  96. struct clk *axi_clk;
  97. struct clk *bpu_clk;
  98. struct clk *vce_clk;
  99. };
  100. enum VPU_DEV_FREQ {
  101. VPU_DEV_FREQ_80 = 80000000,
  102. VPU_DEV_FREQ_100 = 100000000,
  103. VPU_DEV_FREQ_150 = 150000000,
  104. VPU_DEV_FREQ_200 = 200000000,
  105. VPU_DEV_FREQ_237 = 237600000,
  106. VPU_DEV_FREQ_300 = 300000000,
  107. VPU_DEV_FREQ_MAX = VPU_DEV_FREQ_300,
  108. };
  109. enum VPU_DEV_FREQ_MODE {
  110. MODE_480P_30F,
  111. MODE_480P_60F,
  112. MODE_720P_30F,
  113. MODE_720P_60F,
  114. MODE_1080P_30F,
  115. MODE_MAX,
  116. };
  117. struct vpu_dev_freq_list {
  118. int mode;
  119. unsigned long axi_rate;
  120. unsigned long bpu_rate;
  121. unsigned long vce_rate;
  122. };
  123. typedef struct vpu_clk_t{
  124. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  125. void __iomem *clkgen;
  126. void __iomem *rst_ctrl;
  127. void __iomem *rst_status;
  128. void __iomem *noc_bus;
  129. uint32_t en_shift;
  130. uint32_t en_mask;
  131. vpu_clkgen_t apb_clk;
  132. vpu_clkgen_t axi_clk;
  133. vpu_clkgen_t bpu_clk;
  134. vpu_clkgen_t vce_clk;
  135. vpu_clkgen_t aximem_128b;
  136. #else
  137. struct clk_bulk_data *clks;
  138. struct reset_control *resets;
  139. struct vpu_devfreq_t vpu_devfreq;
  140. int nr_clks;
  141. #endif
  142. struct device *dev;
  143. bool noc_ctrl;
  144. }vpu_clk_t;
  145. #endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  146. struct device *vpu_dev;
  147. typedef struct vpu_drv_context_t {
  148. struct fasync_struct *async_queue;
  149. unsigned long interrupt_reason;
  150. u32 open_count; /*!<< device reference count. Not instance count */
  151. } vpu_drv_context_t;
  152. /* To track the allocated memory buffer */
  153. typedef struct vpudrv_buffer_pool_t {
  154. struct list_head list;
  155. struct vpudrv_buffer_t vb;
  156. struct file *filp;
  157. } vpudrv_buffer_pool_t;
  158. /* To track the instance index and buffer in instance pool */
  159. typedef struct vpudrv_instanace_list_t {
  160. struct list_head list;
  161. unsigned long inst_idx;
  162. unsigned long core_idx;
  163. struct file *filp;
  164. } vpudrv_instanace_list_t;
  165. typedef struct vpudrv_instance_pool_t {
  166. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  167. } vpudrv_instance_pool_t;
  168. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  169. # define VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE (62*1024*1024)
  170. # define VPU_DRAM_PHYSICAL_BASE 0x86C00000
  171. #include "vmm.h"
  172. static video_mm_t s_vmem;
  173. static vpudrv_buffer_t s_video_memory = {0};
  174. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  175. static int vpu_hw_reset(void);
  176. static void vpu_clk_disable(vpu_clk_t *clk);
  177. static int vpu_clk_enable(vpu_clk_t *clk);
  178. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  179. static void vpu_clk_put(vpu_clk_t *clk);
  180. static int vpu_pmu_enable(struct device *dev);
  181. static void vpu_pmu_disable(struct device *dev);
  182. static int vpu_devfreq_select(struct vpudrv_devfreq_info_t *info);
  183. /* end customer definition */
  184. static vpudrv_buffer_t s_instance_pool = {0};
  185. static vpudrv_buffer_t s_common_memory = {0};
  186. static vpu_drv_context_t s_vpu_drv_context;
  187. static dev_t s_vpu_devt;
  188. static int s_vpu_major;
  189. static struct cdev s_vpu_cdev;
  190. static struct class *s_vpu_class;
  191. static struct vpu_clk_t *s_vpu_clk;
  192. static int s_vpu_open_ref_count;
  193. #ifdef VPU_SUPPORT_ISR
  194. static int s_vpu_irq = VPU_IRQ_NUM;
  195. #endif
  196. static vpudrv_buffer_t s_vpu_register = {0};
  197. static int s_interrupt_flag;
  198. static wait_queue_head_t s_interrupt_wait_q;
  199. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  200. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  201. static DECLARE_MUTEX(s_vpu_sem);
  202. #else
  203. static DEFINE_SEMAPHORE(s_vpu_sem);
  204. #endif
  205. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  206. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  207. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  208. #ifdef CONFIG_PM
  209. /* implement to power management functions */
  210. #define BIT_BASE 0x0000
  211. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  212. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  213. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  214. #define BIT_INT_STS (BIT_BASE + 0x010)
  215. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  216. #define BIT_INT_REASON (BIT_BASE + 0x174)
  217. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  218. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  219. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  220. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  221. /* WAVE4 registers */
  222. #define W4_REG_BASE 0x0000
  223. #define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070)
  224. #define W4_VPU_INT_REASON_CLEAR (W4_REG_BASE + 0x0034)
  225. #define W4_VPU_VINT_CLEAR (W4_REG_BASE + 0x003C)
  226. #define W4_VPU_VPU_INT_STS (W4_REG_BASE + 0x0044)
  227. #define W4_VPU_INT_REASON (W4_REG_BASE + 0x004c)
  228. #define W4_RET_SUCCESS (W4_REG_BASE + 0x0110)
  229. #define W4_RET_FAIL_REASON (W4_REG_BASE + 0x0114)
  230. /* WAVE4 INIT, WAKEUP */
  231. #define W4_PO_CONF (W4_REG_BASE + 0x0000)
  232. #define W4_VCPU_CUR_PC (W4_REG_BASE + 0x0004)
  233. #define W4_VPU_VINT_ENABLE (W4_REG_BASE + 0x0048)
  234. #define W4_VPU_RESET_REQ (W4_REG_BASE + 0x0050)
  235. #define W4_VPU_RESET_STATUS (W4_REG_BASE + 0x0054)
  236. #define W4_VPU_REMAP_CTRL (W4_REG_BASE + 0x0060)
  237. #define W4_VPU_REMAP_VADDR (W4_REG_BASE + 0x0064)
  238. #define W4_VPU_REMAP_PADDR (W4_REG_BASE + 0x0068)
  239. #define W4_VPU_REMAP_CORE_START (W4_REG_BASE + 0x006C)
  240. #define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070)
  241. #define W4_REMAP_CODE_INDEX 0
  242. enum {
  243. W4_INT_INIT_VPU = 0,
  244. W4_INT_DEC_PIC_HDR = 1,
  245. W4_INT_FINI_SEQ = 2,
  246. W4_INT_DEC_PIC = 3,
  247. W4_INT_SET_FRAMEBUF = 4,
  248. W4_INT_FLUSH_DEC = 5,
  249. W4_INT_GET_FW_VERSION = 9,
  250. W4_INT_QUERY_DEC = 10,
  251. W4_INT_SLEEP_VPU = 11,
  252. W4_INT_WAKEUP_VPU = 12,
  253. W4_INT_CHANGE_INT = 13,
  254. W4_INT_CREATE_INSTANCE = 14,
  255. W4_INT_BSBUF_EMPTY = 15, /*!<< Bitstream buffer empty */
  256. W4_INT_ENC_SLICE_INT = 15,
  257. };
  258. enum {
  259. W5_INT_INIT_VPU = 0,
  260. W5_INT_WAKEUP_VPU = 1,
  261. W5_INT_SLEEP_VPU = 2,
  262. W5_INT_CREATE_INSTANCE = 3,
  263. W5_INT_FLUSH_INSTANCE = 4,
  264. W5_INT_DESTORY_INSTANCE = 5,
  265. W5_INT_INIT_SEQ = 6,
  266. W5_INT_SET_FRAMEBUF = 7,
  267. W5_INT_DEC_PIC = 8,
  268. W5_INT_ENC_PIC = 8,
  269. W5_INT_ENC_SET_PARAM = 9,
  270. W5_INT_DEC_QUERY = 14,
  271. W5_INT_BSBUF_EMPTY = 15,
  272. };
  273. #define W4_HW_OPTION (W4_REG_BASE + 0x0124)
  274. #define W4_CODE_SIZE (W4_REG_BASE + 0x011C)
  275. /* Note: W4_INIT_CODE_BASE_ADDR should be aligned to 4KB */
  276. #define W4_ADDR_CODE_BASE (W4_REG_BASE + 0x0118)
  277. #define W4_CODE_PARAM (W4_REG_BASE + 0x0120)
  278. #define W4_INIT_VPU_TIME_OUT_CNT (W4_REG_BASE + 0x0134)
  279. /* WAVE5 registers */
  280. #define W5_ADDR_CODE_BASE (W4_REG_BASE + 0x0110)
  281. #define W5_CODE_SIZE (W4_REG_BASE + 0x0114)
  282. #define W5_CODE_PARAM (W4_REG_BASE + 0x0128)
  283. #define W5_INIT_VPU_TIME_OUT_CNT (W4_REG_BASE + 0x0130)
  284. #define W5_HW_OPTION (W4_REG_BASE + 0x012C)
  285. #define W5_RET_SUCCESS (W4_REG_BASE + 0x0108)
  286. /* WAVE4 Wave4BitIssueCommand */
  287. #define W4_CORE_INDEX (W4_REG_BASE + 0x0104)
  288. #define W4_INST_INDEX (W4_REG_BASE + 0x0108)
  289. #define W4_COMMAND (W4_REG_BASE + 0x0100)
  290. #define W4_VPU_HOST_INT_REQ (W4_REG_BASE + 0x0038)
  291. /* Product register */
  292. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  293. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  294. #endif
  295. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  296. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  297. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  298. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  299. {
  300. if (!vb)
  301. return -1;
  302. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  303. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  304. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  305. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  306. return -1;
  307. }
  308. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  309. #else
  310. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  311. if ((void *)(vb->base) == NULL) {
  312. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  313. return -1;
  314. }
  315. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  316. #endif
  317. return 0;
  318. }
  319. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  320. {
  321. if (!vb)
  322. return;
  323. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  324. if (vb->base)
  325. vmem_free(&s_vmem, vb->phys_addr, 0);
  326. #else
  327. if (vb->base)
  328. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  329. #endif
  330. }
  331. static int vpu_free_instances(struct file *filp)
  332. {
  333. vpudrv_instanace_list_t *vil, *n;
  334. vpudrv_instance_pool_t *vip;
  335. void *vip_base;
  336. int instance_pool_size_per_core;
  337. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  338. void *vdi_mutexes_base;
  339. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  340. #endif
  341. DPRINTK("[VPUDRV] vpu_free_instances\n");
  342. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  343. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  344. {
  345. if (vil->filp == filp) {
  346. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  347. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  348. vip = (vpudrv_instance_pool_t *)vip_base;
  349. if (vip) {
  350. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  351. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  352. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  353. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  354. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  355. if (vdi_mutexes_base) {
  356. int i;
  357. for (i = 0; i < 4; i++) {
  358. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  359. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  360. }
  361. }
  362. #endif
  363. }
  364. s_vpu_open_ref_count--;
  365. list_del(&vil->list);
  366. kfree(vil);
  367. }
  368. }
  369. return 1;
  370. }
  371. static int vpu_free_buffers(struct file *filp)
  372. {
  373. vpudrv_buffer_pool_t *pool, *n;
  374. vpudrv_buffer_t vb;
  375. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  376. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  377. {
  378. if (pool->filp == filp) {
  379. vb = pool->vb;
  380. if (vb.base) {
  381. vpu_free_dma_buffer(&vb);
  382. list_del(&pool->list);
  383. kfree(pool);
  384. }
  385. }
  386. }
  387. return 0;
  388. }
  389. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  390. {
  391. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  392. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  393. int core;
  394. int product_code;
  395. DPRINTK("[VPUDRV][+]%s\n", __func__);
  396. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  397. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  398. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  399. continue;
  400. }
  401. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  402. if (PRODUCT_CODE_W_SERIES(product_code)) {
  403. if (ReadVpuRegister(W4_VPU_VPU_INT_STS)) {
  404. dev->interrupt_reason = ReadVpuRegister(W4_VPU_INT_REASON);
  405. WriteVpuRegister(W4_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  406. WriteVpuRegister(W4_VPU_VINT_CLEAR, 0x1);
  407. }
  408. }
  409. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  410. if (ReadVpuRegister(BIT_INT_STS)) {
  411. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  412. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  413. }
  414. }
  415. else {
  416. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  417. continue;
  418. }
  419. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08lx\n", product_code, dev->interrupt_reason);
  420. }
  421. if (dev->async_queue)
  422. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  423. s_interrupt_flag = 1;
  424. wake_up_interruptible(&s_interrupt_wait_q);
  425. DPRINTK("[VPUDRV][-]%s\n", __func__);
  426. return IRQ_HANDLED;
  427. }
  428. static int vpu_open(struct inode *inode, struct file *filp)
  429. {
  430. DPRINTK("[VPUDRV][+] %s\n", __func__);
  431. pm_runtime_get_sync(s_vpu_clk->dev);
  432. vpu_hw_reset();
  433. spin_lock(&s_vpu_lock);
  434. s_vpu_drv_context.open_count++;
  435. filp->private_data = (void *)(&s_vpu_drv_context);
  436. spin_unlock(&s_vpu_lock);
  437. DPRINTK("[VPUDRV][-] %s\n", __func__);
  438. return 0;
  439. }
  440. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  441. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  442. {
  443. int ret = 0;
  444. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  445. switch (cmd) {
  446. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  447. {
  448. vpudrv_buffer_pool_t *vbp;
  449. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  450. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  451. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  452. if (!vbp) {
  453. up(&s_vpu_sem);
  454. return -ENOMEM;
  455. }
  456. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  457. if (ret) {
  458. kfree(vbp);
  459. up(&s_vpu_sem);
  460. return -EFAULT;
  461. }
  462. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  463. if (ret == -1) {
  464. ret = -ENOMEM;
  465. kfree(vbp);
  466. up(&s_vpu_sem);
  467. break;
  468. }
  469. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  470. if (ret) {
  471. kfree(vbp);
  472. ret = -EFAULT;
  473. up(&s_vpu_sem);
  474. break;
  475. }
  476. vbp->filp = filp;
  477. spin_lock(&s_vpu_lock);
  478. list_add(&vbp->list, &s_vbp_head);
  479. spin_unlock(&s_vpu_lock);
  480. up(&s_vpu_sem);
  481. }
  482. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  483. }
  484. break;
  485. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  486. {
  487. vpudrv_buffer_pool_t *vbp, *n;
  488. vpudrv_buffer_t vb;
  489. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  490. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  491. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  492. if (ret) {
  493. up(&s_vpu_sem);
  494. return -EACCES;
  495. }
  496. if (vb.base)
  497. vpu_free_dma_buffer(&vb);
  498. spin_lock(&s_vpu_lock);
  499. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  500. {
  501. if (vbp->vb.base == vb.base) {
  502. list_del(&vbp->list);
  503. kfree(vbp);
  504. break;
  505. }
  506. }
  507. spin_unlock(&s_vpu_lock);
  508. up(&s_vpu_sem);
  509. }
  510. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  511. }
  512. break;
  513. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  514. {
  515. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  516. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  517. if (s_video_memory.base != 0) {
  518. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  519. if (ret != 0)
  520. ret = -EFAULT;
  521. } else {
  522. ret = -EFAULT;
  523. }
  524. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  525. #endif
  526. }
  527. break;
  528. case VDI_IOCTL_WAIT_INTERRUPT:
  529. {
  530. vpudrv_intr_info_t info;
  531. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  532. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  533. if (ret != 0)
  534. return -EFAULT;
  535. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  536. if (!ret) {
  537. ret = -ETIME;
  538. break;
  539. }
  540. if (signal_pending(current)) {
  541. ret = -ERESTARTSYS;
  542. break;
  543. }
  544. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  545. info.intr_reason = dev->interrupt_reason;
  546. s_interrupt_flag = 0;
  547. dev->interrupt_reason = 0;
  548. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  549. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  550. if (ret != 0)
  551. return -EFAULT;
  552. }
  553. break;
  554. case VDI_IOCTL_SET_CLOCK_GATE:
  555. {
  556. u32 clkgate;
  557. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  558. if (get_user(clkgate, (u32 __user *) arg))
  559. return -EFAULT;
  560. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  561. if (clkgate)
  562. vpu_clk_enable(s_vpu_clk);
  563. else
  564. vpu_clk_disable(s_vpu_clk);
  565. #endif
  566. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  567. }
  568. break;
  569. case VDI_IOCTL_GET_INSTANCE_POOL:
  570. {
  571. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  572. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  573. if (s_instance_pool.base != 0) {
  574. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  575. if (ret != 0)
  576. ret = -EFAULT;
  577. } else {
  578. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  579. if (ret == 0) {
  580. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  581. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  582. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  583. s_instance_pool.phys_addr = s_instance_pool.base;
  584. if (s_instance_pool.base != 0)
  585. #else
  586. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  587. #endif
  588. {
  589. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  590. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  591. if (ret == 0) {
  592. /* success to get memory for instance pool */
  593. up(&s_vpu_sem);
  594. break;
  595. }
  596. }
  597. }
  598. ret = -EFAULT;
  599. }
  600. up(&s_vpu_sem);
  601. }
  602. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  603. }
  604. break;
  605. case VDI_IOCTL_GET_COMMON_MEMORY:
  606. {
  607. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  608. if (s_common_memory.base != 0) {
  609. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  610. if (ret != 0)
  611. ret = -EFAULT;
  612. } else {
  613. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  614. if (ret == 0) {
  615. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  616. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  617. if (ret == 0) {
  618. /* success to get memory for common memory */
  619. break;
  620. }
  621. }
  622. }
  623. ret = -EFAULT;
  624. }
  625. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  626. }
  627. break;
  628. case VDI_IOCTL_OPEN_INSTANCE:
  629. {
  630. vpudrv_inst_info_t inst_info;
  631. vpudrv_instanace_list_t *vil, *n;
  632. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  633. if (!vil)
  634. return -ENOMEM;
  635. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  636. return -EFAULT;
  637. vil->inst_idx = inst_info.inst_idx;
  638. vil->core_idx = inst_info.core_idx;
  639. vil->filp = filp;
  640. spin_lock(&s_vpu_lock);
  641. list_add(&vil->list, &s_inst_list_head);
  642. inst_info.inst_open_count = 0; /* counting the current open instance number */
  643. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  644. {
  645. if (vil->core_idx == inst_info.core_idx)
  646. inst_info.inst_open_count++;
  647. }
  648. spin_unlock(&s_vpu_lock);
  649. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  650. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  651. kfree(vil);
  652. return -EFAULT;
  653. }
  654. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  655. }
  656. break;
  657. case VDI_IOCTL_CLOSE_INSTANCE:
  658. {
  659. vpudrv_inst_info_t inst_info;
  660. vpudrv_instanace_list_t *vil, *n;
  661. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  662. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  663. return -EFAULT;
  664. spin_lock(&s_vpu_lock);
  665. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  666. {
  667. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  668. list_del(&vil->list);
  669. kfree(vil);
  670. break;
  671. }
  672. }
  673. inst_info.inst_open_count = 0; /* counting the current open instance number */
  674. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  675. {
  676. if (vil->core_idx == inst_info.core_idx)
  677. inst_info.inst_open_count++;
  678. }
  679. spin_unlock(&s_vpu_lock);
  680. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  681. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  682. return -EFAULT;
  683. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  684. }
  685. break;
  686. case VDI_IOCTL_GET_INSTANCE_NUM:
  687. {
  688. vpudrv_inst_info_t inst_info;
  689. vpudrv_instanace_list_t *vil, *n;
  690. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  691. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  692. if (ret != 0)
  693. break;
  694. inst_info.inst_open_count = 0;
  695. spin_lock(&s_vpu_lock);
  696. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  697. {
  698. if (vil->core_idx == inst_info.core_idx)
  699. inst_info.inst_open_count++;
  700. }
  701. spin_unlock(&s_vpu_lock);
  702. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  703. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  704. }
  705. break;
  706. case VDI_IOCTL_RESET:
  707. {
  708. vpu_hw_reset();
  709. }
  710. break;
  711. case VDI_IOCTL_GET_REGISTER_INFO:
  712. {
  713. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  714. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  715. if (ret != 0)
  716. ret = -EFAULT;
  717. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  718. }
  719. break;
  720. case VDI_IOCTL_FLUSH_DCACHE:
  721. {
  722. vpudrv_flush_cache_t cache_info;
  723. DPRINTK("[JPUDRV][+]VDI_IOCTL_FLUSH_DCACHE\n");
  724. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  725. if (ret != 0)
  726. ret = -EFAULT;
  727. if(cache_info.flag)
  728. starfive_flush_dcache(cache_info.start,cache_info.size);
  729. DPRINTK("[JPUDRV][-]VDI_IOCTL_FLUSH_DCACHE\n");
  730. break;
  731. }
  732. case VDI_IOCTL_DEVFREQ_SET:
  733. {
  734. vpudrv_devfreq_info_t devfreq_info;
  735. ret = copy_from_user(&devfreq_info, (vpudrv_devfreq_info_t *)arg, sizeof(vpudrv_devfreq_info_t));
  736. if (ret != 0)
  737. ret = -EFAULT;
  738. vpu_devfreq_select(&devfreq_info);
  739. break;
  740. }
  741. default:
  742. {
  743. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  744. }
  745. break;
  746. }
  747. return ret;
  748. }
  749. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  750. {
  751. return -1;
  752. }
  753. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  754. {
  755. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  756. if (!buf) {
  757. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  758. return -EFAULT;
  759. }
  760. if (len == sizeof(vpu_bit_firmware_info_t)) {
  761. vpu_bit_firmware_info_t *bit_firmware_info;
  762. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  763. if (!bit_firmware_info) {
  764. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  765. return -EFAULT;
  766. }
  767. if (copy_from_user(bit_firmware_info, buf, len)) {
  768. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  769. return -EFAULT;
  770. }
  771. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  772. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  773. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  774. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  775. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  776. return -ENODEV;
  777. }
  778. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  779. kfree(bit_firmware_info);
  780. return len;
  781. }
  782. kfree(bit_firmware_info);
  783. }
  784. return -1;
  785. }
  786. static int vpu_release(struct inode *inode, struct file *filp)
  787. {
  788. int ret = 0;
  789. DPRINTK("[VPUDRV] vpu_release\n");
  790. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  791. /* found and free the not handled buffer by user applications */
  792. vpu_free_buffers(filp);
  793. /* found and free the not closed instance by user applications */
  794. vpu_free_instances(filp);
  795. s_vpu_drv_context.open_count--;
  796. if (s_vpu_drv_context.open_count == 0) {
  797. if (s_instance_pool.base) {
  798. DPRINTK("[VPUDRV] free instance pool\n");
  799. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  800. vfree((const void *)s_instance_pool.base);
  801. #else
  802. vpu_free_dma_buffer(&s_instance_pool);
  803. #endif
  804. s_instance_pool.base = 0;
  805. }
  806. if (s_common_memory.base) {
  807. DPRINTK("[VPUDRV] free common memory\n");
  808. vpu_free_dma_buffer(&s_common_memory);
  809. s_common_memory.base = 0;
  810. }
  811. }
  812. }
  813. up(&s_vpu_sem);
  814. pm_runtime_put_sync(s_vpu_clk->dev);
  815. return 0;
  816. }
  817. static int vpu_fasync(int fd, struct file *filp, int mode)
  818. {
  819. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  820. return fasync_helper(fd, filp, mode, &dev->async_queue);
  821. }
  822. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  823. {
  824. unsigned long pfn;
  825. vm->vm_flags |= VM_IO | VM_RESERVED;
  826. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  827. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  828. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  829. }
  830. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  831. {
  832. vm->vm_flags |= VM_IO | VM_RESERVED;
  833. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  834. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  835. }
  836. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  837. {
  838. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  839. int ret;
  840. long length = vm->vm_end - vm->vm_start;
  841. unsigned long start = vm->vm_start;
  842. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  843. unsigned long pfn;
  844. vm->vm_flags |= VM_RESERVED;
  845. /* loop over all pages, map it page individually */
  846. while (length > 0)
  847. {
  848. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  849. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  850. return ret;
  851. }
  852. start += PAGE_SIZE;
  853. vmalloc_area_ptr += PAGE_SIZE;
  854. length -= PAGE_SIZE;
  855. }
  856. return 0;
  857. #else
  858. vm->vm_flags |= VM_RESERVED;
  859. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  860. #endif
  861. }
  862. /*!
  863. * @brief memory map interface for vpu file operation
  864. * @return 0 on success or negative error code on error
  865. */
  866. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  867. {
  868. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  869. if (vm->vm_pgoff == 0)
  870. return vpu_map_to_instance_pool_memory(fp, vm);
  871. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  872. return vpu_map_to_register(fp, vm);
  873. return vpu_map_to_physical_memory(fp, vm);
  874. #else
  875. if (vm->vm_pgoff) {
  876. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  877. return vpu_map_to_instance_pool_memory(fp, vm);
  878. return vpu_map_to_physical_memory(fp, vm);
  879. } else {
  880. return vpu_map_to_register(fp, vm);
  881. }
  882. #endif
  883. }
  884. struct file_operations vpu_fops = {
  885. .owner = THIS_MODULE,
  886. .open = vpu_open,
  887. .read = vpu_read,
  888. .write = vpu_write,
  889. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  890. .unlocked_ioctl = vpu_ioctl,
  891. .release = vpu_release,
  892. .fasync = vpu_fasync,
  893. .mmap = vpu_mmap,
  894. };
  895. static int vpu_probe(struct platform_device *pdev)
  896. {
  897. int err = 0;
  898. struct resource *res = NULL;
  899. struct device *devices;
  900. DPRINTK("[VPUDRV] vpu_probe\n");
  901. if(pdev){
  902. vpu_dev = &pdev->dev;
  903. vpu_dev->coherent_dma_mask = 0xffffffff;
  904. }
  905. if (pdev)
  906. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  907. if (res) {/* if platform driver is implemented */
  908. s_vpu_register.phys_addr = res->start;
  909. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  910. s_vpu_register.size = res->end - res->start;
  911. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  912. } else {
  913. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  914. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  915. s_vpu_register.size = VPU_REG_SIZE;
  916. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  917. }
  918. /* get the major number of the character device */
  919. if ((alloc_chrdev_region(&s_vpu_devt, 0, 1, VPU_DEV_NAME)) < 0) {
  920. err = -EBUSY;
  921. printk(KERN_ERR "could not allocate major number\n");
  922. goto ERROR_PROVE_DEVICE;
  923. }
  924. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  925. s_vpu_major = MAJOR(s_vpu_devt);
  926. /* initialize the device structure and register the device with the kernel */
  927. cdev_init(&s_vpu_cdev, &vpu_fops);
  928. if ((cdev_add(&s_vpu_cdev, s_vpu_devt, 1)) < 0) {
  929. err = -EBUSY;
  930. printk(KERN_ERR "could not allocate chrdev\n");
  931. goto ERROR_PROVE_DEVICE;
  932. }
  933. s_vpu_class = class_create(THIS_MODULE, VPU_DEV_NAME);
  934. if (IS_ERR(s_vpu_class)) {
  935. dev_err(vpu_dev, "class creat error.\n");
  936. goto ERROR_CRART_CLASS;
  937. }
  938. devices = device_create(s_vpu_class, 0, MKDEV(s_vpu_major, 0),
  939. NULL, VPU_DEV_NAME);
  940. if (IS_ERR(devices)) {
  941. dev_err(vpu_dev, "device creat error.\n");
  942. goto ERROR_CREAT_DEVICE;
  943. }
  944. if (pdev)
  945. s_vpu_clk = vpu_clk_get(pdev);
  946. else
  947. s_vpu_clk = vpu_clk_get(NULL);
  948. if (!s_vpu_clk)
  949. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  950. else
  951. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  952. vpu_pmu_enable(s_vpu_clk->dev);
  953. vpu_clk_enable(s_vpu_clk);
  954. reset_control_deassert(s_vpu_clk->resets);
  955. #ifdef VPU_SUPPORT_ISR
  956. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  957. if (pdev)
  958. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  959. if (res) {/* if platform driver is implemented */
  960. s_vpu_irq = res->start;
  961. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  962. } else {
  963. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  964. }
  965. #else
  966. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  967. #endif
  968. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, "VPU_CODEC_IRQ", (void *)(&s_vpu_drv_context));
  969. if (err) {
  970. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  971. goto ERROR_PROVE_DEVICE;
  972. }
  973. #endif
  974. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  975. s_video_memory.size = VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE;
  976. s_video_memory.phys_addr = VPU_DRAM_PHYSICAL_BASE;
  977. s_video_memory.base = (unsigned long)ioremap_nocache(s_video_memory.phys_addr, PAGE_ALIGN(s_video_memory.size));
  978. if (!s_video_memory.base) {
  979. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr==0x%lx, base==0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  980. goto ERROR_PROVE_DEVICE;
  981. }
  982. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  983. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  984. goto ERROR_PROVE_DEVICE;
  985. }
  986. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr==0x%lx, base = =0x%lx\n", s_video_memory.phys_addr, s_video_memory.base);
  987. #else
  988. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  989. #endif
  990. return 0;
  991. ERROR_CREAT_DEVICE:
  992. class_destroy(s_vpu_class);
  993. ERROR_CRART_CLASS:
  994. cdev_del(&s_vpu_cdev);
  995. ERROR_PROVE_DEVICE:
  996. if (s_vpu_major)
  997. unregister_chrdev_region(s_vpu_major, 1);
  998. if (s_vpu_register.virt_addr)
  999. iounmap((void *)s_vpu_register.virt_addr);
  1000. return err;
  1001. }
  1002. static int vpu_remove(struct platform_device *pdev)
  1003. {
  1004. DPRINTK("[VPUDRV] vpu_remove\n");
  1005. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1006. if (s_instance_pool.base) {
  1007. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1008. vfree((const void *)s_instance_pool.base);
  1009. #else
  1010. vpu_free_dma_buffer(&s_instance_pool);
  1011. #endif
  1012. s_instance_pool.base = 0;
  1013. }
  1014. if (s_common_memory.base) {
  1015. vpu_free_dma_buffer(&s_common_memory);
  1016. s_common_memory.base = 0;
  1017. }
  1018. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1019. if (s_video_memory.base) {
  1020. iounmap((void *)s_video_memory.base);
  1021. s_video_memory.base = 0;
  1022. vmem_exit(&s_vmem);
  1023. }
  1024. #endif
  1025. if (s_vpu_major > 0) {
  1026. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1027. class_destroy(s_vpu_class);
  1028. cdev_del(&s_vpu_cdev);
  1029. unregister_chrdev_region(s_vpu_devt, 1);
  1030. s_vpu_major = 0;
  1031. }
  1032. #ifdef VPU_SUPPORT_ISR
  1033. if (s_vpu_irq)
  1034. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1035. #endif
  1036. if (s_vpu_register.virt_addr)
  1037. iounmap((void *)s_vpu_register.virt_addr);
  1038. vpu_clk_put(s_vpu_clk);
  1039. vpu_pmu_disable(&pdev->dev);
  1040. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1041. return 0;
  1042. }
  1043. #ifdef CONFIG_PM
  1044. #define W4_MAX_CODE_BUF_SIZE (512*1024)
  1045. #define W4_CMD_INIT_VPU (0x0001)
  1046. #define W4_CMD_SLEEP_VPU (0x0400)
  1047. #define W4_CMD_WAKEUP_VPU (0x0800)
  1048. #define W5_CMD_SLEEP_VPU (0x0004)
  1049. #define W5_CMD_WAKEUP_VPU (0x0002)
  1050. static void Wave4BitIssueCommand(int core, u32 cmd)
  1051. {
  1052. WriteVpuRegister(W4_VPU_BUSY_STATUS, 1);
  1053. WriteVpuRegister(W4_CORE_INDEX, 0);
  1054. /* coreIdx = ReadVpuRegister(W4_VPU_BUSY_STATUS);*/
  1055. /* coreIdx = 0;*/
  1056. /* WriteVpuRegister(W4_INST_INDEX, (instanceIndex&0xffff)|(codecMode<<16));*/
  1057. WriteVpuRegister(W4_COMMAND, cmd);
  1058. WriteVpuRegister(W4_VPU_HOST_INT_REQ, 1);
  1059. return;
  1060. }
  1061. static int __maybe_unused vpu_runtime_suspend(struct device *dev)
  1062. {
  1063. reset_control_assert(s_vpu_clk->resets);
  1064. vpu_clk_disable(s_vpu_clk);
  1065. return 0;
  1066. }
  1067. static int __maybe_unused vpu_runtime_resume(struct device *dev)
  1068. {
  1069. vpu_clk_enable(s_vpu_clk);
  1070. return reset_control_deassert(s_vpu_clk->resets);
  1071. }
  1072. #ifdef CONFIG_PM_SLEEP
  1073. static int __maybe_unused vpu_suspend(struct device *dev)
  1074. {
  1075. int i;
  1076. int core;
  1077. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1078. int product_code;
  1079. DPRINTK("[VPUDRV] vpu_suspend\n");
  1080. if (s_vpu_open_ref_count > 0) {
  1081. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1082. if (s_bit_firmware_info[core].size == 0)
  1083. continue;
  1084. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1085. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1086. unsigned long cmd_reg = W4_CMD_SLEEP_VPU;
  1087. unsigned long suc_reg = W4_RET_SUCCESS;
  1088. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1089. if (time_after(jiffies, timeout)) {
  1090. DPRINTK("SLEEP_VPU BUSY timeout");
  1091. goto DONE_SUSPEND;
  1092. }
  1093. }
  1094. if (product_code == WAVE512_CODE || product_code == WAVE520_CODE) {
  1095. cmd_reg = W5_CMD_SLEEP_VPU;
  1096. suc_reg = W5_RET_SUCCESS;
  1097. }
  1098. Wave4BitIssueCommand(core, cmd_reg);
  1099. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1100. if (time_after(jiffies, timeout)) {
  1101. DPRINTK("SLEEP_VPU BUSY timeout");
  1102. goto DONE_SUSPEND;
  1103. }
  1104. }
  1105. if (ReadVpuRegister(suc_reg) == 0) {
  1106. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W4_RET_FAIL_REASON));
  1107. goto DONE_SUSPEND;
  1108. }
  1109. }
  1110. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1111. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1112. if (time_after(jiffies, timeout))
  1113. goto DONE_SUSPEND;
  1114. }
  1115. for (i = 0; i < 64; i++)
  1116. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1117. }
  1118. else {
  1119. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1120. goto DONE_SUSPEND;
  1121. }
  1122. }
  1123. }
  1124. pm_runtime_set_suspended(dev);
  1125. return 0;
  1126. DONE_SUSPEND:
  1127. pm_runtime_set_suspended(dev);
  1128. return -EAGAIN;
  1129. }
  1130. static int __maybe_unused vpu_resume(struct device *dev)
  1131. {
  1132. int i;
  1133. int core;
  1134. u32 val;
  1135. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1136. int product_code;
  1137. unsigned long code_base;
  1138. u32 code_size;
  1139. u32 remap_size;
  1140. int regVal;
  1141. u32 hwOption = 0;
  1142. DPRINTK("[VPUDRV] vpu_resume\n");
  1143. if (s_vpu_open_ref_count == 0) {
  1144. pm_runtime_get_sync(dev);
  1145. } else {
  1146. pm_runtime_set_active(dev);
  1147. //pm_runtime_enable(dev);
  1148. }
  1149. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1150. if (s_bit_firmware_info[core].size == 0) {
  1151. continue;
  1152. }
  1153. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1154. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1155. unsigned long addr_code_base_reg = W4_ADDR_CODE_BASE;
  1156. unsigned long code_size_reg = W4_CODE_SIZE;
  1157. unsigned long code_param_reg = W4_CODE_PARAM;
  1158. unsigned long timeout_cnt_reg = W4_INIT_VPU_TIME_OUT_CNT;
  1159. unsigned long hw_opt_reg = W4_HW_OPTION;
  1160. unsigned long suc_reg = W4_RET_SUCCESS;
  1161. if (product_code == WAVE512_CODE || product_code == WAVE520_CODE) {
  1162. addr_code_base_reg = W5_ADDR_CODE_BASE;
  1163. code_size_reg = W5_CODE_SIZE;
  1164. code_param_reg = W5_CODE_PARAM;
  1165. timeout_cnt_reg = W5_INIT_VPU_TIME_OUT_CNT;
  1166. hw_opt_reg = W5_HW_OPTION;
  1167. suc_reg = W5_RET_SUCCESS;
  1168. }
  1169. code_base = s_common_memory.phys_addr;
  1170. /* ALIGN TO 4KB */
  1171. code_size = (W4_MAX_CODE_BUF_SIZE&~0xfff);
  1172. if (code_size < s_bit_firmware_info[core].size*2) {
  1173. goto DONE_WAKEUP;
  1174. }
  1175. regVal = 0;
  1176. WriteVpuRegister(W4_PO_CONF, regVal);
  1177. /* Reset All blocks */
  1178. regVal = 0x7ffffff;
  1179. WriteVpuRegister(W4_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1180. /* Waiting reset done */
  1181. while (ReadVpuRegister(W4_VPU_RESET_STATUS)) {
  1182. if (time_after(jiffies, timeout))
  1183. goto DONE_WAKEUP;
  1184. }
  1185. WriteVpuRegister(W4_VPU_RESET_REQ, 0);
  1186. /* remap page size */
  1187. remap_size = (code_size >> 12) & 0x1ff;
  1188. regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1189. WriteVpuRegister(W4_VPU_REMAP_CTRL, regVal);
  1190. WriteVpuRegister(W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  1191. WriteVpuRegister(W4_VPU_REMAP_PADDR, code_base);
  1192. WriteVpuRegister(addr_code_base_reg, code_base);
  1193. WriteVpuRegister(code_size_reg, code_size);
  1194. WriteVpuRegister(code_param_reg, 0);
  1195. WriteVpuRegister(timeout_cnt_reg, timeout);
  1196. WriteVpuRegister(hw_opt_reg, hwOption);
  1197. /* Interrupt */
  1198. if (product_code == WAVE512_CODE) {
  1199. // decoder
  1200. regVal = (1<<W5_INT_INIT_SEQ);
  1201. regVal |= (1<<W5_INT_DEC_PIC);
  1202. regVal |= (1<<W5_INT_BSBUF_EMPTY);
  1203. }
  1204. else if (product_code == WAVE520_CODE) {
  1205. regVal = (1<<W5_INT_ENC_SET_PARAM);
  1206. regVal |= (1<<W5_INT_ENC_PIC);
  1207. }
  1208. else {
  1209. regVal = (1<<W4_INT_DEC_PIC_HDR);
  1210. regVal |= (1<<W4_INT_DEC_PIC);
  1211. regVal |= (1<<W4_INT_QUERY_DEC);
  1212. regVal |= (1<<W4_INT_SLEEP_VPU);
  1213. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  1214. }
  1215. WriteVpuRegister(W4_VPU_VINT_ENABLE, regVal);
  1216. Wave4BitIssueCommand(core, W4_CMD_INIT_VPU);
  1217. WriteVpuRegister(W4_VPU_REMAP_CORE_START, 1);
  1218. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1219. if (time_after(jiffies, timeout))
  1220. goto DONE_WAKEUP;
  1221. }
  1222. if (ReadVpuRegister(suc_reg) == 0) {
  1223. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W4_RET_FAIL_REASON));
  1224. goto DONE_WAKEUP;
  1225. }
  1226. }
  1227. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1228. WriteVpuRegister(BIT_CODE_RUN, 0);
  1229. /*---- LOAD BOOT CODE*/
  1230. for (i = 0; i < 512; i++) {
  1231. val = s_bit_firmware_info[core].bit_code[i];
  1232. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1233. }
  1234. for (i = 0 ; i < 64 ; i++)
  1235. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1236. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1237. WriteVpuRegister(BIT_CODE_RESET, 1);
  1238. WriteVpuRegister(BIT_CODE_RUN, 1);
  1239. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1240. if (time_after(jiffies, timeout))
  1241. goto DONE_WAKEUP;
  1242. }
  1243. }
  1244. else {
  1245. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1246. goto DONE_WAKEUP;
  1247. }
  1248. }
  1249. if (s_vpu_open_ref_count == 0) {
  1250. pm_runtime_put_sync(dev);
  1251. pm_runtime_set_suspended(dev);
  1252. }
  1253. DONE_WAKEUP:
  1254. return 0;
  1255. }
  1256. #endif /* CONFIG_PM_SLEEP */
  1257. #endif /* CONFIG_PM */
  1258. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1259. static const struct of_device_id vpu_of_id_table[] = {
  1260. { .compatible = "cnm,cnm420l-vpu" },
  1261. { .compatible = "starfive,venc" },
  1262. {}
  1263. };
  1264. MODULE_DEVICE_TABLE(of, vpu_of_id_table);
  1265. static const struct dev_pm_ops cm_vpu_pm_ops = {
  1266. SET_RUNTIME_PM_OPS(vpu_runtime_suspend,
  1267. vpu_runtime_resume, NULL)
  1268. //SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
  1269. };
  1270. static struct platform_driver vpu_driver = {
  1271. .driver = {
  1272. .name = VPU_PLATFORM_DEVICE_NAME,
  1273. .of_match_table = of_match_ptr(vpu_of_id_table),
  1274. .pm = &cm_vpu_pm_ops,
  1275. },
  1276. .probe = vpu_probe,
  1277. .remove = vpu_remove,
  1278. };
  1279. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1280. static int __init vpu_init(void)
  1281. {
  1282. int res;
  1283. DPRINTK("[VPUDRV] begin vpu_init\n");
  1284. init_waitqueue_head(&s_interrupt_wait_q);
  1285. s_common_memory.base = 0;
  1286. s_instance_pool.base = 0;
  1287. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1288. res = platform_driver_register(&vpu_driver);
  1289. #else
  1290. res = vpu_probe(NULL);
  1291. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1292. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1293. return res;
  1294. }
  1295. static void __exit vpu_exit(void)
  1296. {
  1297. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1298. DPRINTK("[VPUDRV] vpu_exit\n");
  1299. platform_driver_unregister(&vpu_driver);
  1300. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1301. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1302. #else
  1303. vpu_clk_disable(s_vpu_clk);
  1304. #endif
  1305. vpu_clk_put(s_vpu_clk);
  1306. if (s_instance_pool.base) {
  1307. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1308. vfree((const void *)s_instance_pool.base);
  1309. #else
  1310. vpu_free_dma_buffer(&s_instance_pool);
  1311. #endif
  1312. s_instance_pool.base = 0;
  1313. }
  1314. if (s_common_memory.base) {
  1315. vpu_free_dma_buffer(&s_common_memory);
  1316. s_common_memory.base = 0;
  1317. }
  1318. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1319. if (s_video_memory.base) {
  1320. iounmap((void *)s_video_memory.base);
  1321. s_video_memory.base = 0;
  1322. vmem_exit(&s_vmem);
  1323. }
  1324. #endif
  1325. if (s_vpu_major > 0) {
  1326. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1327. class_destroy(s_vpu_class);
  1328. cdev_del(&s_vpu_cdev);
  1329. unregister_chrdev_region(s_vpu_devt, 1);
  1330. s_vpu_major = 0;
  1331. }
  1332. #ifdef VPU_SUPPORT_ISR
  1333. if (s_vpu_irq)
  1334. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1335. #endif
  1336. if (s_vpu_register.virt_addr) {
  1337. iounmap((void *)s_vpu_register.virt_addr);
  1338. s_vpu_register.virt_addr = 0x00;
  1339. }
  1340. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1341. return;
  1342. }
  1343. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1344. MODULE_DESCRIPTION("VPU linux driver");
  1345. MODULE_LICENSE("Dual BSD/GPL");
  1346. module_init(vpu_init);
  1347. module_exit(vpu_exit);
  1348. static int vpu_pmu_enable(struct device *dev)
  1349. {
  1350. pm_runtime_set_active(dev);
  1351. pm_runtime_enable(dev);
  1352. return 0;
  1353. }
  1354. static void vpu_pmu_disable(struct device *dev)
  1355. {
  1356. pm_runtime_disable(dev);
  1357. pm_runtime_set_suspended(dev);
  1358. }
  1359. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1360. #define CLK_ENABLE_DATA 1
  1361. #define CLK_DISABLE_DATA 0
  1362. #define CLK_EN_SHIFT 31
  1363. #define CLK_EN_MASK 0x80000000U
  1364. #define SAIF_BD_APBS_BASE 0x13020000
  1365. #define WAVE420L_CLK_AXI_CTRL 0x138U
  1366. #define WAVE420L_CLK_BPU_CTRL 0x13cU
  1367. #define WAVE420L_CLK_VCE_CTRL 0x140U
  1368. #define WAVE420L_CLK_APB_CTRL 0x144U
  1369. #define WAVE420L_CLK_NOCBUS_CTRL 0x148U
  1370. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1371. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1372. #define RSTN_AXI_MASK (0x1 << 22)
  1373. #define RSTN_BPU_MASK (0x1 << 23)
  1374. #define RSTN_VCE_MASK (0x1 << 24)
  1375. #define RSTN_APB_MASK (0x1 << 25)
  1376. #define RSTN_128B_AXIMEM_MASK (0x1 << 26)
  1377. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1378. uint32_t shift, uint32_t mask)
  1379. {
  1380. uint32_t tmp;
  1381. tmp = readl(addr);
  1382. tmp &= ~mask;
  1383. tmp |= (data << shift) & mask;
  1384. writel(tmp, addr);
  1385. }
  1386. static void saif_assert_rst(volatile void __iomem *addr,
  1387. const volatile void __iomem *addr_status, uint32_t mask)
  1388. {
  1389. uint32_t tmp;
  1390. tmp = readl(addr);
  1391. tmp |= mask;
  1392. writel(tmp, addr);
  1393. do {
  1394. tmp = readl(addr_status);
  1395. } while ((tmp & mask) != 0);
  1396. }
  1397. static void saif_clear_rst(volatile void __iomem *addr,
  1398. const volatile void __iomem *addr_status, uint32_t mask)
  1399. {
  1400. uint32_t tmp;
  1401. tmp = readl(addr);
  1402. tmp &= ~mask;
  1403. writel(tmp, addr);
  1404. do {
  1405. tmp = readl(addr_status);
  1406. } while ((tmp & mask) != mask);
  1407. }
  1408. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1409. {
  1410. if (enable)
  1411. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1412. else
  1413. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1414. }
  1415. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1416. {
  1417. if (enable) {
  1418. /*enable*/
  1419. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1420. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1421. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1422. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1423. /*clr-reset*/
  1424. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1425. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1426. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1427. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1428. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1429. } else {
  1430. /*assert-reset*/
  1431. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1432. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1433. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1434. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1435. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1436. /*disable*/
  1437. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1438. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1439. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1440. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1441. }
  1442. }
  1443. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1444. {
  1445. if (!pdev)
  1446. return -ENXIO;
  1447. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1448. if (IS_ERR(vpu_clk->clkgen)) {
  1449. dev_err(dev, "ioremap clkgen failed.\n");
  1450. return PTR_ERR(vpu_clk->clkgen);
  1451. }
  1452. /* clkgen define */
  1453. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_AXI_CTRL;
  1454. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_BPU_CTRL;
  1455. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_VCE_CTRL;
  1456. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_APB_CTRL;
  1457. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE420L_CLK_NOCBUS_CTRL;
  1458. vpu_clk->en_mask = CLK_EN_MASK;
  1459. vpu_clk->en_shift = CLK_EN_SHIFT;
  1460. /* rstgen define */
  1461. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1462. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1463. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1464. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1465. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1466. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1467. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1468. if (device_property_read_bool(&pdev->dev, "starfive,venc_noc_ctrl"))
  1469. vpu_clk->noc_ctrl = true;
  1470. return 0;
  1471. }
  1472. static void vpu_clk_reset(vpu_clk_t *clk)
  1473. {
  1474. /*assert-reset*/
  1475. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1476. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1477. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1478. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1479. /*clr-reset*/
  1480. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1481. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1482. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1483. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1484. }
  1485. int vpu_hw_reset(void)
  1486. {
  1487. if (!s_vpu_clk)
  1488. return -1;
  1489. vpu_clk_reset(s_vpu_clk);
  1490. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1491. return 0;
  1492. }
  1493. struct vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1494. {
  1495. vpu_clk_t *vpu_clk;
  1496. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1497. if (!vpu_clk)
  1498. return NULL;
  1499. if (vpu_of_clk_get(dev, vpu_clk))
  1500. goto err_get_clk;
  1501. return vpu_clk;
  1502. err_get_clk:
  1503. devm_kfree(&pdev->dev, vpu_clk);
  1504. return NULL;
  1505. }
  1506. void vpu_clk_put(struct vpu_clk_t *clk)
  1507. {
  1508. if (clk->clkgen) {
  1509. iounmap(clk->clkgen);
  1510. clk->clkgen = NULL;
  1511. }
  1512. }
  1513. static int vpu_clk_enable(struct vpu_clk_t *clk)
  1514. {
  1515. if (clk == NULL || IS_ERR(clk))
  1516. return -1;
  1517. vpu_pmu_enable(clk->dev);
  1518. vpu_clk_control(clk, true);
  1519. if (clk->noc_ctrl == true)
  1520. vpu_noc_vdec_bus_control(clk, true);
  1521. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1522. return 0;
  1523. }
  1524. void vpu_clk_disable(struct vpu_clk_t *clk)
  1525. {
  1526. if (clk == NULL || IS_ERR(clk))
  1527. return;
  1528. vpu_clk_control(clk, false);
  1529. vpu_pmu_disable(clk->dev);
  1530. if (clk->noc_ctrl == true)
  1531. vpu_noc_vdec_bus_control(clk, false);
  1532. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1533. }
  1534. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1535. static const struct vpu_dev_freq_list wave420l_dev_freq_lists[MODE_MAX+1] = {
  1536. [MODE_480P_30F] = {
  1537. .mode = MODE_480P_30F,
  1538. .axi_rate = VPU_DEV_FREQ_80,
  1539. .bpu_rate = VPU_DEV_FREQ_80,
  1540. .vce_rate = VPU_DEV_FREQ_80,
  1541. },
  1542. [MODE_480P_60F] = {
  1543. .mode = MODE_480P_60F,
  1544. .axi_rate = VPU_DEV_FREQ_100,
  1545. .bpu_rate = VPU_DEV_FREQ_100,
  1546. .vce_rate = VPU_DEV_FREQ_100,
  1547. },
  1548. [MODE_720P_30F] = {
  1549. .mode = MODE_720P_30F,
  1550. .axi_rate = VPU_DEV_FREQ_150,
  1551. .bpu_rate = VPU_DEV_FREQ_150,
  1552. .vce_rate = VPU_DEV_FREQ_150,
  1553. },
  1554. [MODE_720P_60F] = {
  1555. .mode = MODE_720P_60F,
  1556. .axi_rate = VPU_DEV_FREQ_237,
  1557. .bpu_rate = VPU_DEV_FREQ_237,
  1558. .vce_rate = VPU_DEV_FREQ_237,
  1559. },
  1560. [MODE_1080P_30F] = {
  1561. .mode = MODE_1080P_30F,
  1562. .axi_rate = VPU_DEV_FREQ_300,
  1563. .bpu_rate = VPU_DEV_FREQ_300,
  1564. .vce_rate = VPU_DEV_FREQ_300,
  1565. },
  1566. [MODE_MAX] = {
  1567. .mode = MODE_MAX,
  1568. .axi_rate = VPU_DEV_FREQ_MAX,
  1569. .bpu_rate = VPU_DEV_FREQ_MAX,
  1570. .vce_rate = VPU_DEV_FREQ_MAX,
  1571. },
  1572. };
  1573. static int vpu_devfreq_init(vpu_clk_t *vpu_clk)
  1574. {
  1575. struct vpu_devfreq_t *dev_freq = &vpu_clk->vpu_devfreq;
  1576. dev_freq->axi_clk = devm_clk_get_optional(vpu_clk->dev, "axi_clk");
  1577. if (IS_ERR(dev_freq->axi_clk))
  1578. return PTR_ERR(dev_freq->axi_clk);
  1579. dev_freq->bpu_clk = devm_clk_get_optional(vpu_clk->dev, "bpu_clk");
  1580. if (IS_ERR(dev_freq->bpu_clk))
  1581. return PTR_ERR(dev_freq->bpu_clk);
  1582. dev_freq->vce_clk = devm_clk_get_optional(vpu_clk->dev, "vce_clk");
  1583. if (IS_ERR(dev_freq->vce_clk))
  1584. return PTR_ERR(dev_freq->vce_clk);
  1585. return 0;
  1586. }
  1587. static int vpu_devfreq_set(vpu_clk_t *vpu_clk, const struct vpu_dev_freq_list *freq_list)
  1588. {
  1589. struct vpu_devfreq_t *dev_freq = &vpu_clk->vpu_devfreq;
  1590. int ret;
  1591. dev_dbg(vpu_clk->dev, "axi_clk:%ld bpu_clk:%ld vce_clk:%ld\n",
  1592. freq_list->axi_rate, freq_list->bpu_rate, freq_list->vce_rate);
  1593. ret = clk_set_rate(dev_freq->axi_clk, freq_list->axi_rate);
  1594. if (ret)
  1595. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1596. ret = clk_set_rate(dev_freq->bpu_clk, freq_list->bpu_rate);
  1597. if (ret)
  1598. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1599. ret = clk_set_rate(dev_freq->vce_clk, freq_list->vce_rate);
  1600. if (ret)
  1601. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1602. return ret;
  1603. }
  1604. static int vpu_devfreq_select(struct vpudrv_devfreq_info_t *info)
  1605. {
  1606. unsigned long framsize = info->picWidth*info->picHeight;
  1607. int frameRateInfo = info->frameRateInfo;
  1608. int mode;
  1609. if (frameRateInfo <= 30) {
  1610. if (framsize <= FRAMSIZE_480P)
  1611. mode = MODE_480P_30F;
  1612. else if (framsize <= FRAMSIZE_720P)
  1613. mode = MODE_720P_30F;
  1614. else if (framsize <= FRAMSIZE_1080P)
  1615. mode = MODE_1080P_30F;
  1616. else
  1617. mode = MODE_MAX;
  1618. } else {
  1619. if (framsize <= FRAMSIZE_480P)
  1620. mode = MODE_480P_60F;
  1621. else if (framsize <= FRAMSIZE_720P)
  1622. mode = MODE_720P_60F;
  1623. else
  1624. mode = MODE_MAX;
  1625. }
  1626. return vpu_devfreq_set(s_vpu_clk, &wave420l_dev_freq_lists[mode]);
  1627. }
  1628. int vpu_hw_reset(void)
  1629. {
  1630. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1631. /* sram do not need reset */
  1632. return reset_control_reset(s_vpu_clk->resets);
  1633. }
  1634. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1635. {
  1636. struct device *dev = &pdev->dev;
  1637. int ret;
  1638. vpu_clk->dev = dev;
  1639. vpu_clk->clks = vpu_clks;
  1640. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  1641. vpu_clk->resets = devm_reset_control_array_get_exclusive(dev);
  1642. if (IS_ERR(vpu_clk->resets)) {
  1643. ret = PTR_ERR(vpu_clk->resets);
  1644. dev_err(dev, "faied to get vpu reset controls\n");
  1645. }
  1646. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  1647. if (ret)
  1648. dev_err(dev, "faied to get vpu clk controls\n");
  1649. if (device_property_read_bool(dev, "starfive,venc_noc_ctrl"))
  1650. vpu_clk->noc_ctrl = true;
  1651. return 0;
  1652. }
  1653. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1654. {
  1655. vpu_clk_t *vpu_clk;
  1656. if (!pdev)
  1657. return NULL;
  1658. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1659. if (!vpu_clk)
  1660. return NULL;
  1661. if (vpu_of_clk_get(pdev, vpu_clk))
  1662. goto err_of_clk_get;
  1663. vpu_devfreq_init(vpu_clk);
  1664. return vpu_clk;
  1665. err_of_clk_get:
  1666. devm_kfree(&pdev->dev, vpu_clk);
  1667. return NULL;
  1668. }
  1669. static void vpu_clk_put(vpu_clk_t *clk)
  1670. {
  1671. clk_bulk_put(clk->nr_clks, clk->clks);
  1672. }
  1673. static int vpu_clk_enable(vpu_clk_t *clk)
  1674. {
  1675. int ret;
  1676. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1677. if (ret)
  1678. dev_err(clk->dev, "enable clk error.\n");
  1679. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1680. return ret;
  1681. }
  1682. static void vpu_clk_disable(vpu_clk_t *clk)
  1683. {
  1684. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  1685. }
  1686. #endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/