vdec.c 71 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/of.h>
  9. #include <linux/pm_runtime.h>
  10. #include <linux/wait.h>
  11. #include <linux/list.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/uaccess.h>
  15. #include <linux/cdev.h>
  16. #include <linux/slab.h>
  17. #include <linux/of_address.h>
  18. #include <linux/sched.h>
  19. #include <linux/sched/signal.h>
  20. #include <linux/version.h>
  21. #include <linux/kfifo.h>
  22. #include <linux/kthread.h>
  23. #include <linux/reset.h>
  24. #include <asm/io.h>
  25. #include <soc/sifive/sifive_l2_cache.h>
  26. #include "../../../vpuapi/vpuconfig.h"
  27. #include "vpu.h"
  28. //#define ENABLE_DEBUG_MSG
  29. #ifdef ENABLE_DEBUG_MSG
  30. #define DPRINTK(args...) printk(KERN_INFO args);
  31. #else
  32. #define DPRINTK(args...)
  33. #endif
  34. /* definitions to be changed as customer configuration */
  35. /* if you want to have clock gating scheme frame by frame */
  36. /* #define VPU_SUPPORT_CLOCK_CONTROL */
  37. /* if the driver want to use interrupt service from kernel ISR */
  38. #define VPU_SUPPORT_ISR
  39. #ifdef VPU_SUPPORT_ISR
  40. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  41. //#define VPU_IRQ_CONTROL
  42. #endif
  43. /* if clktree is work,try this...*/
  44. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  45. /* if the platform driver knows the name of this driver */
  46. /* VPU_PLATFORM_DEVICE_NAME */
  47. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  48. /* if this driver knows the dedicated video memory address */
  49. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  50. static void starfive_flush_dcache(unsigned long start, unsigned long len)
  51. {
  52. sifive_l2_flush64_range(start, len);
  53. }
  54. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  55. #define VPU_CLK_NAME "vcodec"
  56. #define VPU_DEV_NAME "vdec"
  57. /* if the platform driver knows this driver */
  58. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  59. #define VPU_REG_BASE_ADDR 0x118F0000
  60. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  61. #ifdef VPU_SUPPORT_ISR
  62. #define VPU_IRQ_NUM (23)
  63. #endif
  64. /* this definition is only for chipsnmedia FPGA board env */
  65. /* so for SOC env of customers can be ignored */
  66. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  67. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  68. #endif
  69. struct device *vpu_dev;
  70. typedef struct vpu_drv_context_t {
  71. struct fasync_struct *async_queue;
  72. #ifdef SUPPORT_MULTI_INST_INTR
  73. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  74. #else
  75. unsigned long interrupt_reason;
  76. #endif
  77. u32 open_count; /*!<< device reference count. Not instance count */
  78. } vpu_drv_context_t;
  79. /* To track the allocated memory buffer */
  80. typedef struct vpudrv_buffer_pool_t {
  81. struct list_head list;
  82. struct vpudrv_buffer_t vb;
  83. struct file *filp;
  84. } vpudrv_buffer_pool_t;
  85. /* To track the instance index and buffer in instance pool */
  86. typedef struct vpudrv_instanace_list_t {
  87. struct list_head list;
  88. unsigned long inst_idx;
  89. unsigned long core_idx;
  90. struct file *filp;
  91. } vpudrv_instanace_list_t;
  92. typedef struct vpudrv_instance_pool_t {
  93. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  94. } vpudrv_instance_pool_t;
  95. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  96. typedef struct vpu_clkgen_t {
  97. void __iomem *en_ctrl;
  98. uint32_t rst_mask;
  99. } vpu_clkgen_t;
  100. #endif
  101. struct clk_bulk_data vpu_clks[] = {
  102. { .id = "apb_clk" },
  103. { .id = "axi_clk" },
  104. { .id = "bpu_clk" },
  105. { .id = "vce_clk" },
  106. { .id = "noc_bus" },
  107. };
  108. typedef struct vpu_clk_t {
  109. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  110. void __iomem *clkgen;
  111. void __iomem *rst_ctrl;
  112. void __iomem *rst_status;
  113. void __iomem *noc_bus;
  114. uint32_t en_shift;
  115. uint32_t en_mask;
  116. vpu_clkgen_t apb_clk;
  117. vpu_clkgen_t axi_clk;
  118. vpu_clkgen_t bpu_clk;
  119. vpu_clkgen_t vce_clk;
  120. vpu_clkgen_t aximem_128b;
  121. #else
  122. struct clk_bulk_data *clks;
  123. struct reset_control *resets;
  124. int nr_clks;
  125. #endif
  126. struct device *dev;
  127. bool noc_ctrl;
  128. } vpu_clk_t;
  129. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  130. #include "vmm.h"
  131. static video_mm_t s_vmem;
  132. static vpudrv_buffer_t s_video_memory = {0};
  133. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  134. static int vpu_hw_reset(void);
  135. static void vpu_clk_disable(vpu_clk_t *clk);
  136. static int vpu_clk_enable(vpu_clk_t *clk);
  137. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  138. static void vpu_clk_put(vpu_clk_t *clk);
  139. /* end customer definition */
  140. static vpudrv_buffer_t s_instance_pool = {0};
  141. static vpudrv_buffer_t s_common_memory = {0};
  142. static vpu_drv_context_t s_vpu_drv_context;
  143. static int s_vpu_major;
  144. static struct cdev s_vpu_cdev;
  145. static vpu_clk_t *s_vpu_clk;
  146. static int s_vpu_open_ref_count;
  147. #ifdef VPU_SUPPORT_ISR
  148. static int s_vpu_irq = VPU_IRQ_NUM;
  149. #endif
  150. static vpudrv_buffer_t s_vpu_register = {0};
  151. #ifdef SUPPORT_MULTI_INST_INTR
  152. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  153. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  154. typedef struct kfifo kfifo_t;
  155. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  156. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  157. #else
  158. static int s_interrupt_flag;
  159. static wait_queue_head_t s_interrupt_wait_q;
  160. #endif
  161. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  162. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  163. static DECLARE_MUTEX(s_vpu_sem);
  164. #else
  165. static DEFINE_SEMAPHORE(s_vpu_sem);
  166. #endif
  167. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  168. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  169. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  170. //#ifdef CONFIG_PM
  171. /* implement to power management functions */
  172. #define BIT_BASE 0x0000
  173. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  174. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  175. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  176. #define BIT_INT_STS (BIT_BASE + 0x010)
  177. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  178. #define BIT_INT_REASON (BIT_BASE + 0x174)
  179. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  180. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  181. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  182. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  183. /* WAVE5 registers */
  184. #define W5_REG_BASE 0x0000
  185. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  186. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  187. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  188. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  189. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  190. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  191. #ifdef SUPPORT_MULTI_INST_INTR
  192. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  193. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  194. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  195. typedef enum {
  196. INT_WAVE5_INIT_VPU = 0,
  197. INT_WAVE5_WAKEUP_VPU = 1,
  198. INT_WAVE5_SLEEP_VPU = 2,
  199. INT_WAVE5_CREATE_INSTANCE = 3,
  200. INT_WAVE5_FLUSH_INSTANCE = 4,
  201. INT_WAVE5_DESTORY_INSTANCE = 5,
  202. INT_WAVE5_INIT_SEQ = 6,
  203. INT_WAVE5_SET_FRAMEBUF = 7,
  204. INT_WAVE5_DEC_PIC = 8,
  205. INT_WAVE5_ENC_PIC = 8,
  206. INT_WAVE5_ENC_SET_PARAM = 9,
  207. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  208. INT_WAVE5_ENC_SRC_RELEASE = 10,
  209. #endif
  210. INT_WAVE5_ENC_LOW_LATENCY = 13,
  211. INT_WAVE5_DEC_QUERY = 14,
  212. INT_WAVE5_BSBUF_EMPTY = 15,
  213. INT_WAVE5_BSBUF_FULL = 15,
  214. } Wave5InterruptBit;
  215. #endif
  216. /* WAVE5 INIT, WAKEUP */
  217. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  218. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  219. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  220. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  221. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  222. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  223. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  224. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  225. #define W5_REMAP_CODE_INDEX 0
  226. /* WAVE5 registers */
  227. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  228. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  229. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  230. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  231. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  232. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  233. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  234. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  235. /* Product register */
  236. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  237. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  238. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  239. #endif
  240. //#endif //CONFIG_PM
  241. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  242. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  243. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  244. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  245. {
  246. if (!vb)
  247. return -1;
  248. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  249. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  250. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  251. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  252. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  253. return -1;
  254. }
  255. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  256. #else
  257. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  258. if ((void *)(vb->base) == NULL) {
  259. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  260. return -1;
  261. }
  262. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  263. #endif
  264. return 0;
  265. }
  266. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  267. {
  268. if (!vb)
  269. return;
  270. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  271. if (vb->base)
  272. vmem_free(&s_vmem, vb->phys_addr, 0);
  273. #else
  274. if (vb->base)
  275. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  276. #endif
  277. }
  278. static int vpu_free_instances(struct file *filp)
  279. {
  280. vpudrv_instanace_list_t *vil, *n;
  281. vpudrv_instance_pool_t *vip;
  282. void *vip_base;
  283. int instance_pool_size_per_core;
  284. void *vdi_mutexes_base;
  285. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  286. DPRINTK("[VPUDRV] vpu_free_instances\n");
  287. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  288. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  289. {
  290. if (vil->filp == filp) {
  291. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  292. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  293. vip = (vpudrv_instance_pool_t *)vip_base;
  294. if (vip) {
  295. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  296. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  297. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  298. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  299. if (vdi_mutexes_base) {
  300. int i;
  301. for (i = 0; i < 4; i++) {
  302. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  303. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  304. }
  305. }
  306. }
  307. s_vpu_open_ref_count--;
  308. list_del(&vil->list);
  309. kfree(vil);
  310. }
  311. }
  312. return 1;
  313. }
  314. static int vpu_free_buffers(struct file *filp)
  315. {
  316. vpudrv_buffer_pool_t *pool, *n;
  317. vpudrv_buffer_t vb;
  318. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  319. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  320. {
  321. if (pool->filp == filp) {
  322. vb = pool->vb;
  323. if (vb.base) {
  324. vpu_free_dma_buffer(&vb);
  325. list_del(&pool->list);
  326. kfree(pool);
  327. }
  328. }
  329. }
  330. return 0;
  331. }
  332. #ifdef SUPPORT_MULTI_INST_INTR
  333. static inline u32 get_inst_idx(u32 reg_val)
  334. {
  335. u32 inst_idx;
  336. int i;
  337. for (i=0; i < MAX_NUM_INSTANCE; i++)
  338. {
  339. if(((reg_val >> i)&0x01) == 1)
  340. break;
  341. }
  342. inst_idx = i;
  343. return inst_idx;
  344. }
  345. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  346. {
  347. s32 inst_idx;
  348. u32 reg_val;
  349. u32 int_reason;
  350. int_reason = *reason;
  351. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  352. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  353. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  354. {
  355. reg_val = (empty_inst & 0xffff);
  356. inst_idx = get_inst_idx(reg_val);
  357. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  358. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  359. goto GET_VPU_INST_IDX_HANDLED;
  360. }
  361. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  362. {
  363. reg_val = (seq_inst & 0xffff);
  364. inst_idx = get_inst_idx(reg_val);
  365. *reason = (1 << INT_WAVE5_INIT_SEQ);
  366. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  367. goto GET_VPU_INST_IDX_HANDLED;
  368. }
  369. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  370. {
  371. reg_val = (done_inst & 0xffff);
  372. inst_idx = get_inst_idx(reg_val);
  373. *reason = (1 << INT_WAVE5_DEC_PIC);
  374. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  375. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  376. {
  377. u32 ll_inst_idx;
  378. reg_val = (done_inst >> 16);
  379. ll_inst_idx = get_inst_idx(reg_val);
  380. if (ll_inst_idx == inst_idx)
  381. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  382. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  383. }
  384. goto GET_VPU_INST_IDX_HANDLED;
  385. }
  386. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  387. {
  388. reg_val = (seq_inst & 0xffff);
  389. inst_idx = get_inst_idx(reg_val);
  390. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  391. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  392. goto GET_VPU_INST_IDX_HANDLED;
  393. }
  394. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  395. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  396. {
  397. reg_val = (done_inst & 0xffff);
  398. inst_idx = get_inst_idx(reg_val);
  399. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  400. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  401. goto GET_VPU_INST_IDX_HANDLED;
  402. }
  403. #endif
  404. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  405. {
  406. reg_val = (done_inst >> 16);
  407. inst_idx = get_inst_idx(reg_val);
  408. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  409. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  410. goto GET_VPU_INST_IDX_HANDLED;
  411. }
  412. inst_idx = -1;
  413. *reason = 0;
  414. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  415. GET_VPU_INST_IDX_HANDLED:
  416. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  417. return inst_idx;
  418. }
  419. #endif
  420. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  421. {
  422. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  423. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  424. int core;
  425. int product_code;
  426. #ifdef SUPPORT_MULTI_INST_INTR
  427. u32 intr_reason;
  428. s32 intr_inst_index;
  429. #endif
  430. DPRINTK("[VPUDRV][+]%s\n", __func__);
  431. #ifdef VPU_IRQ_CONTROL
  432. disable_irq_nosync(s_vpu_irq);
  433. #endif
  434. #ifdef SUPPORT_MULTI_INST_INTR
  435. intr_inst_index = 0;
  436. intr_reason = 0;
  437. #endif
  438. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  439. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  440. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  441. continue;
  442. }
  443. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  444. if (PRODUCT_CODE_W_SERIES(product_code)) {
  445. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  446. #ifdef SUPPORT_MULTI_INST_INTR
  447. u32 empty_inst;
  448. u32 done_inst;
  449. u32 seq_inst;
  450. u32 i, reason, reason_clr;
  451. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  452. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  453. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  454. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  455. reason_clr = reason;
  456. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  457. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  458. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  459. intr_reason = reason;
  460. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  461. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  462. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  463. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  464. empty_inst = empty_inst & ~(1 << intr_inst_index);
  465. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  466. if (0 == empty_inst) {
  467. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  468. }
  469. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  470. }
  471. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  472. {
  473. done_inst = done_inst & ~(1 << intr_inst_index);
  474. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  475. if (0 == done_inst) {
  476. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  477. }
  478. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  479. }
  480. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  481. {
  482. seq_inst = seq_inst & ~(1 << intr_inst_index);
  483. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  484. if (0 == seq_inst) {
  485. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  486. }
  487. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  488. }
  489. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  490. {
  491. done_inst = (done_inst >> 16);
  492. done_inst = done_inst & ~(1 << intr_inst_index);
  493. done_inst = (done_inst << 16);
  494. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  495. if (0 == done_inst) {
  496. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  497. }
  498. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  499. }
  500. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  501. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  502. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  503. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  504. }
  505. else
  506. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  507. }
  508. else {
  509. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  510. }
  511. }
  512. else {
  513. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  514. }
  515. }
  516. if (0 != reason)
  517. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  518. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  519. #else
  520. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  521. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  522. #endif
  523. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  524. }
  525. }
  526. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  527. if (ReadVpuRegister(BIT_INT_STS)) {
  528. #ifdef SUPPORT_MULTI_INST_INTR
  529. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  530. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  531. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  532. #else
  533. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  534. #endif
  535. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  536. }
  537. }
  538. else {
  539. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  540. continue;
  541. }
  542. #ifdef SUPPORT_MULTI_INST_INTR
  543. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  544. #else
  545. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  546. #endif
  547. }
  548. if (dev->async_queue)
  549. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  550. #ifdef SUPPORT_MULTI_INST_INTR
  551. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  552. s_interrupt_flag[intr_inst_index]= 1;
  553. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  554. }
  555. #else
  556. s_interrupt_flag = 1;
  557. wake_up_interruptible(&s_interrupt_wait_q);
  558. #endif
  559. DPRINTK("[VPUDRV][-]%s\n", __func__);
  560. return IRQ_HANDLED;
  561. }
  562. static int vpu_open(struct inode *inode, struct file *filp)
  563. {
  564. DPRINTK("[VPUDRV][+] %s\n", __func__);
  565. spin_lock(&s_vpu_lock);
  566. s_vpu_drv_context.open_count++;
  567. filp->private_data = (void *)(&s_vpu_drv_context);
  568. spin_unlock(&s_vpu_lock);
  569. DPRINTK("[VPUDRV][-] %s\n", __func__);
  570. return 0;
  571. }
  572. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  573. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  574. {
  575. int ret = 0;
  576. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  577. switch (cmd) {
  578. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  579. {
  580. vpudrv_buffer_pool_t *vbp = NULL;
  581. void *user_address = NULL;
  582. struct task_struct *my_struct = NULL;
  583. struct mm_struct *mm = NULL;
  584. unsigned long address = 0;
  585. pgd_t *pgd = NULL;
  586. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  587. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  588. if (!vbp) {
  589. up(&s_vpu_sem);
  590. return -ENOMEM;
  591. }
  592. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  593. if (ret) {
  594. kfree(vbp);
  595. up(&s_vpu_sem);
  596. return -EFAULT;
  597. }
  598. user_address = (void *)vbp->vb.virt_addr;
  599. my_struct = get_current();
  600. mm = my_struct->mm;
  601. address = (unsigned long)user_address;
  602. pgd = pgd_offset(mm, address);
  603. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  604. p4d_t *p4d = p4d_offset(pgd, address);
  605. pud_t *pud = pud_offset(p4d, address);
  606. if (!pud_none(*pud) && !pud_bad(*pud)) {
  607. pmd_t *pmd = pmd_offset(pud, address);
  608. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  609. pte_t *pte = pte_offset_map(pmd, address);
  610. if (!pte_none(*pte)) {
  611. struct page *pg = pte_page(*pte);
  612. unsigned long phys = page_to_phys(pg);
  613. unsigned long virt = (unsigned long)phys_to_virt(phys);
  614. printk("phy address = %lx, virt = %lx\r\n", phys, virt);
  615. vbp->vb.phys_addr = phys;
  616. vbp->vb.base = virt;
  617. }
  618. pte_unmap(pte);
  619. }
  620. }
  621. }
  622. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  623. if (ret) {
  624. kfree(vbp);
  625. ret = -EFAULT;
  626. up(&s_vpu_sem);
  627. break;
  628. }
  629. vbp->filp = filp;
  630. spin_lock(&s_vpu_lock);
  631. list_add(&vbp->list, &s_vbp_head);
  632. spin_unlock(&s_vpu_lock);
  633. up(&s_vpu_sem);
  634. }
  635. }
  636. break;
  637. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  638. {
  639. vpudrv_buffer_pool_t *vbp;
  640. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  641. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  642. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  643. if (!vbp) {
  644. up(&s_vpu_sem);
  645. return -ENOMEM;
  646. }
  647. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  648. if (ret) {
  649. kfree(vbp);
  650. up(&s_vpu_sem);
  651. return -EFAULT;
  652. }
  653. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  654. if (ret == -1) {
  655. ret = -ENOMEM;
  656. kfree(vbp);
  657. up(&s_vpu_sem);
  658. break;
  659. }
  660. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  661. if (ret) {
  662. kfree(vbp);
  663. ret = -EFAULT;
  664. up(&s_vpu_sem);
  665. break;
  666. }
  667. vbp->filp = filp;
  668. spin_lock(&s_vpu_lock);
  669. list_add(&vbp->list, &s_vbp_head);
  670. spin_unlock(&s_vpu_lock);
  671. up(&s_vpu_sem);
  672. }
  673. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  674. }
  675. break;
  676. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  677. {
  678. vpudrv_buffer_pool_t *vbp, *n;
  679. vpudrv_buffer_t vb;
  680. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  681. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  682. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  683. if (ret) {
  684. up(&s_vpu_sem);
  685. return -EACCES;
  686. }
  687. if (vb.base)
  688. vpu_free_dma_buffer(&vb);
  689. spin_lock(&s_vpu_lock);
  690. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  691. {
  692. if (vbp->vb.base == vb.base) {
  693. list_del(&vbp->list);
  694. kfree(vbp);
  695. break;
  696. }
  697. }
  698. spin_unlock(&s_vpu_lock);
  699. up(&s_vpu_sem);
  700. }
  701. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  702. }
  703. break;
  704. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  705. {
  706. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  707. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  708. if (s_video_memory.base != 0) {
  709. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  710. if (ret != 0)
  711. ret = -EFAULT;
  712. } else {
  713. ret = -EFAULT;
  714. }
  715. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  716. #endif
  717. }
  718. break;
  719. case VDI_IOCTL_WAIT_INTERRUPT:
  720. {
  721. vpudrv_intr_info_t info;
  722. #ifdef SUPPORT_MULTI_INST_INTR
  723. u32 intr_inst_index;
  724. u32 intr_reason_in_q;
  725. u32 interrupt_flag_in_q;
  726. #endif
  727. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  728. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  729. if (ret != 0)
  730. {
  731. return -EFAULT;
  732. }
  733. #ifdef SUPPORT_MULTI_INST_INTR
  734. intr_inst_index = info.intr_inst_index;
  735. intr_reason_in_q = 0;
  736. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  737. if (interrupt_flag_in_q > 0)
  738. {
  739. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  740. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  741. goto INTERRUPT_REMAIN_IN_QUEUE;
  742. }
  743. #endif
  744. #ifdef SUPPORT_MULTI_INST_INTR
  745. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  746. kt = ktime_set(0, info.timeout*1000*1000);
  747. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  748. #else
  749. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  750. #endif
  751. #else
  752. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  753. #endif
  754. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  755. if (ret == -ETIME) {
  756. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  757. break;
  758. }
  759. #endif
  760. if (!ret) {
  761. ret = -ETIME;
  762. break;
  763. }
  764. if (signal_pending(current)) {
  765. ret = -ERESTARTSYS;
  766. break;
  767. }
  768. #ifdef SUPPORT_MULTI_INST_INTR
  769. intr_reason_in_q = 0;
  770. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  771. if (interrupt_flag_in_q > 0) {
  772. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  773. }
  774. else {
  775. dev->interrupt_reason[intr_inst_index] = 0;
  776. }
  777. #endif
  778. #ifdef SUPPORT_MULTI_INST_INTR
  779. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  780. #else
  781. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  782. #endif
  783. #ifdef SUPPORT_MULTI_INST_INTR
  784. INTERRUPT_REMAIN_IN_QUEUE:
  785. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  786. s_interrupt_flag[intr_inst_index] = 0;
  787. dev->interrupt_reason[intr_inst_index] = 0;
  788. #else
  789. info.intr_reason = dev->interrupt_reason;
  790. s_interrupt_flag = 0;
  791. dev->interrupt_reason = 0;
  792. #endif
  793. #ifdef VPU_IRQ_CONTROL
  794. enable_irq(s_vpu_irq);
  795. #endif
  796. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  797. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  798. if (ret != 0)
  799. {
  800. return -EFAULT;
  801. }
  802. }
  803. break;
  804. case VDI_IOCTL_SET_CLOCK_GATE:
  805. {
  806. u32 clkgate;
  807. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  808. if (get_user(clkgate, (u32 __user *) arg))
  809. return -EFAULT;
  810. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  811. if (clkgate)
  812. vpu_clk_enable(s_vpu_clk);
  813. else
  814. vpu_clk_disable(s_vpu_clk);
  815. #endif
  816. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  817. }
  818. break;
  819. case VDI_IOCTL_GET_INSTANCE_POOL:
  820. {
  821. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  822. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  823. if (s_instance_pool.base != 0) {
  824. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  825. if (ret != 0)
  826. ret = -EFAULT;
  827. } else {
  828. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  829. if (ret == 0) {
  830. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  831. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  832. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  833. s_instance_pool.phys_addr = s_instance_pool.base;
  834. if (s_instance_pool.base != 0)
  835. #else
  836. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  837. #endif
  838. {
  839. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  840. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  841. if (ret == 0) {
  842. /* success to get memory for instance pool */
  843. up(&s_vpu_sem);
  844. break;
  845. }
  846. }
  847. }
  848. ret = -EFAULT;
  849. }
  850. up(&s_vpu_sem);
  851. }
  852. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  853. }
  854. break;
  855. case VDI_IOCTL_GET_COMMON_MEMORY:
  856. {
  857. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  858. if (s_common_memory.base != 0) {
  859. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  860. if (ret != 0)
  861. ret = -EFAULT;
  862. } else {
  863. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  864. if (ret == 0) {
  865. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  866. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  867. if (ret == 0) {
  868. /* success to get memory for common memory */
  869. break;
  870. }
  871. }
  872. }
  873. ret = -EFAULT;
  874. }
  875. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  876. }
  877. break;
  878. case VDI_IOCTL_OPEN_INSTANCE:
  879. {
  880. vpudrv_inst_info_t inst_info;
  881. vpudrv_instanace_list_t *vil, *n;
  882. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  883. if (!vil)
  884. return -ENOMEM;
  885. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  886. return -EFAULT;
  887. vil->inst_idx = inst_info.inst_idx;
  888. vil->core_idx = inst_info.core_idx;
  889. vil->filp = filp;
  890. spin_lock(&s_vpu_lock);
  891. list_add(&vil->list, &s_inst_list_head);
  892. inst_info.inst_open_count = 0; /* counting the current open instance number */
  893. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  894. {
  895. if (vil->core_idx == inst_info.core_idx)
  896. inst_info.inst_open_count++;
  897. }
  898. #ifdef SUPPORT_MULTI_INST_INTR
  899. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  900. #endif
  901. spin_unlock(&s_vpu_lock);
  902. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  903. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  904. kfree(vil);
  905. return -EFAULT;
  906. }
  907. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  908. }
  909. break;
  910. case VDI_IOCTL_CLOSE_INSTANCE:
  911. {
  912. vpudrv_inst_info_t inst_info;
  913. vpudrv_instanace_list_t *vil, *n;
  914. u32 found = 0;
  915. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  916. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  917. return -EFAULT;
  918. spin_lock(&s_vpu_lock);
  919. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  920. {
  921. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  922. list_del(&vil->list);
  923. kfree(vil);
  924. found = 1;
  925. break;
  926. }
  927. }
  928. if (0 == found) {
  929. spin_unlock(&s_vpu_lock);
  930. return -EINVAL;
  931. }
  932. inst_info.inst_open_count = 0; /* counting the current open instance number */
  933. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  934. {
  935. if (vil->core_idx == inst_info.core_idx)
  936. inst_info.inst_open_count++;
  937. }
  938. #ifdef SUPPORT_MULTI_INST_INTR
  939. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  940. #endif
  941. spin_unlock(&s_vpu_lock);
  942. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  943. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  944. return -EFAULT;
  945. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  946. }
  947. break;
  948. case VDI_IOCTL_GET_INSTANCE_NUM:
  949. {
  950. vpudrv_inst_info_t inst_info;
  951. vpudrv_instanace_list_t *vil, *n;
  952. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  953. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  954. if (ret != 0)
  955. break;
  956. spin_lock(&s_vpu_lock);
  957. inst_info.inst_open_count = 0;
  958. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  959. {
  960. if (vil->core_idx == inst_info.core_idx)
  961. inst_info.inst_open_count++;
  962. }
  963. spin_unlock(&s_vpu_lock);
  964. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  965. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  966. }
  967. break;
  968. case VDI_IOCTL_RESET:
  969. {
  970. vpu_hw_reset();
  971. }
  972. break;
  973. case VDI_IOCTL_GET_REGISTER_INFO:
  974. {
  975. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  976. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  977. if (ret != 0)
  978. ret = -EFAULT;
  979. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  980. }
  981. break;
  982. case VDI_IOCTL_FLUSH_DCACHE:
  983. {
  984. vpudrv_flush_cache_t cache_info;
  985. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  986. if (ret != 0)
  987. ret = -EFAULT;
  988. if(cache_info.flag)
  989. starfive_flush_dcache(cache_info.start,cache_info.size);
  990. break;
  991. }
  992. default:
  993. {
  994. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  995. }
  996. break;
  997. }
  998. return ret;
  999. }
  1000. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  1001. {
  1002. return -1;
  1003. }
  1004. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  1005. {
  1006. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  1007. if (!buf) {
  1008. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  1009. return -EFAULT;
  1010. }
  1011. if (len == sizeof(vpu_bit_firmware_info_t)) {
  1012. vpu_bit_firmware_info_t *bit_firmware_info;
  1013. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  1014. if (!bit_firmware_info) {
  1015. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  1016. return -EFAULT;
  1017. }
  1018. if (copy_from_user(bit_firmware_info, buf, len)) {
  1019. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1020. return -EFAULT;
  1021. }
  1022. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1023. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1024. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1025. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1026. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1027. return -ENODEV;
  1028. }
  1029. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1030. kfree(bit_firmware_info);
  1031. return len;
  1032. }
  1033. kfree(bit_firmware_info);
  1034. }
  1035. return -1;
  1036. }
  1037. static int vpu_release(struct inode *inode, struct file *filp)
  1038. {
  1039. int ret = 0;
  1040. u32 open_count;
  1041. #ifdef SUPPORT_MULTI_INST_INTR
  1042. int i;
  1043. #endif
  1044. DPRINTK("[VPUDRV] vpu_release\n");
  1045. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1046. /* found and free the not handled buffer by user applications */
  1047. vpu_free_buffers(filp);
  1048. /* found and free the not closed instance by user applications */
  1049. vpu_free_instances(filp);
  1050. spin_lock(&s_vpu_lock);
  1051. s_vpu_drv_context.open_count--;
  1052. open_count = s_vpu_drv_context.open_count;
  1053. spin_unlock(&s_vpu_lock);
  1054. if (open_count == 0) {
  1055. #ifdef SUPPORT_MULTI_INST_INTR
  1056. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1057. kfifo_reset(&s_interrupt_pending_q[i]);
  1058. }
  1059. #endif
  1060. if (s_instance_pool.base) {
  1061. DPRINTK("[VPUDRV] free instance pool\n");
  1062. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1063. vfree((const void *)s_instance_pool.base);
  1064. #else
  1065. vpu_free_dma_buffer(&s_instance_pool);
  1066. #endif
  1067. s_instance_pool.base = 0;
  1068. }
  1069. }
  1070. }
  1071. up(&s_vpu_sem);
  1072. vpu_hw_reset();
  1073. return 0;
  1074. }
  1075. static int vpu_fasync(int fd, struct file *filp, int mode)
  1076. {
  1077. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1078. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1079. }
  1080. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1081. {
  1082. unsigned long pfn;
  1083. vm->vm_flags |= VM_IO | VM_RESERVED;
  1084. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1085. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1086. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1087. }
  1088. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1089. {
  1090. vm->vm_flags |= VM_IO | VM_RESERVED;
  1091. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1092. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1093. }
  1094. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1095. {
  1096. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1097. int ret;
  1098. long length = vm->vm_end - vm->vm_start;
  1099. unsigned long start = vm->vm_start;
  1100. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1101. unsigned long pfn;
  1102. vm->vm_flags |= VM_RESERVED;
  1103. /* loop over all pages, map it page individually */
  1104. while (length > 0)
  1105. {
  1106. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1107. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1108. return ret;
  1109. }
  1110. start += PAGE_SIZE;
  1111. vmalloc_area_ptr += PAGE_SIZE;
  1112. length -= PAGE_SIZE;
  1113. }
  1114. return 0;
  1115. #else
  1116. vm->vm_flags |= VM_RESERVED;
  1117. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1118. #endif
  1119. }
  1120. /*!
  1121. * @brief memory map interface for vpu file operation
  1122. * @return 0 on success or negative error code on error
  1123. */
  1124. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1125. {
  1126. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1127. if (vm->vm_pgoff == 0)
  1128. return vpu_map_to_instance_pool_memory(fp, vm);
  1129. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1130. return vpu_map_to_register(fp, vm);
  1131. return vpu_map_to_physical_memory(fp, vm);
  1132. #else
  1133. if (vm->vm_pgoff) {
  1134. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1135. return vpu_map_to_instance_pool_memory(fp, vm);
  1136. return vpu_map_to_physical_memory(fp, vm);
  1137. } else {
  1138. return vpu_map_to_register(fp, vm);
  1139. }
  1140. #endif
  1141. }
  1142. struct file_operations vpu_fops = {
  1143. .owner = THIS_MODULE,
  1144. .open = vpu_open,
  1145. .read = vpu_read,
  1146. .write = vpu_write,
  1147. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1148. .unlocked_ioctl = vpu_ioctl,
  1149. .release = vpu_release,
  1150. .fasync = vpu_fasync,
  1151. .mmap = vpu_mmap,
  1152. };
  1153. static int vpu_probe(struct platform_device *pdev)
  1154. {
  1155. int err = 0;
  1156. struct resource *res = NULL;
  1157. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1158. struct resource res_cma;
  1159. struct device_node *node;
  1160. #endif
  1161. DPRINTK("[VPUDRV] vpu_probe\n");
  1162. if(pdev){
  1163. vpu_dev = &pdev->dev;
  1164. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1165. //vpu_dev->dma_ops = NULL;
  1166. dev_info(vpu_dev,"device init.\n");
  1167. }
  1168. if (pdev)
  1169. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1170. if (res) {/* if platform driver is implemented */
  1171. s_vpu_register.phys_addr = res->start;
  1172. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1173. s_vpu_register.size = res->end - res->start;
  1174. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1175. } else {
  1176. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1177. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1178. s_vpu_register.size = VPU_REG_SIZE;
  1179. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1180. }
  1181. /* get the major number of the character device */
  1182. if ((alloc_chrdev_region(&s_vpu_major, 0, 1, VPU_DEV_NAME)) < 0) {
  1183. err = -EBUSY;
  1184. printk(KERN_ERR "could not allocate major number\n");
  1185. goto ERROR_PROVE_DEVICE;
  1186. }
  1187. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1188. /* initialize the device structure and register the device with the kernel */
  1189. cdev_init(&s_vpu_cdev, &vpu_fops);
  1190. if ((cdev_add(&s_vpu_cdev, s_vpu_major, 1)) < 0) {
  1191. err = -EBUSY;
  1192. printk(KERN_ERR "could not allocate chrdev\n");
  1193. goto ERROR_PROVE_DEVICE;
  1194. }
  1195. if (pdev)
  1196. s_vpu_clk = vpu_clk_get(pdev);
  1197. else
  1198. s_vpu_clk = vpu_clk_get(NULL);
  1199. if (!s_vpu_clk)
  1200. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1201. else
  1202. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1203. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1204. #else
  1205. vpu_clk_enable(s_vpu_clk);
  1206. #endif
  1207. #ifdef VPU_SUPPORT_ISR
  1208. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1209. if (pdev)
  1210. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1211. if (res) {/* if platform driver is implemented */
  1212. s_vpu_irq = res->start;
  1213. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1214. } else {
  1215. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1216. }
  1217. #else
  1218. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1219. #endif
  1220. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1221. if (err) {
  1222. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1223. goto ERROR_PROVE_DEVICE;
  1224. }
  1225. #endif
  1226. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1227. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1228. if(node){
  1229. dev_info(vpu_dev, "Get mem form memory-region\n");
  1230. of_address_to_resource(node, 0, &res_cma);
  1231. s_video_memory.size = resource_size(&res_cma);
  1232. s_video_memory.phys_addr = res_cma.start;
  1233. }else{
  1234. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1235. return 0;
  1236. }
  1237. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1238. if (!s_video_memory.base) {
  1239. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1240. goto ERROR_PROVE_DEVICE;
  1241. }
  1242. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1243. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1244. goto ERROR_PROVE_DEVICE;
  1245. }
  1246. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1247. #else
  1248. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1249. #endif
  1250. return 0;
  1251. ERROR_PROVE_DEVICE:
  1252. if (s_vpu_major)
  1253. unregister_chrdev_region(s_vpu_major, 1);
  1254. if (s_vpu_register.virt_addr)
  1255. iounmap((void *)s_vpu_register.virt_addr);
  1256. return err;
  1257. }
  1258. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1259. static int vpu_remove(struct platform_device *pdev)
  1260. {
  1261. DPRINTK("[VPUDRV] vpu_remove\n");
  1262. if (s_instance_pool.base) {
  1263. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1264. vfree((const void *)s_instance_pool.base);
  1265. #else
  1266. vpu_free_dma_buffer(&s_instance_pool);
  1267. #endif
  1268. s_instance_pool.base = 0;
  1269. }
  1270. if (s_common_memory.base) {
  1271. vpu_free_dma_buffer(&s_common_memory);
  1272. s_common_memory.base = 0;
  1273. }
  1274. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1275. if (s_video_memory.base) {
  1276. iounmap((void *)s_video_memory.base);
  1277. s_video_memory.base = 0;
  1278. vmem_exit(&s_vmem);
  1279. }
  1280. #endif
  1281. if (s_vpu_major > 0) {
  1282. cdev_del(&s_vpu_cdev);
  1283. unregister_chrdev_region(s_vpu_major, 1);
  1284. s_vpu_major = 0;
  1285. }
  1286. #ifdef VPU_SUPPORT_ISR
  1287. if (s_vpu_irq)
  1288. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1289. #endif
  1290. if (s_vpu_register.virt_addr)
  1291. iounmap((void *)s_vpu_register.virt_addr);
  1292. vpu_clk_disable(s_vpu_clk);
  1293. vpu_clk_put(s_vpu_clk);
  1294. return 0;
  1295. }
  1296. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1297. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1298. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1299. #define W5_CMD_INIT_VPU (0x0001)
  1300. #define W5_CMD_SLEEP_VPU (0x0004)
  1301. #define W5_CMD_WAKEUP_VPU (0x0002)
  1302. static void Wave5BitIssueCommand(int core, u32 cmd)
  1303. {
  1304. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1305. WriteVpuRegister(W5_COMMAND, cmd);
  1306. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1307. return;
  1308. }
  1309. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1310. {
  1311. int i;
  1312. int core;
  1313. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1314. int product_code;
  1315. DPRINTK("[VPUDRV] vpu_suspend\n");
  1316. vpu_clk_enable(s_vpu_clk);
  1317. if (s_vpu_open_ref_count > 0) {
  1318. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1319. if (s_bit_firmware_info[core].size == 0)
  1320. continue;
  1321. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1322. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1323. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1324. if (time_after(jiffies, timeout)) {
  1325. DPRINTK("SLEEP_VPU BUSY timeout");
  1326. goto DONE_SUSPEND;
  1327. }
  1328. }
  1329. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1330. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1331. if (time_after(jiffies, timeout)) {
  1332. DPRINTK("SLEEP_VPU BUSY timeout");
  1333. goto DONE_SUSPEND;
  1334. }
  1335. }
  1336. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1337. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1338. goto DONE_SUSPEND;
  1339. }
  1340. }
  1341. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1342. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1343. if (time_after(jiffies, timeout))
  1344. goto DONE_SUSPEND;
  1345. }
  1346. for (i = 0; i < 64; i++)
  1347. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1348. }
  1349. else {
  1350. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1351. goto DONE_SUSPEND;
  1352. }
  1353. }
  1354. }
  1355. vpu_clk_disable(s_vpu_clk);
  1356. return 0;
  1357. DONE_SUSPEND:
  1358. vpu_clk_disable(s_vpu_clk);
  1359. return -EAGAIN;
  1360. }
  1361. static int vpu_resume(struct platform_device *pdev)
  1362. {
  1363. int i;
  1364. int core;
  1365. u32 val;
  1366. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1367. int product_code;
  1368. unsigned long code_base;
  1369. u32 code_size;
  1370. u32 remap_size;
  1371. int regVal;
  1372. u32 hwOption = 0;
  1373. DPRINTK("[VPUDRV] vpu_resume\n");
  1374. vpu_clk_enable(s_vpu_clk);
  1375. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1376. if (s_bit_firmware_info[core].size == 0) {
  1377. continue;
  1378. }
  1379. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1380. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1381. code_base = s_common_memory.phys_addr;
  1382. /* ALIGN TO 4KB */
  1383. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1384. if (code_size < s_bit_firmware_info[core].size*2) {
  1385. goto DONE_WAKEUP;
  1386. }
  1387. regVal = 0;
  1388. WriteVpuRegister(W5_PO_CONF, regVal);
  1389. /* Reset All blocks */
  1390. regVal = 0x7ffffff;
  1391. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1392. /* Waiting reset done */
  1393. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1394. if (time_after(jiffies, timeout))
  1395. goto DONE_WAKEUP;
  1396. }
  1397. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1398. /* remap page size */
  1399. remap_size = (code_size >> 12) & 0x1ff;
  1400. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1401. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1402. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1403. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1404. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1405. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1406. WriteVpuRegister(W5_CODE_PARAM, 0);
  1407. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1408. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1409. /* Interrupt */
  1410. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1411. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1412. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1413. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1414. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1415. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1416. }
  1417. else {
  1418. // decoder
  1419. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1420. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1421. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1422. }
  1423. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1424. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1425. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1426. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1427. if (time_after(jiffies, timeout))
  1428. goto DONE_WAKEUP;
  1429. }
  1430. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1431. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1432. goto DONE_WAKEUP;
  1433. }
  1434. }
  1435. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1436. WriteVpuRegister(BIT_CODE_RUN, 0);
  1437. /*---- LOAD BOOT CODE*/
  1438. for (i = 0; i < 512; i++) {
  1439. val = s_bit_firmware_info[core].bit_code[i];
  1440. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1441. }
  1442. for (i = 0 ; i < 64 ; i++)
  1443. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1444. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1445. WriteVpuRegister(BIT_CODE_RESET, 1);
  1446. WriteVpuRegister(BIT_CODE_RUN, 1);
  1447. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1448. if (time_after(jiffies, timeout))
  1449. goto DONE_WAKEUP;
  1450. }
  1451. }
  1452. else {
  1453. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1454. goto DONE_WAKEUP;
  1455. }
  1456. }
  1457. if (s_vpu_open_ref_count == 0)
  1458. vpu_clk_disable(s_vpu_clk);
  1459. DONE_WAKEUP:
  1460. if (s_vpu_open_ref_count > 0)
  1461. vpu_clk_enable(s_vpu_clk);
  1462. return 0;
  1463. }
  1464. #else
  1465. #define vpu_suspend NULL
  1466. #define vpu_resume NULL
  1467. #endif /* !CONFIG_PM */
  1468. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1469. static const struct of_device_id cm_vpu_match[] = {
  1470. {
  1471. .compatible = "c&m,cm511-vpu",
  1472. },
  1473. {
  1474. .compatible = "starfive,vdec",
  1475. },
  1476. {
  1477. /* end of table */
  1478. },
  1479. };
  1480. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1481. static struct platform_driver vpu_driver = {
  1482. .driver = {
  1483. .name = VPU_PLATFORM_DEVICE_NAME,
  1484. .of_match_table = cm_vpu_match,
  1485. },
  1486. .probe = vpu_probe,
  1487. .remove = vpu_remove,
  1488. .suspend = vpu_suspend,
  1489. .resume = vpu_resume,
  1490. };
  1491. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1492. static int __init vpu_init(void)
  1493. {
  1494. int res;
  1495. #ifdef SUPPORT_MULTI_INST_INTR
  1496. int i;
  1497. #endif
  1498. DPRINTK("[VPUDRV] begin vpu_init\n");
  1499. #ifdef SUPPORT_MULTI_INST_INTR
  1500. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1501. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1502. }
  1503. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1504. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1505. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1506. if (res) {
  1507. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1508. }
  1509. }
  1510. #else
  1511. init_waitqueue_head(&s_interrupt_wait_q);
  1512. #endif
  1513. s_common_memory.base = 0;
  1514. s_instance_pool.base = 0;
  1515. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1516. res = platform_driver_register(&vpu_driver);
  1517. #else
  1518. res = vpu_probe(NULL);
  1519. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1520. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1521. return res;
  1522. }
  1523. static void __exit vpu_exit(void)
  1524. {
  1525. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1526. DPRINTK("[VPUDRV] vpu_exit\n");
  1527. platform_driver_unregister(&vpu_driver);
  1528. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1529. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1530. #else
  1531. vpu_clk_disable(s_vpu_clk);
  1532. #endif
  1533. vpu_clk_put(s_vpu_clk);
  1534. if (s_instance_pool.base) {
  1535. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1536. vfree((const void *)s_instance_pool.base);
  1537. #else
  1538. vpu_free_dma_buffer(&s_instance_pool);
  1539. #endif
  1540. s_instance_pool.base = 0;
  1541. }
  1542. if (s_common_memory.base) {
  1543. vpu_free_dma_buffer(&s_common_memory);
  1544. s_common_memory.base = 0;
  1545. }
  1546. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1547. if (s_video_memory.base) {
  1548. iounmap((void *)s_video_memory.base);
  1549. s_video_memory.base = 0;
  1550. vmem_exit(&s_vmem);
  1551. }
  1552. #endif
  1553. if (s_vpu_major > 0) {
  1554. cdev_del(&s_vpu_cdev);
  1555. unregister_chrdev_region(s_vpu_major, 1);
  1556. s_vpu_major = 0;
  1557. }
  1558. #ifdef VPU_SUPPORT_ISR
  1559. if (s_vpu_irq)
  1560. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1561. #endif
  1562. #ifdef SUPPORT_MULTI_INST_INTR
  1563. {
  1564. int i;
  1565. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1566. kfifo_free(&s_interrupt_pending_q[i]);
  1567. }
  1568. }
  1569. #endif
  1570. if (s_vpu_register.virt_addr) {
  1571. iounmap((void *)s_vpu_register.virt_addr);
  1572. s_vpu_register.virt_addr = 0x00;
  1573. }
  1574. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1575. return;
  1576. }
  1577. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1578. MODULE_DESCRIPTION("VPU linux driver");
  1579. MODULE_LICENSE("GPL");
  1580. module_init(vpu_init);
  1581. module_exit(vpu_exit);
  1582. static int vpu_pmu_enable(struct device *dev)
  1583. {
  1584. int ret;
  1585. pm_runtime_enable(dev);
  1586. ret = pm_runtime_get_sync(dev);
  1587. if (ret < 0)
  1588. dev_err(dev, "failed to get pm runtime: %d\n", ret);
  1589. return ret;
  1590. }
  1591. static void vpu_pmu_disable(struct device *dev)
  1592. {
  1593. pm_runtime_put_sync(dev);
  1594. pm_runtime_disable(dev);
  1595. }
  1596. /* clk&reset for starfive jh7110*/
  1597. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1598. #define CLK_ENABLE_DATA 1
  1599. #define CLK_DISABLE_DATA 0
  1600. #define CLK_EN_SHIFT 31
  1601. #define CLK_EN_MASK 0x80000000U
  1602. #define SAIF_BD_APBS_BASE 0x13020000
  1603. #define WAVE511_CLK_AXI_CTRL 0x118U
  1604. #define WAVE511_CLK_BPU_CTRL 0x11cU
  1605. #define WAVE511_CLK_VCE_CTRL 0x120U
  1606. #define WAVE511_CLK_APB_CTRL 0x124U
  1607. #define WAVE511_CLK_NOCBUS_CTRL 0x130U
  1608. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1609. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1610. #define RSTN_AXI_MASK (0x1 << 15)
  1611. #define RSTN_BPU_MASK (0x1 << 16)
  1612. #define RSTN_VCE_MASK (0x1 << 17)
  1613. #define RSTN_APB_MASK (0x1 << 18)
  1614. #define RSTN_128B_AXIMEM_MASK (0x1 << 21)
  1615. static uint32_t saif_get_reg(const volatile void __iomem *addr,
  1616. uint32_t shift, uint32_t mask)
  1617. {
  1618. u32 tmp;
  1619. tmp = readl(addr);
  1620. tmp = (tmp & mask) >> shift;
  1621. return tmp;
  1622. }
  1623. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1624. uint32_t shift, uint32_t mask)
  1625. {
  1626. uint32_t tmp;
  1627. tmp = readl(addr);
  1628. tmp &= ~mask;
  1629. tmp |= (data << shift) & mask;
  1630. writel(tmp, addr);
  1631. }
  1632. static void saif_assert_rst(volatile void __iomem *addr,
  1633. const volatile void __iomem *addr_status, uint32_t mask)
  1634. {
  1635. uint32_t tmp;
  1636. tmp = readl(addr);
  1637. tmp |= mask;
  1638. writel(tmp, addr);
  1639. do {
  1640. tmp = readl(addr_status);
  1641. } while ((tmp & mask) != 0);
  1642. }
  1643. static void saif_clear_rst(volatile void __iomem *addr,
  1644. const volatile void __iomem *addr_status, uint32_t mask)
  1645. {
  1646. uint32_t tmp;
  1647. tmp = readl(addr);
  1648. tmp &= ~mask;
  1649. writel(tmp, addr);
  1650. do {
  1651. tmp = readl(addr_status);
  1652. } while ((tmp & mask) != mask);
  1653. }
  1654. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1655. {
  1656. if (enable)
  1657. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1658. else
  1659. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1660. }
  1661. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1662. {
  1663. if (enable) {
  1664. /*enable*/
  1665. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1666. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1667. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1668. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1669. /*clr-reset*/
  1670. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1671. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1672. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1673. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1674. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1675. } else {
  1676. /*assert-reset*/
  1677. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1678. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1679. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1680. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1681. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1682. /*disable*/
  1683. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1684. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1685. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1686. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1687. }
  1688. }
  1689. static void vpu_clk_reset(vpu_clk_t *clk)
  1690. {
  1691. /*assert-reset*/
  1692. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1693. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1694. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1695. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1696. /*clr-reset*/
  1697. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1698. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1699. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1700. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1701. }
  1702. int vpu_hw_reset(void)
  1703. {
  1704. if (!s_vpu_clk)
  1705. return -1;
  1706. vpu_clk_reset(s_vpu_clk);
  1707. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1708. return 0;
  1709. }
  1710. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1711. {
  1712. if (!pdev)
  1713. return -ENXIO;
  1714. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1715. if (IS_ERR(vpu_clk->clkgen)) {
  1716. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1717. return PTR_ERR(vpu_clk->clkgen);
  1718. }
  1719. /* clkgen define */
  1720. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
  1721. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
  1722. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
  1723. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
  1724. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
  1725. vpu_clk->en_mask = CLK_EN_MASK;
  1726. vpu_clk->en_shift = CLK_EN_SHIFT;
  1727. /* rstgen define */
  1728. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1729. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1730. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1731. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1732. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1733. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1734. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1735. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
  1736. vpu_clk->noc_ctrl = true;
  1737. return 0;
  1738. }
  1739. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1740. {
  1741. vpu_clk_t *vpu_clk;
  1742. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1743. if (!vpu_clk)
  1744. return NULL;
  1745. if (vpu_of_clk_get(pdev, vpu_clk))
  1746. goto err_get_clk;
  1747. return vpu_clk;
  1748. err_get_clk:
  1749. devm_kfree(&pdev->dev, vpu_clk);
  1750. return NULL;
  1751. }
  1752. static void vpu_clk_put(vpu_clk_t *clk)
  1753. {
  1754. if (clk->clkgen) {
  1755. iounmap(clk->clkgen);
  1756. clk->clkgen = NULL;
  1757. }
  1758. }
  1759. static int vpu_clk_enable(vpu_clk_t *clk)
  1760. {
  1761. if (clk == NULL || IS_ERR(clk))
  1762. return -1;
  1763. vpu_pmu_enable(clk->dev);
  1764. vpu_clk_control(clk, true);
  1765. if (clk->noc_ctrl == true)
  1766. vpu_noc_vdec_bus_control(clk, true);
  1767. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1768. return 0;
  1769. }
  1770. static void vpu_clk_disable(vpu_clk_t *clk)
  1771. {
  1772. if (clk == NULL || IS_ERR(clk))
  1773. return;
  1774. vpu_clk_control(clk, false);
  1775. vpu_pmu_disable(clk->dev);
  1776. if (clk->noc_ctrl == true)
  1777. vpu_noc_vdec_bus_control(clk, false);
  1778. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1779. }
  1780. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1781. int vpu_hw_reset(void)
  1782. {
  1783. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1784. /* sram do not need reset */
  1785. return reset_control_reset(s_vpu_clk->resets);
  1786. }
  1787. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1788. {
  1789. struct device *dev = &pdev->dev;
  1790. int ret;
  1791. vpu_clk->dev = dev;
  1792. vpu_clk->clks = vpu_clks;
  1793. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  1794. vpu_clk->resets = devm_reset_control_array_get_exclusive(dev);
  1795. if (IS_ERR(vpu_clk->resets)) {
  1796. ret = PTR_ERR(vpu_clk->resets);
  1797. dev_err(dev, "faied to get vpu reset controls\n");
  1798. }
  1799. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  1800. if (ret)
  1801. dev_err(dev, "faied to get vpu clk controls\n");
  1802. if (device_property_read_bool(dev, "starfive,vdec_noc_ctrl"))
  1803. vpu_clk->noc_ctrl = true;
  1804. return 0;
  1805. }
  1806. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1807. {
  1808. vpu_clk_t *vpu_clk;
  1809. if (!pdev)
  1810. return NULL;
  1811. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1812. if (!vpu_clk)
  1813. return NULL;
  1814. if (vpu_of_clk_get(pdev, vpu_clk))
  1815. goto err_of_clk_get;
  1816. return vpu_clk;
  1817. err_of_clk_get:
  1818. devm_kfree(&pdev->dev, vpu_clk);
  1819. return NULL;
  1820. }
  1821. static void vpu_clk_put(vpu_clk_t *clk)
  1822. {
  1823. clk_bulk_put(clk->nr_clks, clk->clks);
  1824. }
  1825. static int vpu_clk_enable(vpu_clk_t *clk)
  1826. {
  1827. int ret;
  1828. vpu_pmu_enable(clk->dev);
  1829. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1830. if (ret)
  1831. dev_err(clk->dev, "enable clk error.\n");
  1832. ret = reset_control_deassert(clk->resets);
  1833. if (ret)
  1834. dev_err(clk->dev, "deassert vpu error.\n");
  1835. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1836. return ret;
  1837. }
  1838. static void vpu_clk_disable(vpu_clk_t *clk)
  1839. {
  1840. int ret;
  1841. ret = reset_control_assert(clk->resets);
  1842. if (ret)
  1843. dev_err(clk->dev, "assert vpu error.\n");
  1844. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  1845. vpu_pmu_disable(clk->dev);
  1846. }
  1847. #endif