common.c 46 KB

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  1. #include "product.h"
  2. #include "wave/common/common.h"
  3. #include "wave/common/common_vpuconfig.h"
  4. #include "vpuerror.h"
  5. #include "wave/common/common_regdefine.h"
  6. #define COMMAND_TIMEOUT 0xffff
  7. void Wave4BitIssueCommand(CodecInst* instance, Uint32 cmd)
  8. {
  9. Uint32 instanceIndex = 0;
  10. Uint32 codecMode = 0;
  11. Uint32 coreIdx;
  12. if (instance != NULL) {
  13. instanceIndex = instance->instIndex;
  14. codecMode = instance->codecMode;
  15. }
  16. coreIdx = instance->coreIdx;
  17. VpuWriteReg(coreIdx, W4_VPU_BUSY_STATUS, 1);
  18. VpuWriteReg(coreIdx, W4_RET_SUCCESS, 0); //for debug
  19. VpuWriteReg(coreIdx, W4_CORE_INDEX, 0);
  20. if (instance->productId == PRODUCT_ID_7Q) // only coda7q use codecModeAux for DIV
  21. VpuWriteReg(coreIdx, W4_INST_INDEX, (instanceIndex&0xffff)|(codecMode<<16) | (instance->codecModeAux<<24));
  22. else
  23. VpuWriteReg(coreIdx, W4_INST_INDEX, (instanceIndex&0xffff)|(codecMode<<16));
  24. VpuWriteReg(coreIdx, W4_COMMAND, cmd);
  25. if ((instance != NULL && instance->loggingEnable))
  26. vdi_log(coreIdx, cmd, 1);
  27. if (cmd != INIT_VPU) {
  28. VpuWriteReg(coreIdx, W4_VPU_HOST_INT_REQ, 1);
  29. }
  30. return;
  31. }
  32. static RetCode SetupWave4Properties(
  33. Uint32 coreIdx
  34. )
  35. {
  36. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  37. Uint32 regVal;
  38. Uint8* str;
  39. CodecInst hdr;
  40. /* GET FIRMWARE&HARDWARE INFORMATION */
  41. hdr.coreIdx = 0;
  42. hdr.instIndex = 0;
  43. hdr.loggingEnable = 0;
  44. Wave4BitIssueCommand((CodecInst*)&hdr, GET_FW_VERSION);
  45. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  46. return RETCODE_VPU_RESPONSE_TIMEOUT;
  47. }
  48. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  49. if (regVal == 0) {
  50. return RETCODE_FAILURE;
  51. }
  52. regVal = VpuReadReg(coreIdx, W4_RET_PRODUCT_NAME);
  53. str = (Uint8*)&regVal;
  54. pAttr->productName[0] = str[3];
  55. pAttr->productName[1] = str[2];
  56. pAttr->productName[2] = str[1];
  57. pAttr->productName[3] = str[0];
  58. pAttr->productName[4] = 0;
  59. pAttr->productNumber = VpuReadReg(coreIdx, W4_RET_PRODUCT_VERSION);
  60. switch (pAttr->productNumber) {
  61. case WAVE410_CODE: pAttr->productId = PRODUCT_ID_410; break;
  62. case WAVE4102_CODE: pAttr->productId = PRODUCT_ID_4102; break;
  63. case WAVE420_CODE: pAttr->productId = PRODUCT_ID_420; break;
  64. case WAVE412_CODE: pAttr->productId = PRODUCT_ID_412; break;
  65. case CODA7Q_CODE: pAttr->productId = PRODUCT_ID_7Q; break;
  66. case WAVE420L_CODE: pAttr->productId = PRODUCT_ID_420L; break;
  67. case WAVE510_CODE: pAttr->productId = PRODUCT_ID_510; break;
  68. case WAVE512_CODE: pAttr->productId = PRODUCT_ID_412; break;
  69. case WAVE515_CODE: pAttr->productId = PRODUCT_ID_515; break;
  70. default: pAttr->productId = PRODUCT_ID_NONE; break;
  71. }
  72. pAttr->hwConfigDef0 = VpuReadReg(coreIdx, W4_RET_STD_DEF0);
  73. pAttr->hwConfigDef1 = VpuReadReg(coreIdx, W4_RET_STD_DEF1);
  74. pAttr->hwConfigFeature = VpuReadReg(coreIdx, W4_RET_CONF_FEATURE);
  75. pAttr->hwConfigDate = VpuReadReg(coreIdx, W4_RET_CONFIG_DATE);
  76. pAttr->hwConfigRev = VpuReadReg(coreIdx, W4_RET_CONFIG_REVISION);
  77. pAttr->hwConfigType = VpuReadReg(coreIdx, W4_RET_CONFIG_TYPE);
  78. pAttr->supportGDIHW = TRUE;
  79. if (pAttr->productId == PRODUCT_ID_420L) {
  80. pAttr->supportDecoders = (1<<STD_HEVC);
  81. pAttr->supportEncoders = (1<<STD_HEVC);
  82. pAttr->supportGDIHW = FALSE;
  83. }
  84. else if (pAttr->productId == PRODUCT_ID_420) {
  85. pAttr->supportDecoders = (1<<STD_HEVC);
  86. pAttr->supportEncoders = (1<<STD_HEVC);
  87. }
  88. else if (pAttr->productId == PRODUCT_ID_412) {
  89. pAttr->supportDecoders = (1<<STD_HEVC);
  90. pAttr->supportDecoders |= (1<<STD_VP9);;
  91. pAttr->supportEncoders = (1<<STD_VP9);
  92. }
  93. else if (pAttr->productId == PRODUCT_ID_515) {
  94. pAttr->supportDecoders = (1<<STD_HEVC);
  95. pAttr->supportDecoders |= (1<<STD_VP9);
  96. pAttr->supportDecoders |= (1<<STD_AVS2);
  97. pAttr->supportEncoders = (1<<STD_VP9);
  98. }
  99. else if (pAttr->productId == PRODUCT_ID_7Q) {
  100. pAttr->supportDecoders = (1<<STD_AVC) |
  101. (1<<STD_VC1) |
  102. (1<<STD_MPEG2) |
  103. (1<<STD_MPEG4) |
  104. (1<<STD_H263) |
  105. (1<<STD_AVS) |
  106. (1<<STD_DIV3) |
  107. (1<<STD_RV) |
  108. (1<<STD_THO) |
  109. (1<<STD_VP8) |
  110. (1<<STD_HEVC);
  111. pAttr->supportEncoders = (1<<STD_AVC) | (1<<STD_MPEG4) | (1<<STD_H263);
  112. }
  113. else {
  114. // Wave410
  115. pAttr->supportDecoders = (1<<STD_HEVC);
  116. pAttr->supportEncoders = 0;
  117. }
  118. pAttr->supportFBCBWOptimization = (BOOL)((pAttr->hwConfigDef1>>15)&0x01);
  119. pAttr->supportWTL = TRUE;
  120. pAttr->supportTiled2Linear = FALSE;
  121. pAttr->supportMapTypes = FALSE;
  122. pAttr->support128bitBus = TRUE;
  123. pAttr->supportThumbnailMode = TRUE;
  124. pAttr->supportEndianMask = (Uint32)((1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN) | (0xffff<<16));
  125. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  126. pAttr->framebufferCacheType = FramebufCacheNone;
  127. pAttr->bitstreamBufferMargin = (pAttr->productId == PRODUCT_ID_7Q) ? 1024 : 0;
  128. pAttr->numberOfVCores = MAX_NUM_VCORE;
  129. pAttr->numberOfMemProtectRgns = 10;
  130. return RETCODE_SUCCESS;
  131. }
  132. Int32 WaveVpuGetProductId(Uint32 coreIdx)
  133. {
  134. Uint32 productId = PRODUCT_ID_NONE;
  135. Uint32 val;
  136. if (coreIdx >= MAX_NUM_VPU_CORE)
  137. return PRODUCT_ID_NONE;
  138. val = VpuReadReg(coreIdx, W4_PRODUCT_NUMBER);
  139. switch (val) {
  140. case WAVE410_CODE: productId = PRODUCT_ID_410; break;
  141. case WAVE4102_CODE: productId = PRODUCT_ID_4102; break;
  142. case WAVE420_CODE: productId = PRODUCT_ID_420; break;
  143. case WAVE412_CODE: productId = PRODUCT_ID_412; break;
  144. case CODA7Q_CODE: productId = PRODUCT_ID_7Q; break;
  145. case WAVE420L_CODE: productId = PRODUCT_ID_420L; break;
  146. case WAVE510_CODE: productId = PRODUCT_ID_510; break;
  147. case WAVE512_CODE: productId = PRODUCT_ID_512; break;
  148. case WAVE515_CODE: productId = PRODUCT_ID_515; break;
  149. case WAVE520_CODE: productId = PRODUCT_ID_520; break;
  150. default:
  151. VLOG(ERR, "Check productId(%d)\n", val);
  152. break;
  153. }
  154. return productId;
  155. }
  156. RetCode Wave4VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  157. {
  158. Uint32 regVal;
  159. CodecInstHeader hdr = {0};
  160. /* GET FIRMWARE&HARDWARE INFORMATION */
  161. hdr.coreIdx = 0;
  162. hdr.instIndex = 0;
  163. hdr.loggingEnable = 0;
  164. Wave4BitIssueCommand((CodecInst*)&hdr, GET_FW_VERSION);
  165. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  166. return RETCODE_VPU_RESPONSE_TIMEOUT;
  167. }
  168. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  169. if (regVal == 0)
  170. return RETCODE_FAILURE;
  171. regVal = VpuReadReg(coreIdx, W4_RET_FW_VERSION);
  172. if (versionInfo != NULL) {
  173. *versionInfo = 0;
  174. }
  175. if (revision != NULL) {
  176. *revision = regVal;
  177. }
  178. regVal = VpuReadReg(coreIdx,W4_RET_CONFIG_REVISION );
  179. VLOG(INFO, "\nget hw version %d !!!\n", regVal);
  180. return RETCODE_SUCCESS;
  181. }
  182. RetCode Wave4VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  183. {
  184. vpu_buffer_t vb;
  185. PhysicalAddress codeBase;
  186. Uint32 codeSize;
  187. Uint32 i, regVal, remapSize;
  188. Uint32 hwOption = 0;
  189. CodecInstHeader hdr;
  190. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  191. vdi_get_common_memory(coreIdx, &vb);
  192. codeBase = vb.phys_addr;
  193. /* ALIGN TO 4KB */
  194. codeSize = (WAVE4_MAX_CODE_BUF_SIZE&~0xfff);
  195. if (codeSize < size*2) {
  196. return RETCODE_INSUFFICIENT_RESOURCE;
  197. }
  198. VLOG(INFO, "\nVPU INIT Start!!!\n");
  199. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  200. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  201. regVal = 0;
  202. VpuWriteReg(coreIdx, W4_PO_CONF, regVal);
  203. /* Reset All blocks */
  204. regVal = 0x7ffffff;
  205. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, regVal); // Reset All blocks
  206. /* Waiting reset done */
  207. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  208. VLOG(ERR, "VPU init(W4_VPU_RESET_REQ) timeout\n");
  209. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  210. return RETCODE_VPU_RESPONSE_TIMEOUT;
  211. }
  212. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  213. /* clear registers */
  214. for (i=W4_CMD_REG_BASE; i<W4_CMD_REG_END; i+=4)
  215. VpuWriteReg(coreIdx, i, 0x00);
  216. /* remap page size */
  217. remapSize = (codeSize >> 12) &0x1ff;
  218. regVal = 0x80000000 | (0 << 16) | (W4_REMAP_CODE_INDEX<<12) | (1<<11) | remapSize;
  219. VpuWriteReg(coreIdx, W4_VPU_REMAP_CTRL, regVal);
  220. VpuWriteReg(coreIdx, W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  221. VpuWriteReg(coreIdx, W4_VPU_REMAP_PADDR, codeBase);
  222. VpuWriteReg(coreIdx, W4_ADDR_CODE_BASE, codeBase);
  223. VpuWriteReg(coreIdx, W4_CODE_SIZE, codeSize);
  224. VpuWriteReg(coreIdx, W4_CODE_PARAM, 0);
  225. //timeoutTicks = COMMAND_TIMEOUT*VCPU_CLOCK_IN_MHZ*(1000000>>15);
  226. VpuWriteReg(coreIdx, W4_TIMEOUT_CNT, 0xffffffff);
  227. VpuWriteReg(coreIdx, W4_HW_OPTION, hwOption);
  228. /* Interrupt */
  229. // for encoder interrupt
  230. regVal = (1<<W4_INT_ENC_PIC);
  231. regVal |= (1<<W4_INT_SLEEP_VPU);
  232. regVal |= (1<<W4_INT_SET_PARAM);
  233. // for decoder interrupt
  234. regVal |= (1<<W4_INT_DEC_PIC_HDR);
  235. regVal |= (1<<W4_INT_DEC_PIC);
  236. regVal |= (1<<W4_INT_QUERY_DEC);
  237. regVal |= (1<<W4_INT_SLEEP_VPU);
  238. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  239. VpuWriteReg(coreIdx, W4_VPU_VINT_ENABLE, regVal);
  240. hdr.coreIdx = coreIdx;
  241. Wave4BitIssueCommand((CodecInst*)&hdr, INIT_VPU);
  242. VpuWriteReg(coreIdx, W4_VPU_REMAP_CORE_START, 1);
  243. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  244. VLOG(ERR, "VPU init(W4_VPU_REMAP_CORE_START) timeout\n");
  245. return RETCODE_VPU_RESPONSE_TIMEOUT;
  246. }
  247. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  248. if (regVal == 0) {
  249. Uint32 reasonCode = VpuReadReg(coreIdx, W4_RET_FAIL_REASON);
  250. VLOG(ERR, "VPU init(W4_RET_SUCCESS) failed(%d) REASON CODE(%08x)\n", regVal, reasonCode);
  251. return RETCODE_FAILURE;
  252. }
  253. SetupWave4Properties(coreIdx);
  254. return RETCODE_SUCCESS;
  255. }
  256. RetCode Wave4VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  257. {
  258. vpu_buffer_t vb;
  259. PhysicalAddress codeBase;
  260. PhysicalAddress oldCodeBase;
  261. Uint32 codeSize;
  262. Uint32 regVal, remapSize;
  263. CodecInstHeader hdr;
  264. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  265. vdi_get_common_memory(coreIdx, &vb);
  266. codeBase = vb.phys_addr;
  267. /* ALIGN TO 4KB */
  268. codeSize = (WAVE4_MAX_CODE_BUF_SIZE&~0xfff);
  269. if (codeSize < size*2) {
  270. return RETCODE_INSUFFICIENT_RESOURCE;
  271. }
  272. oldCodeBase = VpuReadReg(coreIdx, W4_VPU_REMAP_PADDR);
  273. if (oldCodeBase != codeBase) {
  274. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  275. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  276. regVal = 0;
  277. VpuWriteReg(coreIdx, W4_PO_CONF, regVal);
  278. // Waiting for completion of bus transaction
  279. // Step1 : disable request
  280. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x100); // WAVE410 GDI added new feature: disable_request
  281. // Step2 : Waiting for completion of bus transaction
  282. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_GDI_VCORE0_BUS_STATUS) == -1) {
  283. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  284. vdi_log(coreIdx, RESET_VPU, 2);
  285. return RETCODE_VPU_RESPONSE_TIMEOUT;
  286. }
  287. /* Reset All blocks */
  288. regVal = 0x7ffffff;
  289. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, regVal); // Reset All blocks
  290. /* Waiting reset done */
  291. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  292. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  293. return RETCODE_VPU_RESPONSE_TIMEOUT;
  294. }
  295. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  296. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  297. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  298. /* not needed to clear registers
  299. for (i=W4_CMD_REG_BASE; i<W4_CMD_REG_END; i+=4)
  300. VpuWriteReg(coreIdx, i, 0x00)
  301. */
  302. /* remap page size */
  303. remapSize = (codeSize >> 12) &0x1ff;
  304. regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remapSize;
  305. VpuWriteReg(coreIdx, W4_VPU_REMAP_CTRL, regVal);
  306. VpuWriteReg(coreIdx, W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  307. VpuWriteReg(coreIdx, W4_VPU_REMAP_PADDR, codeBase);
  308. VpuWriteReg(coreIdx, W4_ADDR_CODE_BASE, codeBase);
  309. VpuWriteReg(coreIdx, W4_CODE_SIZE, codeSize);
  310. VpuWriteReg(coreIdx, W4_CODE_PARAM, 0);
  311. VpuWriteReg(coreIdx, W4_TIMEOUT_CNT, COMMAND_TIMEOUT);
  312. VpuWriteReg(coreIdx, W4_HW_OPTION, 0);
  313. /* Interrupt */
  314. // for encoder interrupt
  315. regVal = (1<<W4_INT_ENC_PIC);
  316. regVal |= (1<<W4_INT_SLEEP_VPU);
  317. regVal |= (1<<W4_INT_SET_PARAM);
  318. // for decoder interrupt
  319. regVal |= (1<<W4_INT_DEC_PIC_HDR);
  320. regVal |= (1<<W4_INT_DEC_PIC);
  321. regVal |= (1<<W4_INT_QUERY_DEC);
  322. regVal |= (1<<W4_INT_SLEEP_VPU);
  323. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  324. VpuWriteReg(coreIdx, W4_VPU_VINT_ENABLE, regVal);
  325. hdr.coreIdx = coreIdx;
  326. Wave4BitIssueCommand((CodecInst*)&hdr, INIT_VPU);
  327. VpuWriteReg(coreIdx, W4_VPU_REMAP_CORE_START, 1);
  328. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  329. return RETCODE_VPU_RESPONSE_TIMEOUT;
  330. }
  331. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  332. if (regVal == 0)
  333. return RETCODE_FAILURE;
  334. }
  335. SetupWave4Properties(coreIdx);
  336. return RETCODE_SUCCESS;
  337. }
  338. Uint32 Wave4VpuIsInit(Uint32 coreIdx)
  339. {
  340. Uint32 pc;
  341. pc = (Uint32)VpuReadReg(coreIdx, W4_VCPU_CUR_PC);
  342. return pc;
  343. }
  344. Int32 Wave4VpuIsBusy(Uint32 coreIdx)
  345. {
  346. return VpuReadReg(coreIdx, W4_VPU_BUSY_STATUS);
  347. }
  348. Int32 Wave4VpuWaitInterrupt(CodecInst* handle, Int32 timeout)
  349. {
  350. Int32 reason = -1;
  351. Uint32 coreIdx = handle->coreIdx;
  352. if ((reason=vdi_wait_interrupt(coreIdx, timeout, W4_VPU_VINT_REASON_USR)) > 0) {
  353. /* If you are using device driver that we provide. the below codes are meaningless.
  354. * Because device driver clears interrupt.
  355. */
  356. VpuWriteReg(coreIdx, W4_VPU_VINT_REASON_CLR, reason);
  357. VpuWriteReg(coreIdx, W4_VPU_VINT_CLEAR, 1);
  358. }
  359. return reason;
  360. }
  361. RetCode Wave4VpuClearInterrupt(Uint32 coreIdx, Uint32 flags)
  362. {
  363. Uint32 interruptReason;
  364. interruptReason = VpuReadReg(coreIdx, W4_VPU_VINT_REASON_USR);
  365. interruptReason &= ~flags;
  366. VpuWriteReg(coreIdx, W4_VPU_VINT_REASON_USR, interruptReason);
  367. return RETCODE_SUCCESS;
  368. }
  369. RetCode Wave4VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size)
  370. {
  371. CodecInstHeader hdr;
  372. Uint32 regVal;
  373. vpu_buffer_t vb;
  374. PhysicalAddress codeBase;
  375. Uint32 codeSize;
  376. Uint32 remapSize;
  377. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  378. hdr.coreIdx = coreIdx;
  379. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  380. return RETCODE_VPU_RESPONSE_TIMEOUT;
  381. }
  382. if(iSleepWake==1) //saves
  383. {
  384. Wave4BitIssueCommand((CodecInst*)&hdr, SLEEP_VPU);
  385. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1)
  386. {
  387. return RETCODE_VPU_RESPONSE_TIMEOUT;
  388. }
  389. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  390. if (regVal == 0)
  391. {
  392. APIDPRINT("SLEEP_VPU failed [0x%x]", VpuReadReg(coreIdx, W4_RET_FAIL_REASON));
  393. return RETCODE_FAILURE;
  394. }
  395. }
  396. else //restore
  397. {
  398. Uint32 hwOption = 0;
  399. vdi_get_common_memory(coreIdx, &vb);
  400. codeBase = vb.phys_addr;
  401. /* ALIGN TO 4KB */
  402. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  403. if (codeSize < size*2) {
  404. return RETCODE_INSUFFICIENT_RESOURCE;
  405. }
  406. regVal = 0;
  407. VpuWriteReg(coreIdx, W4_PO_CONF, regVal);
  408. /* SW_RESET_SAFETY */
  409. regVal = W4_RST_BLOCK_ALL;
  410. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, regVal); // Reset All blocks
  411. /* Waiting reset done */
  412. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  413. VLOG(ERR, "VPU Wakeup(W4_VPU_RESET_REQ) timeout\n");
  414. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  415. return RETCODE_VPU_RESPONSE_TIMEOUT;
  416. }
  417. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  418. /* remap page size */
  419. remapSize = (codeSize >> 12) &0x1ff;
  420. regVal = 0x80000000 | (0 << 16) |(W4_REMAP_CODE_INDEX<<12) | (1<<11) | remapSize;
  421. VpuWriteReg(coreIdx, W4_VPU_REMAP_CTRL, regVal);
  422. VpuWriteReg(coreIdx, W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  423. VpuWriteReg(coreIdx, W4_VPU_REMAP_PADDR, codeBase);
  424. VpuWriteReg(coreIdx, W4_ADDR_CODE_BASE, codeBase);
  425. VpuWriteReg(coreIdx, W4_CODE_SIZE, codeSize);
  426. VpuWriteReg(coreIdx, W4_CODE_PARAM, 0);
  427. VpuWriteReg(coreIdx, W4_TIMEOUT_CNT, COMMAND_TIMEOUT);
  428. VpuWriteReg(coreIdx, W4_HW_OPTION, hwOption);
  429. /* Interrupt */
  430. // for encoder interrupt
  431. regVal = (1<<W4_INT_ENC_PIC);
  432. regVal |= (1<<W4_INT_SLEEP_VPU);
  433. regVal |= (1<<W4_INT_SET_PARAM);
  434. // for decoder interrupt
  435. regVal |= (1<<W4_INT_DEC_PIC_HDR);
  436. regVal |= (1<<W4_INT_DEC_PIC);
  437. regVal |= (1<<W4_INT_QUERY_DEC);
  438. regVal |= (1<<W4_INT_SLEEP_VPU);
  439. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  440. VpuWriteReg(coreIdx, W4_VPU_VINT_ENABLE, regVal);
  441. hdr.coreIdx = coreIdx;
  442. VpuWriteReg(coreIdx, W4_VPU_BUSY_STATUS, 1);
  443. VpuWriteReg(coreIdx, W4_RET_SUCCESS, 0); //for debug
  444. VpuWriteReg(coreIdx, W4_CORE_INDEX, 0);
  445. if (hdr.productId == PRODUCT_ID_7Q) // only coda7q use codecModeAux for DIV
  446. VpuWriteReg(coreIdx, W4_INST_INDEX, (hdr.instIndex&0xffff)|(hdr.codecMode<<16) | (hdr.codecModeAux<<24));
  447. else
  448. VpuWriteReg(coreIdx, W4_INST_INDEX, (hdr.instIndex&0xffff)|(hdr.codecMode<<16));
  449. VpuWriteReg(coreIdx, W4_COMMAND, INIT_VPU);
  450. if (hdr.loggingEnable) {
  451. vdi_log(coreIdx, INIT_VPU, 1);
  452. }
  453. VpuWriteReg(coreIdx, W4_VPU_REMAP_CORE_START, 1);
  454. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  455. VLOG(ERR, "VPU Wakeup (W4_VPU_REMAP_CORE_START) timeout\n");
  456. return RETCODE_VPU_RESPONSE_TIMEOUT;
  457. }
  458. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  459. if (regVal == 0) {
  460. Uint32 reasonCode = VpuReadReg(coreIdx, W4_RET_FAIL_REASON);
  461. VLOG(ERR, "VPU Wakeup(W4_RET_SUCCESS) failed(%d) REASON CODE(%08x)\n", regVal, reasonCode);
  462. return RETCODE_FAILURE;
  463. }
  464. }
  465. return RETCODE_SUCCESS;
  466. }
  467. RetCode Wave4VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  468. {
  469. Uint32 val = 0;
  470. RetCode ret = RETCODE_FAILURE;
  471. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  472. // VPU doesn't send response. Force to set BUSY flag to 0.
  473. VpuWriteReg(coreIdx, W4_VPU_BUSY_STATUS, 0);
  474. if (pAttr->supportGDIHW == TRUE) {
  475. // Waiting for completion of bus transaction
  476. // Step1 : disable request
  477. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x100); // WAVE410 GDI added new feature: disable_request
  478. // Step2 : Waiting for completion of bus transaction
  479. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_GDI_VCORE0_BUS_STATUS) == -1) {
  480. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  481. vdi_log(coreIdx, RESET_VPU, 2);
  482. return RETCODE_VPU_RESPONSE_TIMEOUT;
  483. }
  484. }
  485. else {
  486. if (pAttr->productId == PRODUCT_ID_420L) {
  487. val = vdi_fio_read_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL);
  488. if ((val>>24) == 0x01) {
  489. /* VPU has a bus transaction controller */
  490. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x11);
  491. }
  492. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_GDI_VCORE0_BUS_STATUS) == -1) {
  493. vdi_log(coreIdx, RESET_VPU, 2);
  494. return RETCODE_VPU_RESPONSE_TIMEOUT;
  495. }
  496. }
  497. }
  498. if (resetMode == SW_RESET_SAFETY) {
  499. if ((ret=Wave4VpuSleepWake(coreIdx, TRUE, NULL, 0)) != RETCODE_SUCCESS) {
  500. return ret;
  501. }
  502. }
  503. switch (resetMode) {
  504. case SW_RESET_ON_BOOT:
  505. case SW_RESET_FORCE:
  506. val = W4_RST_BLOCK_ALL;
  507. break;
  508. case SW_RESET_SAFETY:
  509. val = W4_RST_BLOCK_ACLK_ALL | W4_RST_BLOCK_BCLK_ALL | W4_RST_BLOCK_CCLK_ALL;
  510. break;
  511. default:
  512. return RETCODE_INVALID_PARAM;
  513. }
  514. if (val) {
  515. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, val);
  516. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  517. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  518. vdi_log(coreIdx, RESET_VPU, 2);
  519. return RETCODE_VPU_RESPONSE_TIMEOUT;
  520. }
  521. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  522. }
  523. if (pAttr->supportGDIHW == TRUE) {
  524. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  525. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  526. }
  527. else {
  528. if (pAttr->productId == PRODUCT_ID_420L) {
  529. val = vdi_fio_read_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL);
  530. if ((val>>24) == 0x01) {
  531. /* VPU has a bus transaction controller */
  532. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0);
  533. }
  534. }
  535. }
  536. if (resetMode == SW_RESET_SAFETY || resetMode == SW_RESET_FORCE) {
  537. ret = Wave4VpuSleepWake(coreIdx, FALSE, NULL, 0);
  538. }
  539. return RETCODE_SUCCESS;
  540. }
  541. RetCode Wave4VpuBuildUpDecParam(CodecInst* instance, DecOpenParam* param)
  542. {
  543. RetCode ret = RETCODE_SUCCESS;
  544. DecInfo* pDecInfo;
  545. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  546. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  547. pDecInfo->streamRdPtrRegAddr = W4_BS_RD_PTR;
  548. pDecInfo->streamWrPtrRegAddr = W4_BS_WR_PTR;
  549. pDecInfo->frameDisplayFlagRegAddr = W4_RET_DEC_DISP_FLAG;
  550. pDecInfo->currentPC = W4_VCPU_CUR_PC;
  551. pDecInfo->busyFlagAddr = W4_VPU_BUSY_STATUS;
  552. if ((pAttr->supportDecoders&(1<<param->bitstreamFormat)) == 0)
  553. return RETCODE_NOT_SUPPORTED_FEATURE;
  554. pDecInfo->seqChangeMask = (param->bitstreamFormat == STD_HEVC) ?
  555. SEQ_CHANGE_ENABLE_ALL_HEVC : SEQ_CHANGE_ENABLE_ALL_VP9;
  556. pDecInfo->targetSubLayerId = HEVC_MAX_SUB_LAYER_ID;
  557. if (param->vbWork.size > 0) {
  558. pDecInfo->vbWork = param->vbWork;
  559. pDecInfo->workBufferAllocExt = TRUE;
  560. vdi_attach_dma_memory(instance->coreIdx, &param->vbWork);
  561. }
  562. else {
  563. if ((instance->productId == PRODUCT_ID_412) || (instance->productId == PRODUCT_ID_512) || (instance->productId == PRODUCT_ID_515)) {
  564. pDecInfo->vbWork.size = WAVE412DEC_WORKBUF_SIZE;
  565. }
  566. else {
  567. pDecInfo->vbWork.size = WAVE4DEC_WORKBUF_SIZE;
  568. }
  569. pDecInfo->workBufferAllocExt = FALSE;
  570. if (vdi_allocate_dma_memory(instance->coreIdx, &pDecInfo->vbWork) < 0) {
  571. pDecInfo->vbWork.base = 0;
  572. pDecInfo->vbWork.phys_addr = 0;
  573. pDecInfo->vbWork.size = 0;
  574. pDecInfo->vbWork.virt_addr = 0;
  575. return RETCODE_INSUFFICIENT_RESOURCE;
  576. }
  577. }
  578. vdi_clear_memory(instance->coreIdx, pDecInfo->vbWork.phys_addr, pDecInfo->vbWork.size, 0);
  579. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  580. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  581. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  582. Wave4BitIssueCommand(instance, CREATE_INSTANCE);
  583. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  584. if (instance->loggingEnable)
  585. vdi_log(instance->coreIdx, CREATE_INSTANCE, 2);
  586. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork);
  587. return RETCODE_VPU_RESPONSE_TIMEOUT;
  588. }
  589. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE) {
  590. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork);
  591. ret = RETCODE_FAILURE;
  592. }
  593. return ret;
  594. }
  595. RetCode Wave4VpuDecFiniSeq(CodecInst* instance)
  596. {
  597. DecInfo* pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  598. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  599. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  600. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  601. Wave4BitIssueCommand(instance, FINI_SEQ);
  602. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1)
  603. return RETCODE_VPU_RESPONSE_TIMEOUT;
  604. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE)
  605. return RETCODE_FAILURE;
  606. return RETCODE_SUCCESS;
  607. }
  608. RetCode Wave4VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos, BOOL explicitEnd)
  609. {
  610. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  611. pDecInfo->streamEndflag = (eos == 1) ? TRUE : FALSE;
  612. if (running == TRUE) {
  613. BitStreamMode bsMode = (BitStreamMode)pDecInfo->openParam.bitstreamMode;
  614. BOOL explicitEndFlag=0;
  615. explicitEndFlag = (BOOL)(bsMode == BS_MODE_PIC_END || pDecInfo->streamEndflag == TRUE || explicitEnd == TRUE);
  616. VpuWriteReg(instance->coreIdx, W4_BS_OPTION, (pDecInfo->streamEndflag<<1)|explicitEndFlag );
  617. }
  618. return RETCODE_SUCCESS;
  619. }
  620. RetCode Wave4VpuDecRegisterFramebuffer(CodecInst* inst, FrameBuffer* fbArr, TiledMapType mapType, Uint32 count)
  621. {
  622. RetCode ret = RETCODE_SUCCESS;
  623. DecInfo* pDecInfo = &inst->CodecInfo->decInfo;
  624. DecInitialInfo* sequenceInfo = &inst->CodecInfo->decInfo.initialInfo;
  625. Int32 q, j, i, remain, idx;
  626. Uint32 mvCount;
  627. Uint32 k;
  628. Int32 coreIdx, startNo, endNo;
  629. Uint32 regVal, cbcrInterleave, nv21;
  630. Uint32 endian, yuvFormat = 0;
  631. Uint32 addrY, addrCb, addrCr;
  632. Uint32 mvColSize, fbcYTblSize, fbcCTblSize, lumaStride, chromaStride;
  633. vpu_buffer_t vbBuffer;
  634. Uint32 stride;
  635. Uint32 colorFormat = 0;
  636. Uint32 outputFormat = 0;
  637. Uint32 axiID;
  638. coreIdx = inst->coreIdx;
  639. axiID = pDecInfo->openParam.virtAxiID;
  640. cbcrInterleave = pDecInfo->openParam.cbcrInterleave;
  641. nv21 = pDecInfo->openParam.nv21;
  642. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  643. if (mapType == COMPRESSED_FRAME_MAP) {
  644. cbcrInterleave = 0;
  645. nv21 = 0;
  646. if (inst->codecMode == C7_VP9_DEC) {
  647. mvColSize = WAVE4_DEC_VP9_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  648. }
  649. else if (inst->codecMode == HEVC_DEC) {
  650. mvColSize = WAVE4_DEC_HEVC_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  651. }
  652. else if (inst->codecMode == C7_AVS2_DEC) {
  653. mvColSize = CODA7Q_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight); // [FIX ME!!!]
  654. }
  655. else {
  656. mvColSize = CODA7Q_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  657. }
  658. mvColSize = VPU_ALIGN16(mvColSize);
  659. vbBuffer.phys_addr = 0;
  660. if (inst->codecMode == HEVC_DEC || inst->codecMode == C7_HEVC_DEC || inst->codecMode == C7_VP9_DEC || inst->codecMode == C7_AVS2_DEC) {
  661. vbBuffer.size = ((mvColSize+4095)&~4095)+4096; /* 4096 is a margin */
  662. mvCount = count;
  663. for (k=0 ; k<mvCount ; k++) {
  664. if ( pDecInfo->vbMV[k].size == 0) {
  665. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  666. return RETCODE_INSUFFICIENT_RESOURCE;
  667. pDecInfo->vbMV[k] = vbBuffer;
  668. }
  669. }
  670. }
  671. //VP9 Decoded size : 64 aligned.
  672. if (inst->codecMode == C7_VP9_DEC)
  673. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(VPU_ALIGN64(pDecInfo->initialInfo.picWidth), VPU_ALIGN64(pDecInfo->initialInfo.picHeight));
  674. else if (inst->codecMode == HEVC_DEC)
  675. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  676. else if (inst->codecMode == C7_AVS2_DEC)
  677. fbcYTblSize = CODA7Q_FBC_LUMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight); // [FIX ME!!!]
  678. else
  679. fbcYTblSize = CODA7Q_FBC_LUMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  680. fbcYTblSize = VPU_ALIGN16(fbcYTblSize);
  681. vbBuffer.phys_addr = 0;
  682. vbBuffer.size = ((fbcYTblSize+4095)&~4095)+4096;
  683. for (k=0 ; k<count ; k++) {
  684. if ( pDecInfo->vbFbcYTbl[k].size == 0) {
  685. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  686. return RETCODE_INSUFFICIENT_RESOURCE;
  687. pDecInfo->vbFbcYTbl[k] = vbBuffer;
  688. }
  689. }
  690. if (inst->codecMode == C7_VP9_DEC)
  691. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(pDecInfo->initialInfo.picWidth), VPU_ALIGN64(pDecInfo->initialInfo.picHeight));
  692. else if (inst->codecMode == HEVC_DEC)
  693. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  694. else if (inst->codecMode == C7_AVS2_DEC)
  695. fbcCTblSize = CODA7Q_FBC_CHROMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight); // [FIX ME!!!]
  696. else
  697. fbcCTblSize = CODA7Q_FBC_CHROMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  698. fbcCTblSize = VPU_ALIGN16(fbcCTblSize);
  699. vbBuffer.phys_addr = 0;
  700. vbBuffer.size = ((fbcCTblSize+4095)&~4095)+4096;
  701. for (k=0 ; k<count ; k++) {
  702. if ( pDecInfo->vbFbcCTbl[k].size == 0) {
  703. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  704. return RETCODE_INSUFFICIENT_RESOURCE;
  705. pDecInfo->vbFbcCTbl[k] = vbBuffer;
  706. }
  707. }
  708. if (inst->productId == PRODUCT_ID_420 || inst->productId == PRODUCT_ID_420L) {
  709. lumaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth)*(pDecInfo->initialInfo.lumaBitdepth>8 ? 5 : 4);
  710. lumaStride = VPU_ALIGN32(lumaStride);
  711. chromaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth/2)*(pDecInfo->initialInfo.chromaBitdepth>8 ? 5 : 4);
  712. chromaStride = VPU_ALIGN32(chromaStride);
  713. VpuWriteReg(coreIdx, W4_FBC_STRIDE, lumaStride<<16 | chromaStride);
  714. }
  715. }
  716. endian = vdi_convert_endian(coreIdx, fbArr[0].endian) & VDI_128BIT_ENDIAN_MASK;
  717. regVal = (pDecInfo->initialInfo.picWidth<<16)|(pDecInfo->initialInfo.picHeight);
  718. VpuWriteReg(coreIdx, W4_PIC_SIZE, regVal);
  719. yuvFormat = 0; /* YUV420 8bit */
  720. if (mapType == LINEAR_FRAME_MAP) {
  721. BOOL justified = W4_WTL_RIGHT_JUSTIFIED;
  722. Uint32 formatNo = W4_WTL_PIXEL_8BIT;
  723. switch (pDecInfo->wtlFormat) {
  724. case FORMAT_420_P10_16BIT_MSB:
  725. justified = W4_WTL_RIGHT_JUSTIFIED;
  726. formatNo = W4_WTL_PIXEL_16BIT;
  727. break;
  728. case FORMAT_420_P10_16BIT_LSB:
  729. justified = W4_WTL_LEFT_JUSTIFIED;
  730. formatNo = W4_WTL_PIXEL_16BIT;
  731. break;
  732. case FORMAT_420_P10_32BIT_MSB:
  733. justified = W4_WTL_RIGHT_JUSTIFIED;
  734. formatNo = W4_WTL_PIXEL_32BIT;
  735. break;
  736. case FORMAT_420_P10_32BIT_LSB:
  737. justified = W4_WTL_LEFT_JUSTIFIED;
  738. formatNo = W4_WTL_PIXEL_32BIT;
  739. break;
  740. default:
  741. break;
  742. }
  743. yuvFormat = justified<<2 | formatNo;
  744. }
  745. stride = fbArr[0].stride;
  746. if (mapType == COMPRESSED_FRAME_MAP) {
  747. if ( pDecInfo->chFbcFrameIdx != -1 )
  748. stride = fbArr[pDecInfo->chFbcFrameIdx].stride;
  749. } else {
  750. if ( pDecInfo->chBwbFrameIdx != -1 )
  751. stride = fbArr[pDecInfo->chBwbFrameIdx].stride;
  752. }
  753. if (mapType == LINEAR_FRAME_MAP) {
  754. outputFormat = 0;
  755. outputFormat |= (nv21 << 1);
  756. outputFormat |= (cbcrInterleave << 0);
  757. if (inst->productId == PRODUCT_ID_420 || inst->productId == PRODUCT_ID_420L) {
  758. lumaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth)*(pDecInfo->initialInfo.lumaBitdepth>8 ? 5 : 4);
  759. lumaStride = VPU_ALIGN32(lumaStride);
  760. chromaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth/2)*(pDecInfo->initialInfo.chromaBitdepth>8 ? 5 : 4);
  761. chromaStride = VPU_ALIGN32(chromaStride);
  762. VpuWriteReg(coreIdx, W4_FBC_STRIDE, lumaStride<<16 | chromaStride);
  763. }
  764. }
  765. regVal =
  766. ((mapType == LINEAR_FRAME_MAP)<< 28) |
  767. (axiID << 24) |
  768. (1<< 23) | /* PIXEL ORDER in 128bit. first pixel in low address */
  769. (yuvFormat << 20) |
  770. (colorFormat << 19) |
  771. (outputFormat << 16) |
  772. (stride);
  773. VpuWriteReg(coreIdx, W4_COMMON_PIC_INFO, regVal);
  774. if ( pDecInfo->interResChange == 1)
  775. {
  776. i=0;
  777. // W4_SFB_OPTION [2:0] : 0x3 = SET_FB_UPDATE_MODE
  778. VpuWriteReg(coreIdx, W4_SFB_OPTION, (pDecInfo->openParam.fbc_mode<<20) | (endian<<16) | (1<<4) | (1<<3) | 3);
  779. if (mapType == COMPRESSED_FRAME_MAP) {
  780. idx=pDecInfo->chFbcFrameIdx;
  781. } else {
  782. idx=pDecInfo->chBwbFrameIdx;
  783. }
  784. VpuWriteReg(coreIdx, W4_SET_FB_NUM, (idx<<8)|idx);
  785. if (mapType == LINEAR_FRAME_MAP && pDecInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  786. addrY = fbArr[idx].bufY;
  787. addrCb = fbArr[idx].bufCr;
  788. addrCr = fbArr[idx].bufCb;
  789. }
  790. else {
  791. addrY = fbArr[idx].bufY;
  792. addrCb = fbArr[idx].bufCb;
  793. addrCr = fbArr[idx].bufCr;
  794. }
  795. VpuWriteReg(coreIdx, W4_ADDR_LUMA_BASE0 + (i<<4), addrY);
  796. VpuWriteReg(coreIdx, W4_ADDR_CB_BASE0 + (i<<4), addrCb);
  797. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  798. if (mapType == COMPRESSED_FRAME_MAP) {
  799. VpuWriteReg(coreIdx, W4_ADDR_FBC_Y_OFFSET0 + (i<<4), pDecInfo->vbFbcYTbl[idx].phys_addr); /* Luma FBC offset table */
  800. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), pDecInfo->vbFbcCTbl[idx].phys_addr); /* Chroma FBC offset table */
  801. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), pDecInfo->vbMV[idx].phys_addr);
  802. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  803. pDecInfo->vbFbcYTbl[idx].phys_addr,
  804. pDecInfo->vbFbcCTbl[idx].phys_addr,
  805. pDecInfo->vbMV[idx].phys_addr);
  806. }
  807. else {
  808. VpuWriteReg(coreIdx, W4_ADDR_CR_BASE0 + (i<<4), addrCr);
  809. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  810. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), 0);
  811. APIDPRINT("Cr(0x%08x)\n", addrCr);
  812. }
  813. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  814. VpuWriteReg(coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  815. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  816. Wave4BitIssueCommand(inst, SET_FRAMEBUF);
  817. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  818. return RETCODE_VPU_RESPONSE_TIMEOUT;
  819. }
  820. }
  821. else
  822. {
  823. remain = count;
  824. q = (remain+7)/8;
  825. idx = 0;
  826. for (j=0; j<q; j++) {
  827. regVal = (pDecInfo->openParam.fbc_mode<<20)|(endian<<16) | (j==q-1)<<4 | ((j==0)<<3) ;
  828. VpuWriteReg(coreIdx, W4_SFB_OPTION, regVal);
  829. startNo = j*8;
  830. endNo = startNo + (remain>=8 ? 8 : remain) - 1;
  831. VpuWriteReg(coreIdx, W4_SET_FB_NUM, (startNo<<8)|endNo);
  832. for (i=0; i<8 && i<remain; i++) {
  833. if (mapType == LINEAR_FRAME_MAP && pDecInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  834. addrY = fbArr[i+startNo].bufY;
  835. addrCb = fbArr[i+startNo].bufCr;
  836. addrCr = fbArr[i+startNo].bufCb;
  837. }
  838. else {
  839. addrY = fbArr[i+startNo].bufY;
  840. addrCb = fbArr[i+startNo].bufCb;
  841. addrCr = fbArr[i+startNo].bufCr;
  842. }
  843. VpuWriteReg(coreIdx, W4_ADDR_LUMA_BASE0 + (i<<4), addrY);
  844. VpuWriteReg(coreIdx, W4_ADDR_CB_BASE0 + (i<<4), addrCb);
  845. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  846. if (mapType == COMPRESSED_FRAME_MAP) {
  847. VpuWriteReg(coreIdx, W4_ADDR_FBC_Y_OFFSET0 + (i<<4), pDecInfo->vbFbcYTbl[idx].phys_addr); /* Luma FBC offset table */
  848. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), pDecInfo->vbFbcCTbl[idx].phys_addr); /* Chroma FBC offset table */
  849. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), pDecInfo->vbMV[idx].phys_addr);
  850. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  851. pDecInfo->vbFbcYTbl[idx].phys_addr,
  852. pDecInfo->vbFbcCTbl[idx].phys_addr,
  853. pDecInfo->vbMV[idx].phys_addr);
  854. }
  855. else {
  856. VpuWriteReg(coreIdx, W4_ADDR_CR_BASE0 + (i<<4), addrCr);
  857. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  858. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), 0);
  859. APIDPRINT("Cr(0x%08x)\n", addrCr);
  860. }
  861. idx++;
  862. }
  863. remain -= i;
  864. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  865. VpuWriteReg(coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  866. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  867. // CODA7Q needs temporal buffer address.
  868. VpuWriteReg(coreIdx, W4_ADDR_TEMP_BASE, pDecInfo->vbTemp.phys_addr);
  869. VpuWriteReg(coreIdx, W4_TEMP_SIZE, pDecInfo->vbTemp.size);
  870. VpuWriteReg(coreIdx, W4_TEMP_PARAM, 0);
  871. Wave4BitIssueCommand(inst, SET_FRAMEBUF);
  872. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  873. return RETCODE_VPU_RESPONSE_TIMEOUT;
  874. }
  875. }
  876. }
  877. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  878. if (regVal == 0) {
  879. return RETCODE_FAILURE;
  880. }
  881. if (inst->productId == PRODUCT_ID_7Q) {
  882. if (ConfigSecAXICoda7(coreIdx, pDecInfo->openParam.bitstreamFormat,
  883. &pDecInfo->secAxiInfo,
  884. pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight, sequenceInfo->profile) == 0) {
  885. return RETCODE_INSUFFICIENT_RESOURCE;
  886. }
  887. }
  888. else {
  889. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  890. &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight,
  891. sequenceInfo->profile, sequenceInfo->level) == 0) {
  892. return RETCODE_INSUFFICIENT_RESOURCE;
  893. }
  894. }
  895. return ret;
  896. }
  897. RetCode Wave4VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  898. {
  899. Int32 regVal;
  900. Uint32 i, j;
  901. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  902. VpuWriteReg(instance->coreIdx, W4_FLUSH_DECODER_OPTION, FLUSH_DPB);
  903. /* Set up work-buffer */
  904. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  905. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  906. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  907. Wave4BitIssueCommand(instance, FLUSH_DECODER);
  908. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  909. return RETCODE_VPU_RESPONSE_TIMEOUT;
  910. }
  911. // Clear display flags.
  912. pDecInfo->frameDisplayFlag = 0;
  913. regVal = VpuReadReg(instance->coreIdx, W4_RET_SUCCESS);
  914. if (regVal == 0) {
  915. return RETCODE_FAILURE;
  916. }
  917. /* Get remaining framebuffers */
  918. if (framebufferIndexes != NULL) {
  919. for (j=0,i=W4_RET_DEC_DISPLAY_INDEX_0; i<=W4_RET_DEC_DISPLAY_INDEX_15 && j<size; i+=4, j++) {
  920. regVal = VpuReadReg(instance->coreIdx, i);
  921. framebufferIndexes[j].linearIndex = regVal>>16;
  922. framebufferIndexes[j].tiledIndex = regVal&0xffff;
  923. if (pDecInfo->wtlEnable == FALSE)
  924. framebufferIndexes[j].linearIndex = framebufferIndexes[j].tiledIndex;
  925. APIDPRINT("FLUSH LINEAR(%d) TILED(%d)\n", framebufferIndexes[j].linearIndex, framebufferIndexes[j].tiledIndex);
  926. }
  927. }
  928. return RETCODE_SUCCESS;
  929. }
  930. RetCode Wave4VpuEncFiniSeq(CodecInst* instance)
  931. {
  932. EncInfo* pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  933. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  934. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  935. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  936. Wave4BitIssueCommand(instance, FINI_SEQ);
  937. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1)
  938. return RETCODE_VPU_RESPONSE_TIMEOUT;
  939. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE)
  940. return RETCODE_FAILURE;
  941. return RETCODE_SUCCESS;
  942. }
  943. RetCode Wave4VpuBuildUpEncParam(CodecInst* instance, EncOpenParam* param)
  944. {
  945. RetCode ret = RETCODE_SUCCESS;
  946. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  947. EncInfo* pEncInfo = &instance->CodecInfo->encInfo;
  948. pEncInfo->streamRdPtrRegAddr = W4_BS_RD_PTR;
  949. pEncInfo->streamWrPtrRegAddr = W4_BS_WR_PTR;
  950. pEncInfo->currentPC = W4_VCPU_CUR_PC;
  951. pEncInfo->busyFlagAddr = W4_VPU_BUSY_STATUS;
  952. if (instance->productId == PRODUCT_ID_7Q) {
  953. if (param->bitstreamFormat == STD_HEVC)
  954. instance->codecMode = C7_HEVC_ENC;
  955. else if (param->bitstreamFormat == STD_AVC)
  956. instance->codecMode = C7_AVC_ENC;
  957. else if (param->bitstreamFormat == STD_MPEG4 || param->bitstreamFormat == STD_H263)
  958. instance->codecMode = C7_MP4_ENC;
  959. else
  960. return RETCODE_NOT_SUPPORTED_FEATURE;
  961. }
  962. else {
  963. if (param->bitstreamFormat == STD_HEVC)
  964. instance->codecMode = HEVC_ENC;
  965. else
  966. return RETCODE_NOT_SUPPORTED_FEATURE;
  967. }
  968. if ((pAttr->supportEncoders&(1<<param->bitstreamFormat)) == 0)
  969. return RETCODE_NOT_SUPPORTED_FEATURE;
  970. pEncInfo->vbWork.size = WAVE4ENC_WORKBUF_SIZE;
  971. if (vdi_allocate_dma_memory(instance->coreIdx, &pEncInfo->vbWork) < 0)
  972. {
  973. pEncInfo->vbWork.base = 0;
  974. pEncInfo->vbWork.phys_addr = 0;
  975. pEncInfo->vbWork.size = 0;
  976. pEncInfo->vbWork.virt_addr = 0;
  977. return RETCODE_INSUFFICIENT_RESOURCE;
  978. }
  979. vdi_clear_memory(instance->coreIdx, pEncInfo->vbWork.phys_addr, pEncInfo->vbWork.size, 0);
  980. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  981. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  982. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  983. Wave4BitIssueCommand(instance, CREATE_INSTANCE);
  984. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  985. if (instance->loggingEnable)
  986. vdi_log(instance->coreIdx, CREATE_INSTANCE, 2);
  987. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork);
  988. return RETCODE_VPU_RESPONSE_TIMEOUT;
  989. }
  990. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE) {
  991. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork);
  992. ret = RETCODE_FAILURE;
  993. }
  994. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  995. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  996. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  997. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  998. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  999. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  1000. pEncInfo->stride = 0;
  1001. pEncInfo->vbFrame.size = 0;
  1002. pEncInfo->vbPPU.size = 0;
  1003. pEncInfo->frameAllocExt = 0;
  1004. pEncInfo->ppuAllocExt = 0;
  1005. pEncInfo->secAxiInfo.u.wave4.useBitEnable = 0;
  1006. pEncInfo->secAxiInfo.u.wave4.useIpEnable = 0;
  1007. pEncInfo->secAxiInfo.u.wave4.useLfRowEnable = 0;
  1008. pEncInfo->rotationEnable = 0;
  1009. pEncInfo->mirrorEnable = 0;
  1010. pEncInfo->mirrorDirection = MIRDIR_NONE;
  1011. pEncInfo->rotationAngle = 0;
  1012. pEncInfo->initialInfoObtained = 0;
  1013. pEncInfo->ringBufferEnable = param->ringBufferEnable;
  1014. pEncInfo->sliceIntEnable = 0;
  1015. return ret;
  1016. }