regdefine.h 7.5 KB

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  1. /*
  2. * Copyright (c) 2018, Chips&Media
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright notice,
  11. * this list of conditions and the following disclaimer in the documentation
  12. * and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  15. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  16. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  17. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  18. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  19. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  21. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  23. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. */
  25. #ifdef USE_FEEDING_METHOD_BUFFER
  26. #include "codaj12/config.h"
  27. #else
  28. #include "../config.h"
  29. #endif
  30. #ifndef NPT_REGDEFINE_H_INCLUDED
  31. #define NPT_REGDEFINE_H_INCLUDED
  32. //------------------------------------------------------------------------------
  33. // REGISTER BASE
  34. //------------------------------------------------------------------------------
  35. #define NPT_REG_SIZE 0x300
  36. #define NPT_BASE 0x00
  37. #define NPT_PROC_BASE (NPT_BASE + (4*NPT_REG_SIZE))
  38. /*--------------------------------------------------------------------
  39. NIEUPORT REGISTERS
  40. --------------------------------------------------------------------*/
  41. // MAIN CONTROL REGISTER
  42. #define MJPEG_PIC_START_REG (NPT_BASE + 0x000) // [3] - start partial encoding [2] - pic stop en/decoding[1] - pic init en/decoding [0] - pic start en/decoding
  43. #define MJPEG_PIC_STATUS_REG (NPT_BASE + 0x004) // [8] - stop [7:4] - partial buffer interrupt [3] - overflow, [2] - bbc interrupt, [1] - error, [0] - done
  44. #define MJPEG_PIC_ERRMB_REG (NPT_BASE + 0x008) // [27:24] - error restart idx, [23:12] - error MCU pos X, [11:0] - error MCU pos Y
  45. #define MJPEG_PIC_SETMB_REG (NPT_BASE + 0x00C) // [27:16] - MCU pos X, [11:0] - MCU pos Y
  46. #define MJPEG_PIC_CTRL_REG (NPT_BASE + 0x010) // [12:7] huffman table index [6] - user huffman en, [4] - TC direction, [3] - encoder enable, [1:0] - operation mode
  47. #define MJPEG_PIC_SIZE_REG (NPT_BASE + 0x014)
  48. #define MJPEG_MCU_INFO_REG (NPT_BASE + 0x018)
  49. #define MJPEG_ROT_INFO_REG (NPT_BASE + 0x01C) // [4] - rot-mir enable, [3:0] - rot-mir mode
  50. #define MJPEG_SCL_INFO_REG (NPT_BASE + 0x020)
  51. #define MJPEG_IF_INFO_REG (NPT_BASE + 0x024) // [1] - sensor interface clear, [0] - display interface clear
  52. #define MJPEG_CLP_INFO_REG (NPT_BASE + 0x028)
  53. #define MJPEG_OP_INFO_REG (NPT_BASE + 0x02C) // [31:16] - # of line in 1 partial buffer, [5:3] - # of partial buffers [2:0] - # of request
  54. #define MJPEG_DPB_CONFIG_REG (NPT_BASE + 0x030)
  55. #define MJPEG_DPB_BASE00_REG (NPT_BASE + 0x034)
  56. #define MJPEG_DPB_BASE01_REG (NPT_BASE + 0x038)
  57. #define MJPEG_DPB_BASE02_REG (NPT_BASE + 0x03C)
  58. #define MJPEG_DPB_BASE10_REG (NPT_BASE + 0x040)
  59. #define MJPEG_DPB_BASE11_REG (NPT_BASE + 0x044)
  60. #define MJPEG_DPB_BASE12_REG (NPT_BASE + 0x048)
  61. #define MJPEG_DPB_BASE20_REG (NPT_BASE + 0x04C)
  62. #define MJPEG_DPB_BASE21_REG (NPT_BASE + 0x050)
  63. #define MJPEG_DPB_BASE22_REG (NPT_BASE + 0x054)
  64. #define MJPEG_DPB_BASE30_REG (NPT_BASE + 0x058)
  65. #define MJPEG_DPB_BASE31_REG (NPT_BASE + 0x05C)
  66. #define MJPEG_DPB_BASE32_REG (NPT_BASE + 0x060)
  67. #define MJPEG_DPB_YSTRIDE_REG (NPT_BASE + 0x064)
  68. #define MJPEG_DPB_CSTRIDE_REG (NPT_BASE + 0x068)
  69. #define MJPEG_WRESP_CHECK_REG (NPT_BASE + 0x06C)
  70. #define MJPEG_CLP_BASE_REG (NPT_BASE + 0x070)
  71. #define MJPEG_CLP_SIZE_REG (NPT_BASE + 0x074)
  72. #define MJPEG_HUFF_CTRL_REG (NPT_BASE + 0x080)
  73. #define MJPEG_HUFF_ADDR_REG (NPT_BASE + 0x084)
  74. #define MJPEG_HUFF_DATA_REG (NPT_BASE + 0x088)
  75. #define MJPEG_QMAT_CTRL_REG (NPT_BASE + 0x090)
  76. #define MJPEG_QMAT_ADDR_REG (NPT_BASE + 0x094)
  77. #define MJPEG_QMAT_DATA_REG (NPT_BASE + 0x098)
  78. #define MJPEG_COEF_CTRL_REG (NPT_BASE + 0x0A0)
  79. #define MJPEG_COEF_ADDR_REG (NPT_BASE + 0x0A4)
  80. #define MJPEG_COEF_DATA_REG (NPT_BASE + 0x0A8)
  81. #define MJPEG_RST_INTVAL_REG (NPT_BASE + 0x0B0)
  82. #define MJPEG_RST_INDEX_REG (NPT_BASE + 0x0B4)
  83. #define MJPEG_RST_COUNT_REG (NPT_BASE + 0x0B8)
  84. #define MJPEG_INTR_MASK_REG (NPT_BASE + 0x0C0)
  85. #define MJPEG_CYCLE_INFO_REG (NPT_BASE + 0x0C8)
  86. #define MJPEG_DPCM_DIFF_Y_REG (NPT_BASE + 0x0F0)
  87. #define MJPEG_DPCM_DIFF_CB_REG (NPT_BASE + 0x0F4)
  88. #define MJPEG_DPCM_DIFF_CR_REG (NPT_BASE + 0x0F8)
  89. #define MJPEG_VERSION_INFO_REG (NPT_BASE + 0x0FC)
  90. // GBU CONTROL REGISTER
  91. #define MJPEG_GBU_CTRL_REG (NPT_BASE + 0x100) // [3] - GBU flush for encoding [2] - init GBU for decoding [1] - init GBU ff emulation for decoding [0] - reserved
  92. #define MJPEG_GBU_PBIT_BUSY_REG (NPT_BASE + 0x104)
  93. #define MJPEG_GBU_BPTR_REG (NPT_BASE + 0x110)
  94. #define MJPEG_GBU_WPTR_REG (NPT_BASE + 0x114)
  95. #define MJPEG_GBU_TCNT_REG (NPT_BASE + 0x118)
  96. //#define MJPEG_GBU_TCNT_REG+4 (NPT_BASE + 0x11C)
  97. #define MJPEG_GBU_PBIT_08_REG (NPT_BASE + 0x120)
  98. #define MJPEG_GBU_PBIT_16_REG (NPT_BASE + 0x124)
  99. #define MJPEG_GBU_PBIT_24_REG (NPT_BASE + 0x128)
  100. #define MJPEG_GBU_PBIT_32_REG (NPT_BASE + 0x12C)
  101. #define MJPEG_GBU_BBSR_REG (NPT_BASE + 0x140)
  102. #define MJPEG_GBU_BBER_REG (NPT_BASE + 0x144)
  103. #define MJPEG_GBU_BBIR_REG (NPT_BASE + 0x148)
  104. #define MJPEG_GBU_BBHR_REG (NPT_BASE + 0x14C)
  105. #define MJPEG_GBU_BCNT_REG (NPT_BASE + 0x158)
  106. #define MJPEG_GBU_FF_RPTR_REG (NPT_BASE + 0x160)
  107. #define MJPEG_GBU_FF_WPTR_REG (NPT_BASE + 0x164)
  108. // BBC CONTROL REGISTER
  109. #define MJPEG_BBC_END_ADDR_REG (NPT_BASE + 0x208)
  110. #define MJPEG_BBC_WR_PTR_REG (NPT_BASE + 0x20C)
  111. #define MJPEG_BBC_RD_PTR_REG (NPT_BASE + 0x210)
  112. #define MJPEG_BBC_EXT_ADDR_REG (NPT_BASE + 0x214)
  113. #define MJPEG_BBC_INT_ADDR_REG (NPT_BASE + 0x218)
  114. #define MJPEG_BBC_DATA_CNT_REG (NPT_BASE + 0x21C)
  115. #define MJPEG_BBC_COMMAND_REG (NPT_BASE + 0x220) // [2:1] - endianness [0] - load/save
  116. #define MJPEG_BBC_BUSY_REG (NPT_BASE + 0x224)
  117. #define MJPEG_BBC_CTRL_REG (NPT_BASE + 0x228) // [2:1] - endianness [0] - BBC auto run
  118. #define MJPEG_BBC_CUR_POS_REG (NPT_BASE + 0x22C)
  119. #define MJPEG_BBC_BAS_ADDR_REG (NPT_BASE + 0x230)
  120. #define MJPEG_BBC_STRM_CTRL_REG (NPT_BASE + 0x234) // [31] - end of bitstream file [23:0] - stream counter
  121. #define MJPEG_BBC_FLUSH_CMD_REG (NPT_BASE + 0x238)
  122. #define MJPEG_SLICE_INFO_REG (NPT_BASE + 0x240)
  123. #define MJPEG_SLICE_POS_REG (NPT_BASE + 0x244)
  124. #define MJPEG_SLICE_DPB_POS_REG (NPT_BASE + 0x248)
  125. #define MJPEG_INST_CTRL_START_REG (NPT_PROC_BASE + 0x000)
  126. #define MJPEG_INST_CTRL_STATUS_REG (NPT_PROC_BASE + 0x004)
  127. #endif