jpu-starfive.h 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2021 StarFive Technology Co., Ltd.
  4. */
  5. #ifndef __JPU_STARFIVE_H__
  6. #define __JPU_STARFIVE_H__
  7. #include <linux/io.h>
  8. #include <linux/clk.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/reset.h>
  11. #include <linux/reset-controller.h>
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/clk-provider.h>
  15. #define JPU_ID_NUM 5
  16. struct starfive_jpu_data {
  17. struct device *dev;
  18. struct clk *clk_jpu_id[JPU_ID_NUM];
  19. struct reset_control *rst_jpu_id[JPU_ID_NUM];
  20. };
  21. static struct starfive_jpu_data *sf_jpu = NULL;
  22. const char jpu_data_id[JPU_ID_NUM][15] = {
  23. "jpcgc300_main",
  24. "vdecbrg_main",
  25. "jpeg_axi",
  26. "jpeg_cclk",
  27. "jpeg_apb",
  28. };
  29. void starfive_jpu_rst_status(void)
  30. {
  31. int i;
  32. int rst_state;
  33. for (i = 0; i < JPU_ID_NUM; i++) {
  34. rst_state = reset_control_status(sf_jpu->rst_jpu_id[i]);
  35. dev_dbg(sf_jpu->dev, "status_rst%d:%d", i, rst_state);
  36. }
  37. return;
  38. }
  39. void starfive_jpu_clk_status(void)
  40. {
  41. int i;
  42. int clk_state;
  43. for (i = 0; i < JPU_ID_NUM; i++) {
  44. clk_state = __clk_is_enabled(sf_jpu->clk_jpu_id[i]);
  45. dev_dbg(sf_jpu->dev, "status_clk%d:%d", i, clk_state);
  46. }
  47. return;
  48. }
  49. /*Do not assert the reset: jpeg_axi, jpcgc300_main, vdecbrg_main. */
  50. void starfive_jpu_rst_exit(void)
  51. {
  52. int i;
  53. int ret;
  54. for (i = 3; i < JPU_ID_NUM; i++) {
  55. ret = reset_control_assert(sf_jpu->rst_jpu_id[i]);
  56. if (ret) {
  57. dev_err(sf_jpu->dev, "JPU reset assert failed:\n");
  58. dev_err(sf_jpu->dev, jpu_data_id[i]);
  59. }
  60. }
  61. return;
  62. }
  63. /*Do not disable the clock: jpeg_axi, jpcgc300_main, vdecbrg_main. */
  64. void starfive_jpu_clk_exit(void)
  65. {
  66. int i;
  67. for (i = 2; i < JPU_ID_NUM; i++) {
  68. clk_disable_unprepare(sf_jpu->clk_jpu_id[i]);
  69. }
  70. return;
  71. }
  72. static int starfive_jpu_clk_init(void)
  73. {
  74. int ret = 0;
  75. int i;
  76. for (i = 0; i < JPU_ID_NUM; i++) {
  77. ret = clk_prepare_enable(sf_jpu->clk_jpu_id[i]);
  78. if (ret) {
  79. dev_err(sf_jpu->dev, "JPU enable clock failed:\n");
  80. dev_err(sf_jpu->dev, jpu_data_id[i]);
  81. goto init_clk_failed;
  82. }
  83. }
  84. return 0;
  85. init_clk_failed:
  86. for(; i > 2 ; i--) {
  87. clk_disable_unprepare(sf_jpu->clk_jpu_id[i-1]);
  88. }
  89. return ret;
  90. }
  91. static int starfive_jpu_get_clk(void)
  92. {
  93. int ret = 0;
  94. int i;
  95. for ( i = 0; i < JPU_ID_NUM ; i++) {
  96. sf_jpu->clk_jpu_id[i] = devm_clk_get(sf_jpu->dev, jpu_data_id[i]);
  97. if (IS_ERR(sf_jpu->clk_jpu_id[i])) {
  98. dev_err(sf_jpu->dev, "JPU get clock failed: \n");
  99. dev_err(sf_jpu->dev, jpu_data_id[i]);
  100. ret = PTR_ERR(sf_jpu->clk_jpu_id[i]);
  101. goto get_clk_failed;
  102. }
  103. }
  104. return 0;
  105. get_clk_failed:
  106. for( ; i > 0 ; i--) {
  107. devm_clk_put(sf_jpu->dev, sf_jpu->clk_jpu_id[i-1]);
  108. }
  109. return ret;
  110. }
  111. static int starfive_jpu_reset_init(void)
  112. {
  113. int ret = 0;
  114. int i;
  115. for (i = 2; i < JPU_ID_NUM ; i++) {
  116. ret = reset_control_deassert(sf_jpu->rst_jpu_id[i]);
  117. if (ret) {
  118. dev_err(sf_jpu->dev, "JPU reset deassert failed: \n");
  119. dev_err(sf_jpu->dev, jpu_data_id[i]);
  120. goto init_reset_failed;
  121. }
  122. }
  123. return 0;
  124. init_reset_failed:
  125. for (; i > 3 ; i--) {
  126. reset_control_assert(sf_jpu->rst_jpu_id[i-1]);
  127. }
  128. return ret;
  129. }
  130. /*Do not manipulate the reset: jpcgc300_main, vdecbrg_main. */
  131. static int starfive_jpu_get_resets(void)
  132. {
  133. int ret = 0;
  134. int i;
  135. for (i = 2; i < JPU_ID_NUM ; i++) {
  136. sf_jpu->rst_jpu_id[i] = devm_reset_control_get_exclusive(sf_jpu->dev, jpu_data_id[i]);
  137. if (IS_ERR(sf_jpu->rst_jpu_id[i])) {
  138. dev_err(sf_jpu->dev, "failed to get JPU reset: \n");
  139. dev_err(sf_jpu->dev, jpu_data_id[i]);
  140. ret = PTR_ERR(sf_jpu->rst_jpu_id[i]);
  141. goto get_resets_failed;
  142. }
  143. }
  144. return 0;
  145. get_resets_failed:
  146. for (; i > 0; i--) {
  147. reset_control_put(sf_jpu->rst_jpu_id[i-1]);
  148. }
  149. return ret;
  150. }
  151. int starfive_jpu_data_init(struct device *dev)
  152. {
  153. int ret = 0;
  154. if (sf_jpu == NULL){
  155. sf_jpu = devm_kzalloc(dev, sizeof(*sf_jpu), GFP_KERNEL);
  156. if (!sf_jpu)
  157. return -ENOMEM;
  158. sf_jpu->dev = dev;
  159. ret = starfive_jpu_get_clk();
  160. if (ret) {
  161. dev_err(sf_jpu->dev, "failed to get jpu clock\n");
  162. return ret;
  163. }
  164. ret = starfive_jpu_get_resets();
  165. if (ret) {
  166. dev_err(sf_jpu->dev, "failed to get jpu resets\n");
  167. return ret;
  168. }
  169. }
  170. return 0;
  171. }
  172. int starfive_jpu_clk_enable(struct device *dev)
  173. {
  174. int ret = 0;
  175. ret = starfive_jpu_data_init(dev);
  176. if (ret)
  177. return ret;
  178. ret = starfive_jpu_clk_init();
  179. if (ret) {
  180. dev_err(sf_jpu->dev, "failed to enable jpu clock\n");
  181. return ret;
  182. }
  183. return 0;
  184. }
  185. int starfive_jpu_clk_disable(struct device *dev)
  186. {
  187. int ret = 0;
  188. ret = starfive_jpu_data_init(dev);
  189. if (ret)
  190. return ret;
  191. starfive_jpu_clk_exit();
  192. return 0;
  193. }
  194. int starfive_jpu_rst_deassert(struct device *dev)
  195. {
  196. int ret = 0;
  197. ret = starfive_jpu_data_init(dev);
  198. if (ret)
  199. return ret;
  200. ret = starfive_jpu_reset_init();
  201. if (ret) {
  202. dev_err(sf_jpu->dev, "failed to deassert jpu resets\n");
  203. return ret;
  204. }
  205. return 0;
  206. }
  207. int starfive_jpu_rst_assert(struct device *dev)
  208. {
  209. int ret = 0;
  210. ret = starfive_jpu_data_init(dev);
  211. if (ret)
  212. return ret;
  213. starfive_jpu_rst_exit();
  214. return 0;
  215. }
  216. int starfive_jpu_clk_rst_init(struct platform_device *pdev)
  217. {
  218. int ret = 0;
  219. ret = starfive_jpu_data_init(&pdev->dev);
  220. if (ret)
  221. return ret;
  222. ret = starfive_jpu_clk_init();
  223. if (ret) {
  224. dev_err(sf_jpu->dev, "failed to enable jpu clock\n");
  225. return ret;
  226. }
  227. starfive_jpu_rst_exit();
  228. mdelay(1);
  229. ret = starfive_jpu_reset_init();
  230. if (ret) {
  231. dev_err(sf_jpu->dev, "failed to set jpu reset\n");
  232. goto init_failed;
  233. }
  234. dev_info(sf_jpu->dev,"success to init JPU clock & reset.");
  235. return 0;
  236. init_failed:
  237. starfive_jpu_clk_exit();
  238. return ret;
  239. }
  240. #endif