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@@ -30,6 +30,8 @@
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/version.h>
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+#include <linux/of.h>
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+#include <soc/starfive/vic7100.h>
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#include "../../../vpuapi/vpuconfig.h"
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@@ -42,19 +44,25 @@
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#define DPRINTK(args...)
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#endif
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+/* if clktree is work,try this...*/
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+#define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+
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+#ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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/* definitions to be changed as customer configuration */
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/* if you want to have clock gating scheme frame by frame */
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-/* #define VPU_SUPPORT_CLOCK_CONTROL */
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+#define VPU_SUPPORT_CLOCK_CONTROL
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+#endif
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+
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/* if the driver want to use interrupt service from kernel ISR */
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#define VPU_SUPPORT_ISR
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/* if the platform driver knows the name of this driver */
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/* VPU_PLATFORM_DEVICE_NAME */
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-/* #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
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+#define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
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/* if this driver knows the dedicated video memory address */
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-#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
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+//#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
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#define VPU_PLATFORM_DEVICE_NAME "vdec"
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#define VPU_CLK_NAME "vcodec"
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@@ -63,11 +71,13 @@
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/* if the platform driver knows this driver */
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/* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
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-#define VPU_REG_BASE_ADDR 0x75000000
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+//#define VPU_REG_BASE_ADDR 0x75000000
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+#define VPU_REG_BASE_ADDR 0x130B0000
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+
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#define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
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#ifdef VPU_SUPPORT_ISR
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-#define VPU_IRQ_NUM (23+32)
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+#define VPU_IRQ_NUM (15)
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#endif
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/* this definition is only for chipsnmedia FPGA board env */
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@@ -77,6 +87,30 @@
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# define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
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#endif
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+#ifdef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+
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+typedef struct vpu_clkgen_t {
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+ void __iomem *en_ctrl;
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+ uint32_t rst_mask;
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+} vpu_clkgen_t;
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+
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+typedef struct vpu_clk_t{
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+ phys_addr_t pmu_base;
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+ void __iomem *clkgen;
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+ void __iomem *rst_status;
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+ uint32_t en_shift;
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+ uint32_t en_mask;
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+ vpu_clkgen_t apb_clk;
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+ vpu_clkgen_t axi_clk;
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+ vpu_clkgen_t bpu_clk;
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+ vpu_clkgen_t vce_clk;
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+ vpu_clkgen_t aximem_128b;
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+ void __iomem *rst_ctrl;
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+}vpu_clk_t;
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+#endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
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+
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+struct device *vpu_dev;
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+
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typedef struct vpu_drv_context_t {
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struct fasync_struct *async_queue;
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unsigned long interrupt_reason;
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@@ -110,11 +144,20 @@ static video_mm_t s_vmem;
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static vpudrv_buffer_t s_video_memory = {0};
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#endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
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+
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+#ifdef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+static int vpu_hw_reset(void);
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+static void vpu_clk_disable(struct vpu_clk_t *clk);
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+static int vpu_clk_enable(struct vpu_clk_t *clk);
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+static struct vpu_clk_t *vpu_clk_get(struct device *dev);
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+static void vpu_clk_put(struct vpu_clk_t *clk);
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+#else
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static int vpu_hw_reset(void);
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static void vpu_clk_disable(struct clk *clk);
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static int vpu_clk_enable(struct clk *clk);
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static struct clk *vpu_clk_get(struct device *dev);
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static void vpu_clk_put(struct clk *clk);
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+#endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
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/* end customer definition */
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static vpudrv_buffer_t s_instance_pool = {0};
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@@ -123,7 +166,12 @@ static vpu_drv_context_t s_vpu_drv_context;
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static int s_vpu_major;
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static struct cdev s_vpu_cdev;
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+#ifdef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+static struct vpu_clk_t *s_vpu_clk;
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+#else
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static struct clk *s_vpu_clk;
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+#endif
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+
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static int s_vpu_open_ref_count;
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#ifdef VPU_SUPPORT_ISR
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static int s_vpu_irq = VPU_IRQ_NUM;
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@@ -269,11 +317,12 @@ static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
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vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
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#else
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- vb->base = (unsigned long)dma_alloc_coherent(NULL, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
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+ vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
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if ((void *)(vb->base) == NULL) {
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printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
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return -1;
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}
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+ starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
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#endif
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return 0;
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}
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@@ -288,7 +337,7 @@ static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
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vmem_free(&s_vmem, vb->phys_addr, 0);
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#else
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if (vb->base)
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- dma_free_coherent(0, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
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+ dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
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#endif
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}
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@@ -745,6 +794,21 @@ static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
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DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
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}
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break;
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+ case VDI_IOCTL_FLUSH_DCACHE:
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+ {
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+ vpudrv_flush_cache_t cache_info;
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+
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+ DPRINTK("[JPUDRV][+]VDI_IOCTL_FLUSH_DCACHE\n");
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+ ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
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+ if (ret != 0)
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+ ret = -EFAULT;
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+
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+ if(cache_info.flag)
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+ starfive_flush_dcache(cache_info.start,cache_info.size);
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+
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+ DPRINTK("[JPUDRV][-]VDI_IOCTL_FLUSH_DCACHE\n");
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+ break;
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+ }
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default:
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{
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printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
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@@ -839,6 +903,8 @@ static int vpu_release(struct inode *inode, struct file *filp)
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}
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up(&s_vpu_sem);
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+ vpu_hw_reset();
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+
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return 0;
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}
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@@ -944,6 +1010,12 @@ static int vpu_probe(struct platform_device *pdev)
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struct resource *res = NULL;
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DPRINTK("[VPUDRV] vpu_probe\n");
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+
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+ if(pdev){
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+ vpu_dev = &pdev->dev;
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+ vpu_dev->coherent_dma_mask = 0xffffffff;
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+ }
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+
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if (pdev)
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res) {/* if platform driver is implemented */
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@@ -1340,9 +1412,16 @@ DONE_WAKEUP:
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#endif /* !CONFIG_PM */
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#ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
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+static const struct of_device_id vpu_of_id_table[] = {
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+ { .compatible = "cnm,cnm420l-vpu" },
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+ {}
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+};
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+MODULE_DEVICE_TABLE(of, vpu_of_id_table);
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+
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static struct platform_driver vpu_driver = {
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.driver = {
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.name = VPU_PLATFORM_DEVICE_NAME,
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+ .of_match_table = of_match_ptr(vpu_of_id_table),
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},
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.probe = vpu_probe,
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.remove = vpu_remove,
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@@ -1431,11 +1510,240 @@ static void __exit vpu_exit(void)
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MODULE_AUTHOR("A customer using C&M VPU, Inc.");
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MODULE_DESCRIPTION("VPU linux driver");
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-MODULE_LICENSE("Proprietary");
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+MODULE_LICENSE("GPL");
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module_init(vpu_init);
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module_exit(vpu_exit);
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+#ifdef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+
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+#define PMU_BASE_ADDR 0x17030000
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+#define PMU_VENC_MASK (0x1<<6)
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+
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+#define CLK_ENABLE_DATA 1
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+#define CLK_DISABLE_DATA 0
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+#define CLK_EN_SHIFT 31
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+#define CLK_EN_MASK 0x80000000U
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+
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+#define SAIF_BD_APBS_BASE 0x13020000
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+#define WAVE420L_CLK_AXI_CTRL 0x138U
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+#define WAVE420L_CLK_BPU_CTRL 0x13cU
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+#define WAVE420L_CLK_VCE_CTRL 0x140U
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+#define WAVE420L_CLK_APB_CTRL 0x144U
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+
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+#define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
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+#define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
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+
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+
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+#define RSTN_AXI_MASK (0x1 << 22)
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+#define RSTN_BPU_MASK (0x1 << 23)
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+#define RSTN_VCE_MASK (0x1 << 24)
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+#define RSTN_APB_MASK (0x1 << 25)
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+#define RSTN_128B_AXIMEM_MASK (0x1 << 26)
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+
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+
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+static void pmu_pd_set(vpu_clk_t *clk, int on_off, uint32_t pd_flag)
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+{
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+ const uint32_t flag_off = 0x0c;
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+ const uint32_t sw_off = 0x44;
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+ void __iomem *base = ioremap(clk->pmu_base, 0x100);
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+
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+ writel(pd_flag, base + flag_off);
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+ writel(0xff, base + sw_off);
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+ if (on_off) {
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+ writel(0x05, base + sw_off);
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+ writel(0x50, base + sw_off);
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+ } else {
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+ writel(0x0a, base + sw_off);
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+ writel(0xa0, base + sw_off);
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+ }
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+
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+ iounmap(base);
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+}
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+
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+static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
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+ uint32_t shift, uint32_t mask)
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+{
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+ uint32_t tmp;
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+
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+ tmp = readl(addr);
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+ tmp &= ~mask;
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+ tmp |= (data << shift) & mask;
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+ writel(tmp, addr);
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+}
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+
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+static void saif_assert_rst(volatile void __iomem *addr,
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+ const volatile void __iomem *addr_status, uint32_t mask)
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+{
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+ uint32_t tmp;
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+
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+ tmp = readl(addr);
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+ tmp |= mask;
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+ writel(tmp, addr);
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+ do {
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+ tmp = readl(addr_status);
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+ } while ((tmp & mask) != 0);
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+}
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+
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+static void saif_clear_rst(volatile void __iomem *addr,
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+ const volatile void __iomem *addr_status, uint32_t mask)
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+{
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+ uint32_t tmp;
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+
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+ tmp = readl(addr);
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+ tmp &= ~mask;
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+ writel(tmp, addr);
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+ do {
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+ tmp = readl(addr_status);
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+ } while ((tmp & mask) != mask);
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+}
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+
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+static void vpu_clk_control(vpu_clk_t *clk, bool enable)
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+{
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+ if (enable) {
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+ /*enable*/
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+ saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+
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+ /*clr-reset*/
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
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+ } else {
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+ /*assert-reset*/
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
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+
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+ /*disable*/
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+ saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ }
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+}
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+
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+static void vpu_aximem_128b_control(vpu_clk_t *clk, bool enable)
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+{
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+ if (enable) {
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
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+ } else {
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ }
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+}
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+
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+
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+static int vpu_of_clk_get(struct device *dev, vpu_clk_t *vpu_clk)
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+{
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+ if (!dev)
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+ return -ENXIO;
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+
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+ vpu_clk->pmu_base = PMU_BASE_ADDR;
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+ vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
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+ if (IS_ERR(vpu_clk->clkgen)) {
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+ dev_err(dev, "ioremap clkgen failed.\n");
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+ return PTR_ERR(vpu_clk->clkgen);
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+ }
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+
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+ /* clkgen define */
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+ vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_AXI_CTRL;
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+ vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_BPU_CTRL;
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+ vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_VCE_CTRL;
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+ vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_APB_CTRL;
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+ vpu_clk->en_mask = CLK_EN_MASK;
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+ vpu_clk->en_shift = CLK_EN_SHIFT;
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+
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+ /* rstgen define */
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+ vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
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+ vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
|
|
|
+ vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
|
|
|
+ vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
|
|
|
+ vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
|
|
|
+ vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
|
|
|
+ vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void vpu_clk_reset(vpu_clk_t *clk)
|
|
|
+{
|
|
|
+ /*assert-reset*/
|
|
|
+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
|
|
|
+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
|
|
|
+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
|
|
|
+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
|
|
|
+
|
|
|
+ /*clr-reset*/
|
|
|
+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
|
|
|
+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
|
|
|
+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
|
|
|
+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+int vpu_hw_reset(void)
|
|
|
+{
|
|
|
+ if (!s_vpu_clk)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ vpu_clk_reset(s_vpu_clk);
|
|
|
+
|
|
|
+ DPRINTK("[VPUDRV] reset vpu hardware. \n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+struct vpu_clk_t *vpu_clk_get(struct device *dev)
|
|
|
+{
|
|
|
+ vpu_clk_t *vpu_clk;
|
|
|
+
|
|
|
+ vpu_clk = devm_kzalloc(dev, sizeof(*vpu_clk), GFP_KERNEL);
|
|
|
+ if (!vpu_clk)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ if (vpu_of_clk_get(dev, vpu_clk))
|
|
|
+ goto err_get_clk;
|
|
|
+
|
|
|
+ return vpu_clk;
|
|
|
+err_get_clk:
|
|
|
+ kfree(vpu_clk);
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+void vpu_clk_put(struct vpu_clk_t *clk)
|
|
|
+{
|
|
|
+ iounmap(clk->clkgen);
|
|
|
+}
|
|
|
+
|
|
|
+static int vpu_clk_enable(struct vpu_clk_t *clk)
|
|
|
+{
|
|
|
+ if (clk == NULL || IS_ERR(clk))
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ pmu_pd_set(clk,true,PMU_VENC_MASK);
|
|
|
+ vpu_clk_control(clk,true);
|
|
|
+ vpu_aximem_128b_control(clk,true);
|
|
|
+
|
|
|
+ DPRINTK("[VPUDRV] vpu_clk_enable\n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void vpu_clk_disable(struct vpu_clk_t *clk)
|
|
|
+{
|
|
|
+ vpu_aximem_128b_control(clk,false);
|
|
|
+ vpu_clk_control(clk,false);
|
|
|
+ pmu_pd_set(clk,false,PMU_VENC_MASK);
|
|
|
+
|
|
|
+ DPRINTK("[VPUDRV] vpu_clk_disable\n");
|
|
|
+}
|
|
|
+
|
|
|
+#else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
|
|
|
int vpu_hw_reset(void)
|
|
|
{
|
|
|
DPRINTK("[VPUDRV] request vpu reset from application. \n");
|
|
@@ -1477,7 +1785,8 @@ int vpu_clk_enable(struct clk *clk)
|
|
|
/* for C&M EVB. */
|
|
|
|
|
|
DPRINTK("[VPUDRV] vpu_clk_enable\n");
|
|
|
- return clk_enable(clk);
|
|
|
+// return clk_enable(clk);
|
|
|
+ return 1;
|
|
|
}
|
|
|
|
|
|
return 0;
|
|
@@ -1487,8 +1796,8 @@ void vpu_clk_disable(struct clk *clk)
|
|
|
{
|
|
|
if (!(clk == NULL || IS_ERR(clk))) {
|
|
|
DPRINTK("[VPUDRV] vpu_clk_disable\n");
|
|
|
- clk_disable(clk);
|
|
|
+// clk_disable(clk);
|
|
|
}
|
|
|
}
|
|
|
-
|
|
|
+#endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
|
|
|
|