imx8mp_evk.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #ifndef __IMX8MP_EVK_H
  6. #define __IMX8MP_EVK_H
  7. #include <linux/sizes.h>
  8. #include <linux/stringify.h>
  9. #include <asm/arch/imx-regs.h>
  10. #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
  11. #define CONFIG_SPL_MAX_SIZE (152 * 1024)
  12. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  13. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  14. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  15. #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  16. #ifdef CONFIG_SPL_BUILD
  17. /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  18. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  19. #define CONFIG_SPL_STACK 0x960000
  20. #define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
  21. #define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
  22. #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
  23. #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
  24. #define CONFIG_SYS_ICACHE_OFF
  25. #define CONFIG_SYS_DCACHE_OFF
  26. #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  27. #undef CONFIG_DM_MMC
  28. #undef CONFIG_DM_PMIC
  29. #undef CONFIG_DM_PMIC_PFUZE100
  30. #define CONFIG_POWER
  31. #define CONFIG_POWER_I2C
  32. #define CONFIG_POWER_PCA9450
  33. #undef CONFIG_DM_I2C
  34. #define CONFIG_SYS_I2C
  35. #endif
  36. /* Initial environment variables */
  37. #define CONFIG_EXTRA_ENV_SETTINGS \
  38. "script=boot.scr\0" \
  39. "image=Image\0" \
  40. "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
  41. "fdt_addr=0x43000000\0" \
  42. "boot_fdt=try\0" \
  43. "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  44. "initrd_addr=0x43800000\0" \
  45. "bootm_size=0x10000000\0" \
  46. "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  47. "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  48. "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  49. "mmcautodetect=yes\0" \
  50. "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
  51. "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  52. "bootscript=echo Running bootscript from mmc ...; " \
  53. "source\0" \
  54. "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  55. "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  56. "mmcboot=echo Booting from mmc ...; " \
  57. "run mmcargs; " \
  58. "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  59. "if run loadfdt; then " \
  60. "booti ${loadaddr} - ${fdt_addr}; " \
  61. "else " \
  62. "echo WARN: Cannot load the DT; " \
  63. "fi; " \
  64. "else " \
  65. "echo wait for boot; " \
  66. "fi;\0" \
  67. "netargs=setenv bootargs ${jh_clk} console=${console} " \
  68. "root=/dev/nfs " \
  69. "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  70. "netboot=echo Booting from net ...; " \
  71. "run netargs; " \
  72. "if test ${ip_dyn} = yes; then " \
  73. "setenv get_cmd dhcp; " \
  74. "else " \
  75. "setenv get_cmd tftp; " \
  76. "fi; " \
  77. "${get_cmd} ${loadaddr} ${image}; " \
  78. "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  79. "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  80. "booti ${loadaddr} - ${fdt_addr}; " \
  81. "else " \
  82. "echo WARN: Cannot load the DT; " \
  83. "fi; " \
  84. "else " \
  85. "booti; " \
  86. "fi;\0"
  87. #define CONFIG_BOOTCOMMAND \
  88. "mmc dev ${mmcdev}; if mmc rescan; then " \
  89. "if run loadbootscript; then " \
  90. "run bootscript; " \
  91. "else " \
  92. "if run loadimage; then " \
  93. "run mmcboot; " \
  94. "else run netboot; " \
  95. "fi; " \
  96. "fi; " \
  97. "else booti ${loadaddr} - ${fdt_addr}; fi"
  98. /* Link Definitions */
  99. #define CONFIG_LOADADDR 0x40480000
  100. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  101. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  102. #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
  103. #define CONFIG_SYS_INIT_SP_OFFSET \
  104. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  105. #define CONFIG_SYS_INIT_SP_ADDR \
  106. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  107. #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  108. /* Size of malloc() pool */
  109. #define CONFIG_SYS_MALLOC_LEN SZ_32M
  110. /* Totally 6GB DDR */
  111. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  112. #define PHYS_SDRAM 0x40000000
  113. #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
  114. #define PHYS_SDRAM_2 0x100000000
  115. #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
  116. #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
  117. /* Monitor Command Prompt */
  118. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  119. #define CONFIG_SYS_CBSIZE 2048
  120. #define CONFIG_SYS_MAXARGS 64
  121. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  122. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  123. sizeof(CONFIG_SYS_PROMPT) + 16)
  124. #define CONFIG_FSL_USDHC
  125. #define CONFIG_SYS_FSL_USDHC_NUM 2
  126. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  127. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  128. #define CONFIG_SYS_I2C_SPEED 100000
  129. #endif