ls1028a.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <fsl_ddr.h>
  10. #include <net.h>
  11. #include <asm/io.h>
  12. #include <hwconfig.h>
  13. #include <fdt_support.h>
  14. #include <linux/libfdt.h>
  15. #include <env_internal.h>
  16. #include <asm/arch-fsl-layerscape/soc.h>
  17. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  18. #include <i2c.h>
  19. #include <asm/arch/soc.h>
  20. #ifdef CONFIG_FSL_LS_PPA
  21. #include <asm/arch/ppa.h>
  22. #endif
  23. #include <fsl_immap.h>
  24. #include <netdev.h>
  25. #include <fdtdec.h>
  26. #include <miiphy.h>
  27. #include "../common/qixis.h"
  28. #include "../drivers/net/fsl_enetc.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. int config_board_mux(void)
  31. {
  32. #ifndef CONFIG_LPUART
  33. #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  34. u8 reg;
  35. reg = QIXIS_READ(brdcfg[13]);
  36. /* Field| Function
  37. * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
  38. * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  39. * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
  40. * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  41. */
  42. reg &= ~(0xf0);
  43. reg |= 0xb0;
  44. QIXIS_WRITE(brdcfg[13], reg);
  45. reg = QIXIS_READ(brdcfg[15]);
  46. /* Field| Function
  47. * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  48. * CAN1 | 0= CAN #1 transceiver enabled
  49. * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  50. * CAN2 | 0= CAN #2 transceiver enabled
  51. */
  52. reg &= ~(0xc0);
  53. QIXIS_WRITE(brdcfg[15], reg);
  54. #endif
  55. #endif
  56. return 0;
  57. }
  58. #ifdef CONFIG_LPUART
  59. u32 get_lpuart_clk(void)
  60. {
  61. return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
  62. }
  63. #endif
  64. int board_init(void)
  65. {
  66. #ifdef CONFIG_ENV_IS_NOWHERE
  67. gd->env_addr = (ulong)&default_environment[0];
  68. #endif
  69. #ifdef CONFIG_FSL_CAAM
  70. sec_init();
  71. #endif
  72. #ifdef CONFIG_FSL_LS_PPA
  73. ppa_init();
  74. #endif
  75. #ifndef CONFIG_SYS_EARLY_PCI_INIT
  76. pci_init();
  77. #endif
  78. #if defined(CONFIG_TARGET_LS1028ARDB)
  79. u8 val = I2C_MUX_CH_DEFAULT;
  80. #ifndef CONFIG_DM_I2C
  81. i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  82. #else
  83. struct udevice *dev;
  84. if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  85. dm_i2c_write(dev, 0x0b, &val, 1);
  86. #endif
  87. #endif
  88. #if defined(CONFIG_TARGET_LS1028ARDB)
  89. u8 reg;
  90. reg = QIXIS_READ(brdcfg[4]);
  91. /*
  92. * Field | Function
  93. * 3 | DisplayPort Power Enable (net DP_PWR_EN):
  94. * DPPWR | 0= DP_PWR is enabled.
  95. */
  96. reg &= ~(DP_PWD_EN_DEFAULT_MASK);
  97. QIXIS_WRITE(brdcfg[4], reg);
  98. #endif
  99. return 0;
  100. }
  101. int board_eth_init(struct bd_info *bis)
  102. {
  103. return pci_eth_init(bis);
  104. }
  105. #ifdef CONFIG_MISC_INIT_R
  106. int misc_init_r(void)
  107. {
  108. config_board_mux();
  109. return 0;
  110. }
  111. #endif
  112. int board_early_init_f(void)
  113. {
  114. #ifdef CONFIG_LPUART
  115. u8 uart;
  116. #endif
  117. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  118. i2c_early_init_f();
  119. #endif
  120. fsl_lsch3_early_init_f();
  121. #ifdef CONFIG_LPUART
  122. /*
  123. * Field| Function
  124. * --------------------------------------------------------------
  125. * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
  126. * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
  127. * --------------------------------------------------------------
  128. * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
  129. * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
  130. */
  131. /* use lpuart0 as system console */
  132. uart = QIXIS_READ(brdcfg[13]);
  133. uart &= ~CFG_LPUART_MUX_MASK;
  134. uart |= CFG_LPUART_EN;
  135. QIXIS_WRITE(brdcfg[13], uart);
  136. #endif
  137. return 0;
  138. }
  139. void detail_board_ddr_info(void)
  140. {
  141. puts("\nDDR ");
  142. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  143. print_ddr_info(0);
  144. }
  145. int esdhc_status_fixup(void *blob, const char *compat)
  146. {
  147. void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
  148. char esdhc1_path[] = "/soc/mmc@2140000";
  149. char esdhc2_path[] = "/soc/mmc@2150000";
  150. char dspi1_path[] = "/soc/spi@2100000";
  151. char dspi2_path[] = "/soc/spi@2110000";
  152. u32 mux_sdhc1, mux_sdhc2;
  153. u32 io = 0;
  154. /*
  155. * The PMUX IO-expander for mux select is used to control
  156. * the muxing of various onboard interfaces.
  157. */
  158. io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
  159. mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
  160. /* Disable esdhc1/dspi1 if not selected. */
  161. if (mux_sdhc1 != 0)
  162. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  163. sizeof("disabled"), 1);
  164. if (mux_sdhc1 != 2)
  165. do_fixup_by_path(blob, dspi1_path, "status", "disabled",
  166. sizeof("disabled"), 1);
  167. io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
  168. mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
  169. /* Disable esdhc2/dspi2 if not selected. */
  170. if (mux_sdhc2 != 0)
  171. do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
  172. sizeof("disabled"), 1);
  173. if (mux_sdhc2 != 2)
  174. do_fixup_by_path(blob, dspi2_path, "status", "disabled",
  175. sizeof("disabled"), 1);
  176. return 0;
  177. }
  178. #ifdef CONFIG_OF_BOARD_SETUP
  179. int ft_board_setup(void *blob, struct bd_info *bd)
  180. {
  181. u64 base[CONFIG_NR_DRAM_BANKS];
  182. u64 size[CONFIG_NR_DRAM_BANKS];
  183. ft_cpu_setup(blob, bd);
  184. /* fixup DT for the two GPP DDR banks */
  185. base[0] = gd->bd->bi_dram[0].start;
  186. size[0] = gd->bd->bi_dram[0].size;
  187. base[1] = gd->bd->bi_dram[1].start;
  188. size[1] = gd->bd->bi_dram[1].size;
  189. #ifdef CONFIG_RESV_RAM
  190. /* reduce size if reserved memory is within this bank */
  191. if (gd->arch.resv_ram >= base[0] &&
  192. gd->arch.resv_ram < base[0] + size[0])
  193. size[0] = gd->arch.resv_ram - base[0];
  194. else if (gd->arch.resv_ram >= base[1] &&
  195. gd->arch.resv_ram < base[1] + size[1])
  196. size[1] = gd->arch.resv_ram - base[1];
  197. #endif
  198. fdt_fixup_memory_banks(blob, base, size, 2);
  199. fdt_fixup_icid(blob);
  200. #ifdef CONFIG_FSL_ENETC
  201. fdt_fixup_enetc_mac(blob);
  202. #endif
  203. return 0;
  204. }
  205. #endif
  206. #ifdef CONFIG_FSL_QIXIS
  207. int checkboard(void)
  208. {
  209. #ifdef CONFIG_TFABOOT
  210. enum boot_src src = get_boot_src();
  211. #endif
  212. u8 sw;
  213. int clock;
  214. char *board;
  215. char buf[64] = {0};
  216. static const char *freq[6] = {"100.00", "125.00", "156.25",
  217. "161.13", "322.26", "100.00 SS"};
  218. cpu_name(buf);
  219. /* find the board details */
  220. sw = QIXIS_READ(id);
  221. switch (sw) {
  222. case 0x46:
  223. board = "QDS";
  224. break;
  225. case 0x47:
  226. board = "RDB";
  227. break;
  228. case 0x49:
  229. board = "HSSI";
  230. break;
  231. default:
  232. board = "unknown";
  233. break;
  234. }
  235. sw = QIXIS_READ(arch);
  236. printf("Board: %s-%s, Version: %c, boot from ",
  237. buf, board, (sw & 0xf) + 'A' - 1);
  238. sw = QIXIS_READ(brdcfg[0]);
  239. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  240. #ifdef CONFIG_TFABOOT
  241. if (src == BOOT_SOURCE_SD_MMC) {
  242. puts("SD\n");
  243. } else if (src == BOOT_SOURCE_SD_MMC2) {
  244. puts("eMMC\n");
  245. } else {
  246. #endif
  247. #ifdef CONFIG_SD_BOOT
  248. puts("SD\n");
  249. #elif defined(CONFIG_EMMC_BOOT)
  250. puts("eMMC\n");
  251. #else
  252. switch (sw) {
  253. case 0:
  254. case 4:
  255. printf("NOR\n");
  256. break;
  257. case 1:
  258. printf("NAND\n");
  259. break;
  260. default:
  261. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  262. break;
  263. }
  264. #endif
  265. #ifdef CONFIG_TFABOOT
  266. }
  267. #endif
  268. printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
  269. puts("SERDES1 Reference : ");
  270. sw = QIXIS_READ(brdcfg[2]);
  271. #ifdef CONFIG_TARGET_LS1028ARDB
  272. clock = (sw >> 6) & 3;
  273. #else
  274. clock = (sw >> 4) & 0xf;
  275. #endif
  276. printf("Clock1 = %sMHz ", freq[clock]);
  277. #ifdef CONFIG_TARGET_LS1028ARDB
  278. clock = (sw >> 4) & 3;
  279. #else
  280. clock = sw & 0xf;
  281. #endif
  282. printf("Clock2 = %sMHz\n", freq[clock]);
  283. return 0;
  284. }
  285. #endif