README 5.3 KB

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  1. Overview
  2. --------
  3. The LS1028A Reference Design (RDB) is a high-performance computing,
  4. evaluation, and development platform that supports ARM SoC LS1028A and its
  5. derivatives.
  6. LS1028A SoC Overview
  7. --------------------------------------
  8. Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
  9. RDB Default Switch Settings (1: ON; 0: OFF)
  10. -------------------------------------------
  11. For XSPI NOR boot (default)
  12. SW2: 1111_1000
  13. SW3: 1111_0000
  14. SW5: 0011_1001
  15. For SD Boot
  16. SW2: 1000_1000
  17. SW3: 1111_0000
  18. SW5: 0011_1001
  19. For eMMC Boot
  20. SW2: 1001_1000
  21. SW3: 1111_0000
  22. SW5: 0011_1001
  23. LS1028ARDB board Overview
  24. -------------------------
  25. Processor
  26. Two Arm Cortex- A72 processor cores:
  27. - Based on 64-bit ARMv8 architecture
  28. - Up to 1.3 GHz operation
  29. - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
  30. data cache
  31. - Arranged as a single cluster of two cores sharing a single 1 MB L2
  32. cache
  33. DDR memory
  34. - Five onboard 1G x8 discrete memory modules (Four data byte lanes
  35. ECC)
  36. - 32-bit data and 4-bit ECC
  37. - One chip select
  38. - Data transfer rates of up to 1.6 GT/s
  39. - Single-bit error correction and double-bit error detection ECC (4-bit
  40. check word across 32-bit data)
  41. High-speed serial ports(SerDes)
  42. - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
  43. Qualcomm AR8033 PHY
  44. - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
  45. through the NXP F104S8A PHY
  46. - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
  47. (8 Gbit/s) cards
  48. - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
  49. slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
  50. SATA Gen 3 cards (6 Gbit/s) at a time
  51. eSDHC
  52. - eSDHC1, eSDHC2
  53. SPI
  54. - Connects to two mikroBUS sockets to support mikro-click modules,
  55. such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
  56. field communications (NFC) controller
  57. Octal SPI (XSPI)
  58. - One 256 MB onboard XSPI serial NOR flash memory
  59. - One 512 MB onboard XSPI serial NAND flash memory
  60. - Supports a QSPI emulator for offboard QSPI emulation
  61. I2C
  62. - All system devices are accessed via I2C1, which is multiplexed on
  63. I2C multiplexer PCA9848 to isolate address conflicts and reduce
  64. capacitive load
  65. - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
  66. thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
  67. 1 and 2
  68. CAN
  69. - The two CAN DB9 ports can support CAN FD fast phase at data rates of
  70. up to 5 Mbit/s
  71. Serial audio interface(SAI)
  72. - Audio codec SGTL5000 provides headphone and audio LINEOUT for
  73. stereo speakers
  74. - IEEE1588 interface to support audio on SAI4
  75. QDS Default Switch Settings (1: ON; 0: OFF)
  76. -------------------------------------------
  77. For SD Boot
  78. SW1 : 1000_0000
  79. SW2 : 1110_0110
  80. SW3 : 0000_0010
  81. SW4 : 0000_0000
  82. SW5 : 0000_0000
  83. SW6 : 0000_0000
  84. SW7 : 1111_0011
  85. SW8 : 1110_0000
  86. SW9 : 1000_0001
  87. SW10: 1110_0000
  88. For XSPI Boot
  89. SW1 : 1111_0000
  90. SW2 : 0000_0110
  91. SW3 : 0000_0010
  92. SW4 : 0000_0000
  93. SW5 : 0110_0000
  94. SW6 : 0101_0000
  95. SW7 : 1111_0011
  96. SW8 : 1110_0000
  97. SW9 : 1000_0000
  98. SW10: 1110_0000
  99. LS1028AQDS board Overview
  100. -------------------------
  101. Processor
  102. Two Arm Cortex- A72 processor cores:
  103. - Based on 64-bit ARMv8 architecture
  104. - Up to 1.3 GHz operation
  105. - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
  106. data cache
  107. - Arranged as a single cluster of two cores sharing a single 1 MB L2
  108. cache
  109. DDR memory
  110. - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
  111. - Supports a single- or dual-ranked SODIMM or UDIMM connector
  112. - 32-bit data and 4-bit ECC
  113. - Supports x8/x16 devices
  114. - Supports ECC error detection and correction
  115. - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
  116. all devices in case of DDR3L or DDR4, respectively. Power can
  117. switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
  118. DDR4 devices, respectively
  119. SerDes (Serializer/Deserializer)
  120. - Four-lane (0-3) SerDes:
  121. - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
  122. Gbit SXGMII, 1 Gbit SGMII
  123. - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
  124. SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
  125. - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
  126. SGMII
  127. - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
  128. SGMII, SATA 2.0/3.0
  129. - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
  130. add-in cards
  131. - Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
  132. lane 2 (TX lines) connects to an SMA connector
  133. Lane 3 connects to 1x7 header to support SATA devices
  134. eSDHC
  135. - eSDHC1, eSDHC2
  136. SPI
  137. - SPI1 and SPI2 support three onboard SPI flash memory devices:
  138. 512 Mbit high-speed flash (with speed of up to 108/54 MHz)
  139. memory for storage
  140. 4 Mbit low-speed flash memory (with speed of up to 40 MHz)
  141. 64 Mbit high-speed flash memory (with speed of up to 104/80
  142. MHz)
  143. - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
  144. up to 104/80 MHz)
  145. - All memories operate at 1.8 V
  146. - A header is provided on SPI1 to test SPI slave mode
  147. I2C
  148. - LS1028A supports eight I2C controllers
  149. Serial audio interface(SAI)
  150. Two SAI ports with audio codec SGTL5000:
  151. - Include stereo LINEIN with support for external analog input
  152. - Provide headphone and line output
  153. Display
  154. - DisplayPort connector to connect the DP data to a 4K display device
  155. (computer monitor)
  156. - eDP connector to connect the DP data to a 4K display panel