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platform: Add OpenPiton platform support

OpenPiton is a research platform from Princeton University [1].

"OpenPiton is the world's first open source, general purpose,
multithreaded manycore processor. It is a tiled manycore
framework scalable from one to 1/2 billion cores."

Add OpenSBI support for OpenPiton. As it is based on ariane core,
it reuses the platform code from arine project.

[1]. https://github.com/PrincetonUniversity/openpiton

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Atish Patra 4 years ago
parent
commit
fb84879e66

+ 33 - 0
docs/platform/fpga-openpiton.md

@@ -0,0 +1,33 @@
+OpenPiton FPGA SoC Platform
+========================
+OpenPiton is the world's first open source, general purpose, multithreaded
+manycore processor. It is a tiled manycore framework scalable from one to
+1/2 billion cores. Currently, OpenPiton supports the 64bit Ariane RISC-V
+processor from ETH Zurich. To this end, Ariane has been equipped with a
+different L1 cache subsystem that follows a write-through protocol and that has
+support for cache invalidations and atomics.
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=fpga/openpiton* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *OpenPiton* platform does not have any platform-specific options.
+
+Building Ariane FPGA Platform
+-----------------------------
+
+**Linux Kernel Payload**
+
+```
+make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+```
+
+Booting Ariane FPGA Platform
+----------------------------
+
+**Linux Kernel Payload**
+
+As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will
+directly boot into Linux directly after powered on.

+ 4 - 0
docs/platform/platform.md

@@ -25,6 +25,9 @@ OpenSBI currently supports the following virtual and hardware platforms:
 
 
 * **Spike**: Platform support for the Spike emulator.
 * **Spike**: Platform support for the Spike emulator.
 
 
+* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based on
+ariane core.
+
 The code for these supported platforms can be used as example to implement
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
 support for other platforms. The *platform/template* directory also provides
 template files for implementing support for a new platform. The *object.mk*,
 template files for implementing support for a new platform. The *object.mk*,
@@ -37,3 +40,4 @@ facilitate the implementation.
 [andes_ae350.md]: andes-ae350.md
 [andes_ae350.md]: andes-ae350.md
 [thead-c910.md]: thead-c910.md
 [thead-c910.md]: thead-c910.md
 [spike.md]: spike.md
 [spike.md]: spike.md
+[fpga_openpiton.md]: fpga_openpiton.md

+ 35 - 0
platform/fpga/openpiton/config.mk

@@ -0,0 +1,35 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2020 Western Digital Corporation or its affiliates.
+#
+
+#for more infos, check out /platform/template/config.mk
+
+PLATFORM_RISCV_XLEN = 64
+
+# Blobs to build
+FW_TEXT_START=0x80000000
+FW_JUMP=n
+
+ifeq ($(PLATFORM_RISCV_XLEN), 32)
+ # This needs to be 4MB aligned for 32-bit support
+ FW_JUMP_ADDR=0x80400000
+ else
+ # This needs to be 2MB aligned for 64-bit support
+ FW_JUMP_ADDR=0x80200000
+ endif
+FW_JUMP_FDT_ADDR=0x82200000
+
+# Firmware with payload configuration.
+FW_PAYLOAD=y
+
+ifeq ($(PLATFORM_RISCV_XLEN), 32)
+# This needs to be 4MB aligned for 32-bit support
+  FW_PAYLOAD_OFFSET=0x400000
+else
+# This needs to be 2MB aligned for 64-bit support
+  FW_PAYLOAD_OFFSET=0x200000
+endif
+FW_PAYLOAD_FDT_ADDR=0x82200000
+FW_PAYLOAD_ALIGN=0x1000

+ 7 - 0
platform/fpga/openpiton/objects.mk

@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2020 Western Digital Corporation or its affiliates.
+#
+
+platform-objs-y += platform.o

+ 200 - 0
platform/fpga/openpiton/platform.c

@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_platform.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/plic.h>
+#include <sbi_utils/serial/uart8250.h>
+#include <sbi_utils/sys/clint.h>
+
+#define OPENPITON_UART_ADDR			0xfff0c2c000
+#define OPENPITON_UART_FREQ			60000000
+#define OPENPITON_UART_BAUDRATE			115200
+#define OPENPITON_UART_REG_SHIFT		0
+#define OPENPITON_UART_REG_WIDTH		1
+#define OPENPITON_PLIC_ADDR			0xfff1100000
+#define OPENPITON_PLIC_NUM_SOURCES		2
+#define OPENPITON_HART_COUNT			3
+#define OPENPITON_CLINT_ADDR			0xfff1020000
+
+#define SBI_OPENPITON_FEATURES	\
+	(SBI_PLATFORM_HAS_TIMER_VALUE | \
+	 SBI_PLATFORM_HAS_SCOUNTEREN | \
+	 SBI_PLATFORM_HAS_MCOUNTEREN | \
+	 SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
+
+/*
+ * OpenPiton platform early initialization.
+ */
+static int openpiton_early_init(bool cold_boot)
+{
+	/* For now nothing to do. */
+	return 0;
+}
+
+/*
+ * OpenPiton platform final initialization.
+ */
+static int openpiton_final_init(bool cold_boot)
+{
+	void *fdt;
+
+	if (!cold_boot)
+		return 0;
+
+	fdt = sbi_scratch_thishart_arg1_ptr();
+	fdt_fixups(fdt);
+
+	return 0;
+}
+
+/*
+ * Initialize the openpiton console.
+ */
+static int openpiton_console_init(void)
+{
+	return uart8250_init(OPENPITON_UART_ADDR,
+			     OPENPITON_UART_FREQ,
+			     OPENPITON_UART_BAUDRATE,
+			     OPENPITON_UART_REG_SHIFT,
+			     OPENPITON_UART_REG_WIDTH);
+}
+
+static int plic_openpiton_warm_irqchip_init(u32 target_hart,
+			   int m_cntx_id, int s_cntx_id)
+{
+	size_t i, ie_words = OPENPITON_PLIC_NUM_SOURCES / 32 + 1;
+
+	if (target_hart >= OPENPITON_HART_COUNT)
+		return -1;
+	/* By default, enable all IRQs for M-mode of target HART */
+	if (m_cntx_id > -1) {
+		for (i = 0; i < ie_words; i++)
+			plic_set_ie(m_cntx_id, i, 1);
+	}
+	/* Enable all IRQs for S-mode of target HART */
+	if (s_cntx_id > -1) {
+		for (i = 0; i < ie_words; i++)
+			plic_set_ie(s_cntx_id, i, 1);
+	}
+	/* By default, enable M-mode threshold */
+	if (m_cntx_id > -1)
+		plic_set_thresh(m_cntx_id, 1);
+	/* By default, disable S-mode threshold */
+	if (s_cntx_id > -1)
+		plic_set_thresh(s_cntx_id, 0);
+
+	return 0;
+}
+
+/*
+ * Initialize the openpiton interrupt controller for current HART.
+ */
+static int openpiton_irqchip_init(bool cold_boot)
+{
+	u32 hartid = current_hartid();
+	int ret;
+
+	if (cold_boot) {
+		ret = plic_cold_irqchip_init(OPENPITON_PLIC_ADDR,
+					     OPENPITON_PLIC_NUM_SOURCES,
+					     OPENPITON_HART_COUNT);
+		if (ret)
+			return ret;
+	}
+	return plic_openpiton_warm_irqchip_init(hartid,
+					2 * hartid, 2 * hartid + 1);
+}
+
+/*
+ * Initialize IPI for current HART.
+ */
+static int openpiton_ipi_init(bool cold_boot)
+{
+	int ret;
+
+	if (cold_boot) {
+		ret = clint_cold_ipi_init(OPENPITON_CLINT_ADDR,
+					  OPENPITON_HART_COUNT);
+		if (ret)
+			return ret;
+	}
+
+	return clint_warm_ipi_init();
+}
+
+/*
+ * Initialize openpiton timer for current HART.
+ */
+static int openpiton_timer_init(bool cold_boot)
+{
+	int ret;
+
+	if (cold_boot) {
+		ret = clint_cold_timer_init(OPENPITON_CLINT_ADDR,
+					    OPENPITON_HART_COUNT, TRUE);
+		if (ret)
+			return ret;
+	}
+
+	return clint_warm_timer_init();
+}
+
+/*
+ * Reboot the openpiton.
+ */
+static int openpiton_system_reboot(u32 type)
+{
+	/* For now nothing to do. */
+	sbi_printf("System reboot\n");
+	return 0;
+}
+
+/*
+ * Shutdown or poweroff the openpiton.
+ */
+static int openpiton_system_shutdown(u32 type)
+{
+	/* For now nothing to do. */
+	sbi_printf("System shutdown\n");
+	return 0;
+}
+
+/*
+ * Platform descriptor.
+ */
+const struct sbi_platform_operations platform_ops = {
+	.early_init = openpiton_early_init,
+	.final_init = openpiton_final_init,
+	.console_init = openpiton_console_init,
+	.console_putc = uart8250_putc,
+	.console_getc = uart8250_getc,
+	.irqchip_init = openpiton_irqchip_init,
+	.ipi_init = openpiton_ipi_init,
+	.ipi_send = clint_ipi_send,
+	.ipi_clear = clint_ipi_clear,
+	.timer_init = openpiton_timer_init,
+	.timer_value = clint_timer_value,
+	.timer_event_start = clint_timer_event_start,
+	.timer_event_stop = clint_timer_event_stop,
+	.system_reboot = openpiton_system_reboot,
+	.system_shutdown = openpiton_system_shutdown
+};
+
+const struct sbi_platform platform = {
+	.opensbi_version = OPENSBI_VERSION,
+	.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
+	.name = "OPENPITON RISC-V",
+	.features = SBI_OPENPITON_FEATURES,
+	.hart_count = OPENPITON_HART_COUNT,
+	.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
+	.platform_ops_addr = (unsigned long)&platform_ops
+};

+ 1 - 0
scripts/create-binary-archive.sh

@@ -93,6 +93,7 @@ case "${BUILD_RISCV_XLEN}" in
 	BUILD_PLATFORM_SUBDIR+=("sifive/fu540")
 	BUILD_PLATFORM_SUBDIR+=("sifive/fu540")
 	BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
 	BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
 	BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
 	BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
+	BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
 	BUILD_PLATFORM_SUBDIR+=("andes/ae350")
 	BUILD_PLATFORM_SUBDIR+=("andes/ae350")
 	BUILD_PLATFORM_SUBDIR+=("thead/c910")
 	BUILD_PLATFORM_SUBDIR+=("thead/c910")
 	BUILD_PLATFORM_SUBDIR+=("spike")
 	BUILD_PLATFORM_SUBDIR+=("spike")