platform.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200
  1. // SPDX-License-Identifier: BSD-2-Clause
  2. /*
  3. * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  4. */
  5. #include <sbi/riscv_asm.h>
  6. #include <sbi/riscv_encoding.h>
  7. #include <sbi/riscv_io.h>
  8. #include <sbi/sbi_console.h>
  9. #include <sbi/sbi_const.h>
  10. #include <sbi/sbi_hart.h>
  11. #include <sbi/sbi_platform.h>
  12. #include <sbi_utils/fdt/fdt_helper.h>
  13. #include <sbi_utils/irqchip/plic.h>
  14. #include <sbi_utils/serial/uart8250.h>
  15. #include <sbi_utils/sys/clint.h>
  16. #define OPENPITON_UART_ADDR 0xfff0c2c000
  17. #define OPENPITON_UART_FREQ 60000000
  18. #define OPENPITON_UART_BAUDRATE 115200
  19. #define OPENPITON_UART_REG_SHIFT 0
  20. #define OPENPITON_UART_REG_WIDTH 1
  21. #define OPENPITON_PLIC_ADDR 0xfff1100000
  22. #define OPENPITON_PLIC_NUM_SOURCES 2
  23. #define OPENPITON_HART_COUNT 3
  24. #define OPENPITON_CLINT_ADDR 0xfff1020000
  25. #define SBI_OPENPITON_FEATURES \
  26. (SBI_PLATFORM_HAS_TIMER_VALUE | \
  27. SBI_PLATFORM_HAS_SCOUNTEREN | \
  28. SBI_PLATFORM_HAS_MCOUNTEREN | \
  29. SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
  30. /*
  31. * OpenPiton platform early initialization.
  32. */
  33. static int openpiton_early_init(bool cold_boot)
  34. {
  35. /* For now nothing to do. */
  36. return 0;
  37. }
  38. /*
  39. * OpenPiton platform final initialization.
  40. */
  41. static int openpiton_final_init(bool cold_boot)
  42. {
  43. void *fdt;
  44. if (!cold_boot)
  45. return 0;
  46. fdt = sbi_scratch_thishart_arg1_ptr();
  47. fdt_fixups(fdt);
  48. return 0;
  49. }
  50. /*
  51. * Initialize the openpiton console.
  52. */
  53. static int openpiton_console_init(void)
  54. {
  55. return uart8250_init(OPENPITON_UART_ADDR,
  56. OPENPITON_UART_FREQ,
  57. OPENPITON_UART_BAUDRATE,
  58. OPENPITON_UART_REG_SHIFT,
  59. OPENPITON_UART_REG_WIDTH);
  60. }
  61. static int plic_openpiton_warm_irqchip_init(u32 target_hart,
  62. int m_cntx_id, int s_cntx_id)
  63. {
  64. size_t i, ie_words = OPENPITON_PLIC_NUM_SOURCES / 32 + 1;
  65. if (target_hart >= OPENPITON_HART_COUNT)
  66. return -1;
  67. /* By default, enable all IRQs for M-mode of target HART */
  68. if (m_cntx_id > -1) {
  69. for (i = 0; i < ie_words; i++)
  70. plic_set_ie(m_cntx_id, i, 1);
  71. }
  72. /* Enable all IRQs for S-mode of target HART */
  73. if (s_cntx_id > -1) {
  74. for (i = 0; i < ie_words; i++)
  75. plic_set_ie(s_cntx_id, i, 1);
  76. }
  77. /* By default, enable M-mode threshold */
  78. if (m_cntx_id > -1)
  79. plic_set_thresh(m_cntx_id, 1);
  80. /* By default, disable S-mode threshold */
  81. if (s_cntx_id > -1)
  82. plic_set_thresh(s_cntx_id, 0);
  83. return 0;
  84. }
  85. /*
  86. * Initialize the openpiton interrupt controller for current HART.
  87. */
  88. static int openpiton_irqchip_init(bool cold_boot)
  89. {
  90. u32 hartid = current_hartid();
  91. int ret;
  92. if (cold_boot) {
  93. ret = plic_cold_irqchip_init(OPENPITON_PLIC_ADDR,
  94. OPENPITON_PLIC_NUM_SOURCES,
  95. OPENPITON_HART_COUNT);
  96. if (ret)
  97. return ret;
  98. }
  99. return plic_openpiton_warm_irqchip_init(hartid,
  100. 2 * hartid, 2 * hartid + 1);
  101. }
  102. /*
  103. * Initialize IPI for current HART.
  104. */
  105. static int openpiton_ipi_init(bool cold_boot)
  106. {
  107. int ret;
  108. if (cold_boot) {
  109. ret = clint_cold_ipi_init(OPENPITON_CLINT_ADDR,
  110. OPENPITON_HART_COUNT);
  111. if (ret)
  112. return ret;
  113. }
  114. return clint_warm_ipi_init();
  115. }
  116. /*
  117. * Initialize openpiton timer for current HART.
  118. */
  119. static int openpiton_timer_init(bool cold_boot)
  120. {
  121. int ret;
  122. if (cold_boot) {
  123. ret = clint_cold_timer_init(OPENPITON_CLINT_ADDR,
  124. OPENPITON_HART_COUNT, TRUE);
  125. if (ret)
  126. return ret;
  127. }
  128. return clint_warm_timer_init();
  129. }
  130. /*
  131. * Reboot the openpiton.
  132. */
  133. static int openpiton_system_reboot(u32 type)
  134. {
  135. /* For now nothing to do. */
  136. sbi_printf("System reboot\n");
  137. return 0;
  138. }
  139. /*
  140. * Shutdown or poweroff the openpiton.
  141. */
  142. static int openpiton_system_shutdown(u32 type)
  143. {
  144. /* For now nothing to do. */
  145. sbi_printf("System shutdown\n");
  146. return 0;
  147. }
  148. /*
  149. * Platform descriptor.
  150. */
  151. const struct sbi_platform_operations platform_ops = {
  152. .early_init = openpiton_early_init,
  153. .final_init = openpiton_final_init,
  154. .console_init = openpiton_console_init,
  155. .console_putc = uart8250_putc,
  156. .console_getc = uart8250_getc,
  157. .irqchip_init = openpiton_irqchip_init,
  158. .ipi_init = openpiton_ipi_init,
  159. .ipi_send = clint_ipi_send,
  160. .ipi_clear = clint_ipi_clear,
  161. .timer_init = openpiton_timer_init,
  162. .timer_value = clint_timer_value,
  163. .timer_event_start = clint_timer_event_start,
  164. .timer_event_stop = clint_timer_event_stop,
  165. .system_reboot = openpiton_system_reboot,
  166. .system_shutdown = openpiton_system_shutdown
  167. };
  168. const struct sbi_platform platform = {
  169. .opensbi_version = OPENSBI_VERSION,
  170. .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
  171. .name = "OPENPITON RISC-V",
  172. .features = SBI_OPENPITON_FEATURES,
  173. .hart_count = OPENPITON_HART_COUNT,
  174. .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
  175. .platform_ops_addr = (unsigned long)&platform_ops
  176. };