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@@ -0,0 +1,144 @@
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+/*
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+ * SPDX-License-Identifier: BSD-2-Clause
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+ *
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+ * Copyright (c) Nuclei Corporation or its affiliates.
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+ *
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+ * Authors:
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+ * lujun <lujun@nucleisys.com>
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+ * hqfang <578567190@qq.com>
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+ */
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+
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+#include <libfdt.h>
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+#include <sbi/riscv_asm.h>
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+#include <sbi/riscv_io.h>
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+#include <sbi/riscv_encoding.h>
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+#include <sbi/sbi_console.h>
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+#include <sbi/sbi_const.h>
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+#include <sbi/sbi_platform.h>
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+#include <sbi_utils/fdt/fdt_fixup.h>
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+#include <sbi_utils/irqchip/plic.h>
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+#include <sbi_utils/serial/sifive-uart.h>
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+#include <sbi_utils/sys/clint.h>
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+
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+/* clang-format off */
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+
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+#define UX600_HART_COUNT 1
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+
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+#define UX600_SYS_CLK 1000000000
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+
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+/* Nuclei timer base address */
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+#define UX600_NUCLEI_TIMER_ADDR 0x2000000
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+/* The clint compatiable timer offset is 0x1000 against nuclei timer */
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+#define UX600_CLINT_TIMER_ADDR (UX600_NUCLEI_TIMER_ADDR + 0x1000)
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+
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+#define UX600_PLIC_ADDR 0x8000000
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+#define UX600_PLIC_NUM_SOURCES 0x35
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+#define UX600_PLIC_NUM_PRIORITIES 7
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+
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+#define UX600_UART0_ADDR 0x10013000
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+#define UX600_UART1_ADDR 0x10023000
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+
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+#define UX600_DEBUG_UART UX600_UART0_ADDR
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+#define UX600_UART_BAUDRATE 115200
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+
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+/* clang-format on */
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+
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+static void ux600_modify_dt(void *fdt)
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+{
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+ fdt_fixups(fdt);
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+}
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+
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+static int ux600_final_init(bool cold_boot)
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+{
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+ void *fdt;
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+
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+ if (!cold_boot)
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+ return 0;
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+
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+ fdt = sbi_scratch_thishart_arg1_ptr();
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+ ux600_modify_dt(fdt);
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+
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+ return 0;
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+}
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+
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+static int ux600_console_init(void)
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+{
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+ return sifive_uart_init(UX600_DEBUG_UART, UX600_SYS_CLK,
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+ UX600_UART_BAUDRATE);
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+}
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+
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+static int ux600_irqchip_init(bool cold_boot)
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+{
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+ int rc;
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+ u32 hartid = current_hartid();
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+
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+ if (cold_boot) {
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+ rc = plic_cold_irqchip_init(UX600_PLIC_ADDR,
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+ UX600_PLIC_NUM_SOURCES,
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+ UX600_HART_COUNT);
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+ if (rc)
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+ return rc;
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+ }
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+
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+ return plic_warm_irqchip_init(hartid, (hartid) ? (2 * hartid - 1) : 0,
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+ (hartid) ? (2 * hartid) : -1);
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+}
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+
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+static int ux600_ipi_init(bool cold_boot)
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+{
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+ int rc;
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+
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+ if (cold_boot) {
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+ rc = clint_cold_ipi_init(UX600_CLINT_TIMER_ADDR, UX600_HART_COUNT);
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+ if (rc)
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+ return rc;
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+ }
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+
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+ return clint_warm_ipi_init();
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+}
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+
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+static int ux600_timer_init(bool cold_boot)
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+{
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+ int rc;
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+
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+ if (cold_boot) {
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+ rc = clint_cold_timer_init(UX600_CLINT_TIMER_ADDR,
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+ UX600_HART_COUNT, TRUE);
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+ if (rc)
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+ return rc;
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+ }
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+
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+ return clint_warm_timer_init();
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+}
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+
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+static int ux600_system_reset(u32 type)
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+{
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+ /* For now nothing to do. */
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+ return 0;
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+}
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+
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+const struct sbi_platform_operations platform_ops = {
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+ .final_init = ux600_final_init,
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+ .console_putc = sifive_uart_putc,
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+ .console_getc = sifive_uart_getc,
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+ .console_init = ux600_console_init,
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+ .irqchip_init = ux600_irqchip_init,
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+ .ipi_send = clint_ipi_send,
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+ .ipi_clear = clint_ipi_clear,
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+ .ipi_init = ux600_ipi_init,
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+ .timer_value = clint_timer_value,
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+ .timer_event_stop = clint_timer_event_stop,
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+ .timer_event_start = clint_timer_event_start,
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+ .timer_init = ux600_timer_init,
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+ .system_reset = ux600_system_reset
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+};
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+
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+const struct sbi_platform platform = {
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+ .opensbi_version = OPENSBI_VERSION,
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+ .platform_version = SBI_PLATFORM_VERSION(0x0U, 0x01U),
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+ .name = "Nuclei UX600",
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+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
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+ .hart_count = UX600_HART_COUNT,
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+ .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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+ .platform_ops_addr = (unsigned long)&platform_ops
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+};
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