0013-RISC-V-Hypervisor-ext-support-Privileged-Spec-1.12.patch 26 KB

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  1. From 34b95485ed2e4c553071fcbb88a0011bcb041e34 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Mon, 17 Jan 2022 13:19:43 +0800
  4. Subject: [PATCH 13/14] RISC-V: Hypervisor ext: support Privileged Spec 1.12
  5. - Hypervisor Memory-Management Instructions
  6. HFENCE.VVMA, HFENCE.GVMA,
  7. - Hypervisor Virtual Machine Load and Store Instructions
  8. HLV.B, HLV.BU, HSV.B,
  9. HLV.H, HLV.HU, HLVX.HU, HSB.H,
  10. HLV.W, HLV.WU, HLVX.WU, HSV.W,
  11. HLV.D, HSV.D
  12. - Hypervisor CSRs (some new, some address changed)
  13. hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
  14. htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
  15. vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp,
  16. changed from https://patches-gcc.linaro.org/patch/65621/
  17. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  18. ---
  19. bfd/cpu-riscv.c | 1 +
  20. bfd/cpu-riscv.h | 1 +
  21. gas/config/tc-riscv.c | 4 +-
  22. gas/testsuite/gas/riscv/h-ext-32.d | 74 ++++++++++++++++++++
  23. gas/testsuite/gas/riscv/h-ext-32.s | 64 +++++++++++++++++
  24. gas/testsuite/gas/riscv/h-ext-64.d | 73 +++++++++++++++++++
  25. gas/testsuite/gas/riscv/h-ext-64.s | 63 +++++++++++++++++
  26. gas/testsuite/gas/riscv/svinval-and-h.d | 15 ++++
  27. gas/testsuite/gas/riscv/svinval-and-h.s | 5 ++
  28. include/opcode/riscv-opc.h | 93 +++++++++++++++++++++++++
  29. include/opcode/riscv.h | 3 +-
  30. opcodes/riscv-opc.c | 21 ++++++
  31. 12 files changed, 415 insertions(+), 2 deletions(-)
  32. create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d
  33. create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s
  34. create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d
  35. create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s
  36. create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.d
  37. create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.s
  38. diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
  39. index 025e94afd3..182f389e57 100644
  40. --- a/bfd/cpu-riscv.c
  41. +++ b/bfd/cpu-riscv.c
  42. @@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] =
  43. {"1.9.1", PRIV_SPEC_CLASS_1P9P1},
  44. {"1.10", PRIV_SPEC_CLASS_1P10},
  45. {"1.11", PRIV_SPEC_CLASS_1P11},
  46. + {"1.12", PRIV_SPEC_CLASS_1P12},
  47. };
  48. /* Get the corresponding CSR version class by giving privilege
  49. diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h
  50. index cafaca23be..4d111ab797 100644
  51. --- a/bfd/cpu-riscv.h
  52. +++ b/bfd/cpu-riscv.h
  53. @@ -32,6 +32,7 @@ enum riscv_spec_class
  54. PRIV_SPEC_CLASS_1P9P1,
  55. PRIV_SPEC_CLASS_1P10,
  56. PRIV_SPEC_CLASS_1P11,
  57. + PRIV_SPEC_CLASS_1P12,
  58. PRIV_SPEC_CLASS_DRAFT,
  59. };
  60. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  61. index d473743019..fca5c8949d 100644
  62. --- a/gas/config/tc-riscv.c
  63. +++ b/gas/config/tc-riscv.c
  64. @@ -360,6 +360,8 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  65. || riscv_subset_supports ("zvamo")));
  66. case INSN_CLASS_V_OR_ZVLSSEG:
  67. return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
  68. + case INSN_CLASS_H:
  69. + return riscv_subset_supports ("i");
  70. default:
  71. as_fatal ("internal: unreachable");
  72. return false;
  73. @@ -4365,4 +4367,4 @@ riscv_pop_insert (void)
  74. extern void pop_insert (const pseudo_typeS *);
  75. pop_insert (riscv_pseudo_table);
  76. -}
  77. \ No newline at end of file
  78. +}
  79. diff --git a/gas/testsuite/gas/riscv/h-ext-32.d b/gas/testsuite/gas/riscv/h-ext-32.d
  80. new file mode 100644
  81. index 0000000000..e851fac500
  82. --- /dev/null
  83. +++ b/gas/testsuite/gas/riscv/h-ext-32.d
  84. @@ -0,0 +1,74 @@
  85. +#as: -march=rv32g -mpriv-spec=1.12
  86. +#source: h-ext-32.s
  87. +#objdump: -d
  88. +
  89. +.*:[ ]+file format .*
  90. +
  91. +
  92. +Disassembly of section .text:
  93. +
  94. +0+000 <.text>:
  95. +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
  96. +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
  97. +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\)
  98. +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\)
  99. +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\)
  100. +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\)
  101. +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\)
  102. +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\)
  103. +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
  104. +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
  105. +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\)
  106. +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\)
  107. +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus
  108. +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1
  109. +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg
  110. +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1
  111. +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg
  112. +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1
  113. +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie
  114. +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1
  115. +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren
  116. +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1
  117. +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie
  118. +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1
  119. +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval
  120. +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1
  121. +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip
  122. +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1
  123. +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip
  124. +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1
  125. +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst
  126. +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1
  127. +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip
  128. +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1
  129. +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg
  130. +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1
  131. +[ ]+[0-9a-f]+:[ ]+61a02573[ ]+csrr[ ]+a0,henvcfgh
  132. +[ ]+[0-9a-f]+:[ ]+61a59073[ ]+csrw[ ]+henvcfgh,a1
  133. +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp
  134. +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1
  135. +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext
  136. +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1
  137. +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta
  138. +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1
  139. +[ ]+[0-9a-f]+:[ ]+61502573[ ]+csrr[ ]+a0,htimedeltah
  140. +[ ]+[0-9a-f]+:[ ]+61559073[ ]+csrw[ ]+htimedeltah,a1
  141. +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus
  142. +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1
  143. +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie
  144. +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1
  145. +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
  146. +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1
  147. +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
  148. +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1
  149. +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
  150. +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1
  151. +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause
  152. +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1
  153. +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval
  154. +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1
  155. +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip
  156. +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
  157. +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
  158. +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
  159. diff --git a/gas/testsuite/gas/riscv/h-ext-32.s b/gas/testsuite/gas/riscv/h-ext-32.s
  160. new file mode 100644
  161. index 0000000000..c3ab5bb592
  162. --- /dev/null
  163. +++ b/gas/testsuite/gas/riscv/h-ext-32.s
  164. @@ -0,0 +1,64 @@
  165. + hlv.b a0, (a1)
  166. + hlv.b a0,0(a1)
  167. + hlv.bu a0, (a1)
  168. + hlv.h a1, (a2)
  169. + hlv.hu a1, (a1)
  170. + hlvx.hu a1, (a2)
  171. + hlv.w a2, (a2)
  172. + hlvx.wu a2, (a3)
  173. + hsv.b a0, (a1)
  174. + hsv.b a0,0(a1)
  175. + hsv.h a0, (a1)
  176. + hsv.w a0, (a1)
  177. + csrr a0, hstatus
  178. + csrw hstatus, a1
  179. + csrr a0, hedeleg
  180. + csrw hedeleg, a1
  181. + csrr a0, hideleg
  182. + csrw hideleg, a1
  183. + csrr a0, hie
  184. + csrw hie, a1
  185. + csrr a0, hcounteren
  186. + csrw hcounteren, a1
  187. + csrr a0, hgeie
  188. + csrw hgeie, a1
  189. + csrr a0, htval
  190. + csrw htval, a1
  191. + csrr a0, hip
  192. + csrw hip, a1
  193. + csrr a0, hvip
  194. + csrw hvip, a1
  195. + csrr a0, htinst
  196. + csrw htinst, a1
  197. + csrr a0, hgeip
  198. + csrw hgeip, a1
  199. + csrr a0, henvcfg
  200. + csrw henvcfg, a1
  201. + csrr a0, henvcfgh
  202. + csrw henvcfgh, a1
  203. + csrr a0, hgatp
  204. + csrw hgatp, a1
  205. + csrr a0, hcontext
  206. + csrw hcontext, a1
  207. + csrr a0, htimedelta
  208. + csrw htimedelta, a1
  209. + csrr a0, htimedeltah
  210. + csrw htimedeltah, a1
  211. + csrr a0, vsstatus
  212. + csrw vsstatus, a1
  213. + csrr a0, vsie
  214. + csrw vsie, a1
  215. + csrr a0, vstvec
  216. + csrw vstvec, a1
  217. + csrr a0, vsscratch
  218. + csrw vsscratch, a1
  219. + csrr a0, vsepc
  220. + csrw vsepc, a1
  221. + csrr a0, vscause
  222. + csrw vscause, a1
  223. + csrr a0, vstval
  224. + csrw vstval, a1
  225. + csrr a0, vsip
  226. + csrw vsip, a1
  227. + csrr a0, vsatp
  228. + csrw vsatp, a1
  229. diff --git a/gas/testsuite/gas/riscv/h-ext-64.d b/gas/testsuite/gas/riscv/h-ext-64.d
  230. new file mode 100644
  231. index 0000000000..efbb634c2b
  232. --- /dev/null
  233. +++ b/gas/testsuite/gas/riscv/h-ext-64.d
  234. @@ -0,0 +1,73 @@
  235. +#as: -march=rv64g -mpriv-spec=1.12
  236. +#source: h-ext-64.s
  237. +#objdump: -d
  238. +
  239. +.*:[ ]+file format .*
  240. +
  241. +
  242. +Disassembly of section .text:
  243. +
  244. +0+000 <.text>:
  245. +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
  246. +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
  247. +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\)
  248. +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\)
  249. +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\)
  250. +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\)
  251. +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\)
  252. +[ ]+[0-9a-f]+:[ ]+6816c673[ ]+hlv.wu[ ]+a2,\(a3\)
  253. +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\)
  254. +[ ]+[0-9a-f]+:[ ]+6c0746f3[ ]+hlv.d[ ]+a3,\(a4\)
  255. +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
  256. +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
  257. +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\)
  258. +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\)
  259. +[ ]+[0-9a-f]+:[ ]+6ea5c073[ ]+hsv.d[ ]+a0,\(a1\)
  260. +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus
  261. +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1
  262. +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg
  263. +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1
  264. +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg
  265. +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1
  266. +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie
  267. +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1
  268. +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren
  269. +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1
  270. +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie
  271. +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1
  272. +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval
  273. +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1
  274. +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip
  275. +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1
  276. +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip
  277. +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1
  278. +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst
  279. +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1
  280. +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip
  281. +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1
  282. +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg
  283. +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1
  284. +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp
  285. +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1
  286. +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext
  287. +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1
  288. +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta
  289. +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1
  290. +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus
  291. +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1
  292. +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie
  293. +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1
  294. +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
  295. +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1
  296. +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
  297. +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1
  298. +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
  299. +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1
  300. +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause
  301. +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1
  302. +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval
  303. +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1
  304. +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip
  305. +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
  306. +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
  307. +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
  308. diff --git a/gas/testsuite/gas/riscv/h-ext-64.s b/gas/testsuite/gas/riscv/h-ext-64.s
  309. new file mode 100644
  310. index 0000000000..72ab3bc988
  311. --- /dev/null
  312. +++ b/gas/testsuite/gas/riscv/h-ext-64.s
  313. @@ -0,0 +1,63 @@
  314. + hlv.b a0, (a1)
  315. + hlv.b a0,0(a1)
  316. + hlv.bu a0, (a1)
  317. + hlv.h a1, (a2)
  318. + hlv.hu a1, (a1)
  319. + hlvx.hu a1, (a2)
  320. + hlv.w a2, (a2)
  321. + hlv.wu a2, (a3)
  322. + hlvx.wu a2, (a3)
  323. + hlv.d a3, (a4)
  324. + hsv.b a0, (a1)
  325. + hsv.b a0,0(a1)
  326. + hsv.h a0, (a1)
  327. + hsv.w a0, (a1)
  328. + hsv.d a0, (a1)
  329. + csrr a0, hstatus
  330. + csrw hstatus, a1
  331. + csrr a0, hedeleg
  332. + csrw hedeleg, a1
  333. + csrr a0, hideleg
  334. + csrw hideleg, a1
  335. + csrr a0, hie
  336. + csrw hie, a1
  337. + csrr a0, hcounteren
  338. + csrw hcounteren, a1
  339. + csrr a0, hgeie
  340. + csrw hgeie, a1
  341. + csrr a0, htval
  342. + csrw htval, a1
  343. + csrr a0, hip
  344. + csrw hip, a1
  345. + csrr a0, hvip
  346. + csrw hvip, a1
  347. + csrr a0, htinst
  348. + csrw htinst, a1
  349. + csrr a0, hgeip
  350. + csrw hgeip, a1
  351. + csrr a0, henvcfg
  352. + csrw henvcfg, a1
  353. + csrr a0, hgatp
  354. + csrw hgatp, a1
  355. + csrr a0, hcontext
  356. + csrw hcontext, a1
  357. + csrr a0, htimedelta
  358. + csrw htimedelta, a1
  359. + csrr a0, vsstatus
  360. + csrw vsstatus, a1
  361. + csrr a0, vsie
  362. + csrw vsie, a1
  363. + csrr a0, vstvec
  364. + csrw vstvec, a1
  365. + csrr a0, vsscratch
  366. + csrw vsscratch, a1
  367. + csrr a0, vsepc
  368. + csrw vsepc, a1
  369. + csrr a0, vscause
  370. + csrw vscause, a1
  371. + csrr a0, vstval
  372. + csrw vstval, a1
  373. + csrr a0, vsip
  374. + csrw vsip, a1
  375. + csrr a0, vsatp
  376. + csrw vsatp, a1
  377. diff --git a/gas/testsuite/gas/riscv/svinval-and-h.d b/gas/testsuite/gas/riscv/svinval-and-h.d
  378. new file mode 100644
  379. index 0000000000..8103a11cf7
  380. --- /dev/null
  381. +++ b/gas/testsuite/gas/riscv/svinval-and-h.d
  382. @@ -0,0 +1,15 @@
  383. +#as: -march=rv64i
  384. +#source: svinval-and-h.s
  385. +#objdump: -d
  386. +
  387. +.*:[ ]+file format .*
  388. +
  389. +
  390. +Disassembly of section .text:
  391. +
  392. +0+000 <.text>:
  393. +[ ]+0:[ ]+22b50073[ ]+hfence.vvma[ ]+a0,a1
  394. +[ ]+4:[ ]+62000073[ ]+hfence.gvma
  395. +[ ]+8:[ ]+62050073[ ]+hfence.gvma[ ]+a0
  396. +[ ]+c:[ ]+62b00073[ ]+hfence.gvma[ ]+zero,a1
  397. +[ ]+10:[ ]+62c58073[ ]+hfence.gvma[ ]+a1,a2
  398. diff --git a/gas/testsuite/gas/riscv/svinval-and-h.s b/gas/testsuite/gas/riscv/svinval-and-h.s
  399. new file mode 100644
  400. index 0000000000..aa031fd888
  401. --- /dev/null
  402. +++ b/gas/testsuite/gas/riscv/svinval-and-h.s
  403. @@ -0,0 +1,5 @@
  404. + hfence.vvma a0, a1
  405. + hfence.gvma
  406. + hfence.gvma a0
  407. + hfence.gvma x0, a1
  408. + hfence.gvma a1, a2
  409. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  410. index 9a4f73054e..ee3d4aa51f 100644
  411. --- a/include/opcode/riscv-opc.h
  412. +++ b/include/opcode/riscv-opc.h
  413. @@ -267,6 +267,11 @@
  414. #define MASK_SFENCE_VMA 0xfe007fff
  415. #define MATCH_WFI 0x10500073
  416. #define MASK_WFI 0xffffffff
  417. +#define MASK_HFENCE_VVMA 0xfe007fff
  418. +#define MATCH_HFENCE_VVMA 0x22000073
  419. +#define MASK_HFENCE_GVMA 0xfe007fff
  420. +#define MATCH_HFENCE_GVMA 0x62000073
  421. +
  422. /* Custom CSRs instruction */
  423. #define MATCH_CFLUSH_D_L1 0xfc000073
  424. #define MASK_CFLUSH_D_L1 0xfff07fff
  425. @@ -2612,6 +2617,22 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  426. #define MATCH_VFDOTVV 0xe4001057
  427. #define MASK_VFDOTVV 0xfc00707f
  428. /* END RVV */
  429. +#define MASK_HLV 0xfff0707f
  430. +#define MATCH_HLVB 0x60004073
  431. +#define MATCH_HLVBU 0x60104073
  432. +#define MATCH_HLVH 0x64004073
  433. +#define MATCH_HLVHU 0x64104073
  434. +#define MATCH_HLVXHU 0x64304073
  435. +#define MATCH_HLVW 0x68004073
  436. +#define MATCH_HLVXWU 0x68304073
  437. +#define MATCH_HLVWU 0x68104073
  438. +#define MATCH_HLVD 0x6c004073
  439. +
  440. +#define MASK_HSV 0xfe007fff
  441. +#define MATCH_HSVB 0x62004073
  442. +#define MATCH_HSVH 0x66004073
  443. +#define MATCH_HSVW 0x6a004073
  444. +#define MATCH_HSVD 0x6e004073
  445. #define MATCH_CUSTOM0 0xb
  446. #define MASK_CUSTOM0 0x707f
  447. @@ -2874,6 +2895,33 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  448. #define CSR_MHPMEVENT29 0x33d
  449. #define CSR_MHPMEVENT30 0x33e
  450. #define CSR_MHPMEVENT31 0x33f
  451. +/* Hypervisor Extension v1.0 (Privileged spec 1.12). */
  452. +#define CSR_HSTATUS 0x600
  453. +#define CSR_HEDELEG 0x602
  454. +#define CSR_HIDELEG 0x603
  455. +#define CSR_HIE 0x604
  456. +#define CSR_HCOUNTEREN 0x606
  457. +#define CSR_HGEIE 0x607
  458. +#define CSR_HTVAL 0x643
  459. +#define CSR_HIP 0x644
  460. +#define CSR_HVIP 0x645
  461. +#define CSR_HTINST 0x64a
  462. +#define CSR_HGEIP 0xe12
  463. +#define CSR_HENVCFG 0x60a
  464. +#define CSR_HENVCFGH 0x61a
  465. +#define CSR_HGATP 0x680
  466. +#define CSR_HCONTEXT 0x6a8
  467. +#define CSR_HTIMEDELTA 0x605
  468. +#define CSR_HTIMEDELTAH 0x615
  469. +#define CSR_VSSTATUS 0x200
  470. +#define CSR_VSIE 0x204
  471. +#define CSR_VSTVEC 0x205
  472. +#define CSR_VSSCRATCH 0x240
  473. +#define CSR_VSEPC 0x241
  474. +#define CSR_VSCAUSE 0x242
  475. +#define CSR_VSTVAL 0x243
  476. +#define CSR_VSIP 0x244
  477. +#define CSR_VSATP 0x280
  478. #define CSR_MBASE 0x380
  479. #define CSR_MBOUND 0x381
  480. #define CSR_MIBASE 0x382
  481. @@ -3023,6 +3071,22 @@ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
  482. DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
  483. DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
  484. DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
  485. +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE)
  486. +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE)
  487. +DECLARE_INSN(hlv_b, MATCH_HLVB, MASK_HLV)
  488. +DECLARE_INSN(hlv_h, MATCH_HLVH, MASK_HLV)
  489. +DECLARE_INSN(hlv_w, MATCH_HLVW, MASK_HLV)
  490. +DECLARE_INSN(hlv_d, MATCH_HLVD, MASK_HLV)
  491. +DECLARE_INSN(hlv_bu, MATCH_HLVBU, MASK_HLV)
  492. +DECLARE_INSN(hlv_hu, MATCH_HLVHU, MASK_HLV)
  493. +DECLARE_INSN(hlv_wu, MATCH_HLVWU, MASK_HLV)
  494. +DECLARE_INSN(hlvx_hu, MATCH_HLVXHU, MASK_HLV)
  495. +DECLARE_INSN(hlvx_wu, MATCH_HLVXWU, MASK_HLV)
  496. +DECLARE_INSN(hsv_b, MATCH_HSVB, MASK_HSV)
  497. +DECLARE_INSN(hsv_h, MATCH_HSVH, MASK_HSV)
  498. +DECLARE_INSN(hsv_w, MATCH_HSVW, MASK_HSV)
  499. +DECLARE_INSN(hsv_d, MATCH_HSVD, MASK_HSV)
  500. +
  501. /* Custom CSRs instruction */
  502. DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
  503. DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
  504. @@ -3449,6 +3513,35 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
  505. DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  506. DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  507. DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
  508. +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */
  509. +/* TODO: Fix to CSR_CLASS_H when explicit h-ext arch string is introduced. */
  510. +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  511. +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  512. +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  513. +DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  514. +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  515. +DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  516. +DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  517. +DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  518. +DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  519. +DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  520. +DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  521. +DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  522. +DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  523. +DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  524. +DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  525. +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  526. +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  527. +DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  528. +DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  529. +DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  530. +DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  531. +DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  532. +DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  533. +DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  534. +DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  535. +DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
  536. +
  537. /* Dropped CSRs. */
  538. DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  539. DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
  540. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  541. index 52f653c288..bfb9b98856 100644
  542. --- a/include/opcode/riscv.h
  543. +++ b/include/opcode/riscv.h
  544. @@ -402,6 +402,7 @@ enum riscv_insn_class
  545. INSN_CLASS_V_AND_F,
  546. INSN_CLASS_V_OR_ZVAMO,
  547. INSN_CLASS_V_OR_ZVLSSEG,
  548. + INSN_CLASS_H,
  549. };
  550. /* This structure holds information for a particular instruction. */
  551. @@ -524,4 +525,4 @@ extern const char * const riscv_vecm_names_numeric[NVECM];
  552. extern const struct riscv_opcode riscv_opcodes[];
  553. extern const struct riscv_opcode riscv_insn_types[];
  554. -#endif /* _RISCV_H_ */
  555. \ No newline at end of file
  556. +#endif /* _RISCV_H_ */
  557. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  558. index a1d7667b13..f42a0db494 100644
  559. --- a/opcodes/riscv-opc.c
  560. +++ b/opcodes/riscv-opc.c
  561. @@ -2087,6 +2087,27 @@ const struct riscv_opcode riscv_opcodes[] =
  562. {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
  563. /* END RVV */
  564. +/* Hypervisor Ext v1.0. */
  565. +{"hfence.vvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 },
  566. +{"hfence.gvma", 0, INSN_CLASS_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 },
  567. +{"hfence.gvma", 0, INSN_CLASS_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 },
  568. +{"hfence.gvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 },
  569. +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */
  570. +{"hlv.b", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVB, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE },
  571. +{"hlv.bu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVBU, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE },
  572. +{"hlv.h", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVH, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE },
  573. +{"hlv.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE },
  574. +{"hlvx.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE },
  575. +{"hlv.w", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVW, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE },
  576. +{"hlv.wu", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE },
  577. +{"hlvx.wu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE },
  578. +{"hlv.d", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVD, MASK_HLV, match_opcode, INSN_DREF|INSN_8_BYTE },
  579. +
  580. +{"hsv.b", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVB, MASK_HSV, match_opcode, INSN_DREF|INSN_1_BYTE },
  581. +{"hsv.h", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVH, MASK_HSV, match_opcode, INSN_DREF|INSN_2_BYTE },
  582. +{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVW, MASK_HSV, match_opcode, INSN_DREF|INSN_4_BYTE },
  583. +{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSVD, MASK_HSV, match_opcode, INSN_DREF|INSN_8_BYTE },
  584. +
  585. /* Terminate the list. */
  586. {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
  587. };
  588. --
  589. 2.33.1