From 34b95485ed2e4c553071fcbb88a0011bcb041e34 Mon Sep 17 00:00:00 2001 From: "eric.tang" Date: Mon, 17 Jan 2022 13:19:43 +0800 Subject: [PATCH 13/14] RISC-V: Hypervisor ext: support Privileged Spec 1.12 - Hypervisor Memory-Management Instructions HFENCE.VVMA, HFENCE.GVMA, - Hypervisor Virtual Machine Load and Store Instructions HLV.B, HLV.BU, HSV.B, HLV.H, HLV.HU, HLVX.HU, HSB.H, HLV.W, HLV.WU, HLVX.WU, HSV.W, HLV.D, HSV.D - Hypervisor CSRs (some new, some address changed) hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, changed from https://patches-gcc.linaro.org/patch/65621/ Signed-off-by: eric.tang --- bfd/cpu-riscv.c | 1 + bfd/cpu-riscv.h | 1 + gas/config/tc-riscv.c | 4 +- gas/testsuite/gas/riscv/h-ext-32.d | 74 ++++++++++++++++++++ gas/testsuite/gas/riscv/h-ext-32.s | 64 +++++++++++++++++ gas/testsuite/gas/riscv/h-ext-64.d | 73 +++++++++++++++++++ gas/testsuite/gas/riscv/h-ext-64.s | 63 +++++++++++++++++ gas/testsuite/gas/riscv/svinval-and-h.d | 15 ++++ gas/testsuite/gas/riscv/svinval-and-h.s | 5 ++ include/opcode/riscv-opc.h | 93 +++++++++++++++++++++++++ include/opcode/riscv.h | 3 +- opcodes/riscv-opc.c | 21 ++++++ 12 files changed, 415 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.d create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.s diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c index 025e94afd3..182f389e57 100644 --- a/bfd/cpu-riscv.c +++ b/bfd/cpu-riscv.c @@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] = {"1.9.1", PRIV_SPEC_CLASS_1P9P1}, {"1.10", PRIV_SPEC_CLASS_1P10}, {"1.11", PRIV_SPEC_CLASS_1P11}, + {"1.12", PRIV_SPEC_CLASS_1P12}, }; /* Get the corresponding CSR version class by giving privilege diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h index cafaca23be..4d111ab797 100644 --- a/bfd/cpu-riscv.h +++ b/bfd/cpu-riscv.h @@ -32,6 +32,7 @@ enum riscv_spec_class PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P11, + PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT, }; diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index d473743019..fca5c8949d 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -360,6 +360,8 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class) || riscv_subset_supports ("zvamo"))); case INSN_CLASS_V_OR_ZVLSSEG: return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg"); + case INSN_CLASS_H: + return riscv_subset_supports ("i"); default: as_fatal ("internal: unreachable"); return false; @@ -4365,4 +4367,4 @@ riscv_pop_insert (void) extern void pop_insert (const pseudo_typeS *); pop_insert (riscv_pseudo_table); -} \ No newline at end of file +} diff --git a/gas/testsuite/gas/riscv/h-ext-32.d b/gas/testsuite/gas/riscv/h-ext-32.d new file mode 100644 index 0000000000..e851fac500 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-32.d @@ -0,0 +1,74 @@ +#as: -march=rv32g -mpriv-spec=1.12 +#source: h-ext-32.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\) +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\) +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1 +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1 +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1 +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1 +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1 +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1 +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1 +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1 +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1 +[ ]+[0-9a-f]+:[ ]+61a02573[ ]+csrr[ ]+a0,henvcfgh +[ ]+[0-9a-f]+:[ ]+61a59073[ ]+csrw[ ]+henvcfgh,a1 +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1 +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1 +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1 +[ ]+[0-9a-f]+:[ ]+61502573[ ]+csrr[ ]+a0,htimedeltah +[ ]+[0-9a-f]+:[ ]+61559073[ ]+csrw[ ]+htimedeltah,a1 +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1 +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1 +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1 +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1 +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1 +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1 +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1 +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 diff --git a/gas/testsuite/gas/riscv/h-ext-32.s b/gas/testsuite/gas/riscv/h-ext-32.s new file mode 100644 index 0000000000..c3ab5bb592 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-32.s @@ -0,0 +1,64 @@ + hlv.b a0, (a1) + hlv.b a0,0(a1) + hlv.bu a0, (a1) + hlv.h a1, (a2) + hlv.hu a1, (a1) + hlvx.hu a1, (a2) + hlv.w a2, (a2) + hlvx.wu a2, (a3) + hsv.b a0, (a1) + hsv.b a0,0(a1) + hsv.h a0, (a1) + hsv.w a0, (a1) + csrr a0, hstatus + csrw hstatus, a1 + csrr a0, hedeleg + csrw hedeleg, a1 + csrr a0, hideleg + csrw hideleg, a1 + csrr a0, hie + csrw hie, a1 + csrr a0, hcounteren + csrw hcounteren, a1 + csrr a0, hgeie + csrw hgeie, a1 + csrr a0, htval + csrw htval, a1 + csrr a0, hip + csrw hip, a1 + csrr a0, hvip + csrw hvip, a1 + csrr a0, htinst + csrw htinst, a1 + csrr a0, hgeip + csrw hgeip, a1 + csrr a0, henvcfg + csrw henvcfg, a1 + csrr a0, henvcfgh + csrw henvcfgh, a1 + csrr a0, hgatp + csrw hgatp, a1 + csrr a0, hcontext + csrw hcontext, a1 + csrr a0, htimedelta + csrw htimedelta, a1 + csrr a0, htimedeltah + csrw htimedeltah, a1 + csrr a0, vsstatus + csrw vsstatus, a1 + csrr a0, vsie + csrw vsie, a1 + csrr a0, vstvec + csrw vstvec, a1 + csrr a0, vsscratch + csrw vsscratch, a1 + csrr a0, vsepc + csrw vsepc, a1 + csrr a0, vscause + csrw vscause, a1 + csrr a0, vstval + csrw vstval, a1 + csrr a0, vsip + csrw vsip, a1 + csrr a0, vsatp + csrw vsatp, a1 diff --git a/gas/testsuite/gas/riscv/h-ext-64.d b/gas/testsuite/gas/riscv/h-ext-64.d new file mode 100644 index 0000000000..efbb634c2b --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-64.d @@ -0,0 +1,73 @@ +#as: -march=rv64g -mpriv-spec=1.12 +#source: h-ext-64.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\) +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\) +[ ]+[0-9a-f]+:[ ]+6816c673[ ]+hlv.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+6c0746f3[ ]+hlv.d[ ]+a3,\(a4\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6ea5c073[ ]+hsv.d[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1 +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1 +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1 +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1 +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1 +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1 +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1 +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1 +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1 +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1 +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1 +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1 +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1 +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1 +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1 +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1 +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1 +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1 +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1 +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 diff --git a/gas/testsuite/gas/riscv/h-ext-64.s b/gas/testsuite/gas/riscv/h-ext-64.s new file mode 100644 index 0000000000..72ab3bc988 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-64.s @@ -0,0 +1,63 @@ + hlv.b a0, (a1) + hlv.b a0,0(a1) + hlv.bu a0, (a1) + hlv.h a1, (a2) + hlv.hu a1, (a1) + hlvx.hu a1, (a2) + hlv.w a2, (a2) + hlv.wu a2, (a3) + hlvx.wu a2, (a3) + hlv.d a3, (a4) + hsv.b a0, (a1) + hsv.b a0,0(a1) + hsv.h a0, (a1) + hsv.w a0, (a1) + hsv.d a0, (a1) + csrr a0, hstatus + csrw hstatus, a1 + csrr a0, hedeleg + csrw hedeleg, a1 + csrr a0, hideleg + csrw hideleg, a1 + csrr a0, hie + csrw hie, a1 + csrr a0, hcounteren + csrw hcounteren, a1 + csrr a0, hgeie + csrw hgeie, a1 + csrr a0, htval + csrw htval, a1 + csrr a0, hip + csrw hip, a1 + csrr a0, hvip + csrw hvip, a1 + csrr a0, htinst + csrw htinst, a1 + csrr a0, hgeip + csrw hgeip, a1 + csrr a0, henvcfg + csrw henvcfg, a1 + csrr a0, hgatp + csrw hgatp, a1 + csrr a0, hcontext + csrw hcontext, a1 + csrr a0, htimedelta + csrw htimedelta, a1 + csrr a0, vsstatus + csrw vsstatus, a1 + csrr a0, vsie + csrw vsie, a1 + csrr a0, vstvec + csrw vstvec, a1 + csrr a0, vsscratch + csrw vsscratch, a1 + csrr a0, vsepc + csrw vsepc, a1 + csrr a0, vscause + csrw vscause, a1 + csrr a0, vstval + csrw vstval, a1 + csrr a0, vsip + csrw vsip, a1 + csrr a0, vsatp + csrw vsatp, a1 diff --git a/gas/testsuite/gas/riscv/svinval-and-h.d b/gas/testsuite/gas/riscv/svinval-and-h.d new file mode 100644 index 0000000000..8103a11cf7 --- /dev/null +++ b/gas/testsuite/gas/riscv/svinval-and-h.d @@ -0,0 +1,15 @@ +#as: -march=rv64i +#source: svinval-and-h.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+22b50073[ ]+hfence.vvma[ ]+a0,a1 +[ ]+4:[ ]+62000073[ ]+hfence.gvma +[ ]+8:[ ]+62050073[ ]+hfence.gvma[ ]+a0 +[ ]+c:[ ]+62b00073[ ]+hfence.gvma[ ]+zero,a1 +[ ]+10:[ ]+62c58073[ ]+hfence.gvma[ ]+a1,a2 diff --git a/gas/testsuite/gas/riscv/svinval-and-h.s b/gas/testsuite/gas/riscv/svinval-and-h.s new file mode 100644 index 0000000000..aa031fd888 --- /dev/null +++ b/gas/testsuite/gas/riscv/svinval-and-h.s @@ -0,0 +1,5 @@ + hfence.vvma a0, a1 + hfence.gvma + hfence.gvma a0 + hfence.gvma x0, a1 + hfence.gvma a1, a2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9a4f73054e..ee3d4aa51f 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -267,6 +267,11 @@ #define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff +#define MASK_HFENCE_VVMA 0xfe007fff +#define MATCH_HFENCE_VVMA 0x22000073 +#define MASK_HFENCE_GVMA 0xfe007fff +#define MATCH_HFENCE_GVMA 0x62000073 + /* Custom CSRs instruction */ #define MATCH_CFLUSH_D_L1 0xfc000073 #define MASK_CFLUSH_D_L1 0xfff07fff @@ -2612,6 +2617,22 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f /* END RVV */ +#define MASK_HLV 0xfff0707f +#define MATCH_HLVB 0x60004073 +#define MATCH_HLVBU 0x60104073 +#define MATCH_HLVH 0x64004073 +#define MATCH_HLVHU 0x64104073 +#define MATCH_HLVXHU 0x64304073 +#define MATCH_HLVW 0x68004073 +#define MATCH_HLVXWU 0x68304073 +#define MATCH_HLVWU 0x68104073 +#define MATCH_HLVD 0x6c004073 + +#define MASK_HSV 0xfe007fff +#define MATCH_HSVB 0x62004073 +#define MATCH_HSVH 0x66004073 +#define MATCH_HSVW 0x6a004073 +#define MATCH_HSVD 0x6e004073 #define MATCH_CUSTOM0 0xb #define MASK_CUSTOM0 0x707f @@ -2874,6 +2895,33 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f +/* Hypervisor Extension v1.0 (Privileged spec 1.12). */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGEIP 0xe12 +#define CSR_HENVCFG 0x60a +#define CSR_HENVCFGH 0x61a +#define CSR_HGATP 0x680 +#define CSR_HCONTEXT 0x6a8 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HTIMEDELTAH 0x615 +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 #define CSR_MIBASE 0x382 @@ -3023,6 +3071,22 @@ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE) +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE) +DECLARE_INSN(hlv_b, MATCH_HLVB, MASK_HLV) +DECLARE_INSN(hlv_h, MATCH_HLVH, MASK_HLV) +DECLARE_INSN(hlv_w, MATCH_HLVW, MASK_HLV) +DECLARE_INSN(hlv_d, MATCH_HLVD, MASK_HLV) +DECLARE_INSN(hlv_bu, MATCH_HLVBU, MASK_HLV) +DECLARE_INSN(hlv_hu, MATCH_HLVHU, MASK_HLV) +DECLARE_INSN(hlv_wu, MATCH_HLVWU, MASK_HLV) +DECLARE_INSN(hlvx_hu, MATCH_HLVXHU, MASK_HLV) +DECLARE_INSN(hlvx_wu, MATCH_HLVXWU, MASK_HLV) +DECLARE_INSN(hsv_b, MATCH_HSVB, MASK_HSV) +DECLARE_INSN(hsv_h, MATCH_HSVH, MASK_HSV) +DECLARE_INSN(hsv_w, MATCH_HSVW, MASK_HSV) +DECLARE_INSN(hsv_d, MATCH_HSVD, MASK_HSV) + /* Custom CSRs instruction */ DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1) DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1) @@ -3449,6 +3513,35 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */ +/* TODO: Fix to CSR_CLASS_H when explicit h-ext arch string is introduced. */ +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) + /* Dropped CSRs. */ DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 52f653c288..bfb9b98856 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -402,6 +402,7 @@ enum riscv_insn_class INSN_CLASS_V_AND_F, INSN_CLASS_V_OR_ZVAMO, INSN_CLASS_V_OR_ZVLSSEG, + INSN_CLASS_H, }; /* This structure holds information for a particular instruction. */ @@ -524,4 +525,4 @@ extern const char * const riscv_vecm_names_numeric[NVECM]; extern const struct riscv_opcode riscv_opcodes[]; extern const struct riscv_opcode riscv_insn_types[]; -#endif /* _RISCV_H_ */ \ No newline at end of file +#endif /* _RISCV_H_ */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index a1d7667b13..f42a0db494 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2087,6 +2087,27 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0}, /* END RVV */ +/* Hypervisor Ext v1.0. */ +{"hfence.vvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 }, +{"hfence.gvma", 0, INSN_CLASS_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 }, +{"hfence.gvma", 0, INSN_CLASS_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 }, +{"hfence.gvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 }, +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */ +{"hlv.b", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVB, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"hlv.bu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVBU, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"hlv.h", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVH, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hlv.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hlvx.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hlv.w", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVW, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hlv.wu", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hlvx.wu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hlv.d", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVD, MASK_HLV, match_opcode, INSN_DREF|INSN_8_BYTE }, + +{"hsv.b", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVB, MASK_HSV, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"hsv.h", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVH, MASK_HSV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVW, MASK_HSV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSVD, MASK_HSV, match_opcode, INSN_DREF|INSN_8_BYTE }, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} }; -- 2.33.1