0008-target-riscv-rvb-add-bcompress-bdecompress-instructi.patch 5.7 KB

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  1. From ffb3819a1bb82a3143449726e8d636f509772750 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Fri, 9 Jul 2021 15:17:18 +0800
  4. Subject: [PATCH 08/11] target/riscv: rvb: add bcompress/bdecompress
  5. instructions
  6. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  7. ---
  8. target/riscv/bitmanip_helper.c | 44 +++++++++++++++++++++++++
  9. target/riscv/helper.h | 2 ++
  10. target/riscv/insn32.decode | 4 +++
  11. target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++
  12. target/riscv/translate.c | 16 +++++++++
  13. 5 files changed, 90 insertions(+)
  14. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  15. index d9c5c56468..5e46b69159 100644
  16. --- a/target/riscv/bitmanip_helper.c
  17. +++ b/target/riscv/bitmanip_helper.c
  18. @@ -396,3 +396,47 @@ target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2)
  19. {
  20. return do_bfpw(rs1, rs2);
  21. }
  22. +
  23. +static target_ulong do_bcompress(target_ulong rs1,
  24. + target_ulong rs2,
  25. + int bits)
  26. +{
  27. + target_ulong r = 0;
  28. + int i, j = 0;
  29. + for (i = 0; i < bits; i++) {
  30. + if ((rs2 >> i) & 1) {
  31. + if ((rs1 >> i) & 1)
  32. + r |= (target_ulong)1 << j;
  33. + j++;
  34. + }
  35. + }
  36. +
  37. + return r;
  38. +}
  39. +
  40. +static target_ulong do_bdecompress(target_ulong rs1,
  41. + target_ulong rs2,
  42. + int bits)
  43. +{
  44. + target_ulong r = 0;
  45. + int i, j = 0;
  46. + for (i = 0; i < bits; i++) {
  47. + if ((rs2 >> i) & 1) {
  48. + if ((rs1 >> j) & 1)
  49. + r |= (target_ulong)1 << i;
  50. + j++;
  51. + }
  52. + }
  53. +
  54. + return r;
  55. +}
  56. +
  57. +target_ulong HELPER(bcompress)(target_ulong rs1, target_ulong rs2)
  58. +{
  59. + return do_bcompress(rs1, rs2, TARGET_LONG_BITS);
  60. +}
  61. +
  62. +target_ulong HELPER(bdecompress)(target_ulong rs1, target_ulong rs2)
  63. +{
  64. + return do_bdecompress(rs1, rs2, TARGET_LONG_BITS);
  65. +}
  66. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  67. index 2ae199f399..577f9f6811 100644
  68. --- a/target/riscv/helper.h
  69. +++ b/target/riscv/helper.h
  70. @@ -76,6 +76,8 @@ DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  71. DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  72. DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  73. DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  74. +DEF_HELPER_FLAGS_2(bcompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  75. +DEF_HELPER_FLAGS_2(bdecompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  76. DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  77. DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  78. DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  79. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  80. index 8187c42323..8aaca89ce9 100644
  81. --- a/target/riscv/insn32.decode
  82. +++ b/target/riscv/insn32.decode
  83. @@ -709,6 +709,8 @@ cmix .....11 .......... 001 ..... 0110011 @r3
  84. cmov .....11 .......... 101 ..... 0110011 @r3
  85. fsl .....10 .......... 001 ..... 0110011 @r3
  86. fsr .....10 .......... 101 ..... 0110011 @r3
  87. +bcompress 0000100 .......... 110 ..... 0110011 @r
  88. +bdecompress 0100100 .......... 110 ..... 0110011 @r
  89. fsri .....1 ........... 101 ..... 0010011 @r3_imm
  90. bseti 001010 ........... 001 ..... 0010011 @sh6
  91. @@ -750,6 +752,8 @@ xperm_w 0010100 .......... 000 ..... 0110011 @r
  92. bfpw 0100100 .......... 111 ..... 0111011 @r
  93. fslw .....10 .......... 001 ..... 0111011 @r3
  94. fsrw .....10 .......... 101 ..... 0111011 @r3
  95. +bcompressw 0000100 .......... 110 ..... 0111011 @r
  96. +bdecompressw 0100100 .......... 110 ..... 0111011 @r
  97. fsriw .....10 .......... 101 ..... 0011011 @r3w_imm
  98. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  99. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  100. index 28a5b34bd4..d4374d174e 100644
  101. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  102. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  103. @@ -295,6 +295,18 @@ static bool trans_bfp(DisasContext *ctx, arg_bfp *a)
  104. return gen_arith(ctx, a, gen_helper_bfp);
  105. }
  106. +static bool trans_bcompress(DisasContext *ctx, arg_bcompress *a)
  107. +{
  108. + REQUIRE_EXT(ctx, RVB);
  109. + return gen_arith(ctx, a, gen_helper_bcompress);
  110. +}
  111. +
  112. +static bool trans_bdecompress(DisasContext *ctx, arg_bdecompress *a)
  113. +{
  114. + REQUIRE_EXT(ctx, RVB);
  115. + return gen_arith(ctx, a, gen_helper_bdecompress);
  116. +}
  117. +
  118. static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
  119. {
  120. REQUIRE_EXT(ctx, RVB);
  121. @@ -384,6 +396,18 @@ static bool trans_fsriw(DisasContext *ctx, arg_fsri *a)
  122. return gen_quati(ctx, a, gen_fsrw);
  123. }
  124. +static bool trans_bcompressw(DisasContext *ctx, arg_bcompressw *a)
  125. +{
  126. + REQUIRE_EXT(ctx, RVB);
  127. + return gen_arith(ctx, a, gen_bcompressw);
  128. +}
  129. +
  130. +static bool trans_bdecompressw(DisasContext *ctx, arg_bdecompressw *a)
  131. +{
  132. + REQUIRE_EXT(ctx, RVB);
  133. + return gen_arith(ctx, a, gen_bdecompressw);
  134. +}
  135. +
  136. static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  137. {
  138. REQUIRE_64BIT(ctx);
  139. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  140. index 24bcf8c580..79d93feec3 100644
  141. --- a/target/riscv/translate.c
  142. +++ b/target/riscv/translate.c
  143. @@ -792,6 +792,22 @@ GEN_RV64ONLY_INSN_2(shflw)
  144. GEN_RV64ONLY_INSN_2(unshflw)
  145. GEN_RV64ONLY_INSN_2(bfpw)
  146. +static void gen_bcompressw(TCGv ret, TCGv arg1, TCGv arg2)
  147. +{
  148. + tcg_gen_ext32u_tl(arg1, arg1);
  149. + tcg_gen_ext32u_tl(arg2, arg2);
  150. + gen_helper_bcompress(ret, arg1, arg2);
  151. + tcg_gen_ext32s_tl(ret, ret);
  152. +}
  153. +
  154. +static void gen_bdecompressw(TCGv ret, TCGv arg1, TCGv arg2)
  155. +{
  156. + tcg_gen_ext32u_tl(arg1, arg1);
  157. + tcg_gen_ext32u_tl(arg2, arg2);
  158. + gen_helper_bdecompress(ret, arg1, arg2);
  159. + tcg_gen_ext32s_tl(ret, ret);
  160. +}
  161. +
  162. static bool gen_arith(DisasContext *ctx, arg_r *a,
  163. void(*func)(TCGv, TCGv, TCGv))
  164. {
  165. --
  166. 2.33.0