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- From ffb3819a1bb82a3143449726e8d636f509772750 Mon Sep 17 00:00:00 2001
- From: "eric.tang" <eric.tang@starfivetech.com>
- Date: Fri, 9 Jul 2021 15:17:18 +0800
- Subject: [PATCH 08/11] target/riscv: rvb: add bcompress/bdecompress
- instructions
- Signed-off-by: eric.tang <eric.tang@starfivetech.com>
- ---
- target/riscv/bitmanip_helper.c | 44 +++++++++++++++++++++++++
- target/riscv/helper.h | 2 ++
- target/riscv/insn32.decode | 4 +++
- target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++
- target/riscv/translate.c | 16 +++++++++
- 5 files changed, 90 insertions(+)
- diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
- index d9c5c56468..5e46b69159 100644
- --- a/target/riscv/bitmanip_helper.c
- +++ b/target/riscv/bitmanip_helper.c
- @@ -396,3 +396,47 @@ target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2)
- {
- return do_bfpw(rs1, rs2);
- }
- +
- +static target_ulong do_bcompress(target_ulong rs1,
- + target_ulong rs2,
- + int bits)
- +{
- + target_ulong r = 0;
- + int i, j = 0;
- + for (i = 0; i < bits; i++) {
- + if ((rs2 >> i) & 1) {
- + if ((rs1 >> i) & 1)
- + r |= (target_ulong)1 << j;
- + j++;
- + }
- + }
- +
- + return r;
- +}
- +
- +static target_ulong do_bdecompress(target_ulong rs1,
- + target_ulong rs2,
- + int bits)
- +{
- + target_ulong r = 0;
- + int i, j = 0;
- + for (i = 0; i < bits; i++) {
- + if ((rs2 >> i) & 1) {
- + if ((rs1 >> j) & 1)
- + r |= (target_ulong)1 << i;
- + j++;
- + }
- + }
- +
- + return r;
- +}
- +
- +target_ulong HELPER(bcompress)(target_ulong rs1, target_ulong rs2)
- +{
- + return do_bcompress(rs1, rs2, TARGET_LONG_BITS);
- +}
- +
- +target_ulong HELPER(bdecompress)(target_ulong rs1, target_ulong rs2)
- +{
- + return do_bdecompress(rs1, rs2, TARGET_LONG_BITS);
- +}
- diff --git a/target/riscv/helper.h b/target/riscv/helper.h
- index 2ae199f399..577f9f6811 100644
- --- a/target/riscv/helper.h
- +++ b/target/riscv/helper.h
- @@ -76,6 +76,8 @@ DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- +DEF_HELPER_FLAGS_2(bcompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- +DEF_HELPER_FLAGS_2(bdecompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
- DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
- DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index 8187c42323..8aaca89ce9 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -709,6 +709,8 @@ cmix .....11 .......... 001 ..... 0110011 @r3
- cmov .....11 .......... 101 ..... 0110011 @r3
- fsl .....10 .......... 001 ..... 0110011 @r3
- fsr .....10 .......... 101 ..... 0110011 @r3
- +bcompress 0000100 .......... 110 ..... 0110011 @r
- +bdecompress 0100100 .......... 110 ..... 0110011 @r
-
- fsri .....1 ........... 101 ..... 0010011 @r3_imm
- bseti 001010 ........... 001 ..... 0010011 @sh6
- @@ -750,6 +752,8 @@ xperm_w 0010100 .......... 000 ..... 0110011 @r
- bfpw 0100100 .......... 111 ..... 0111011 @r
- fslw .....10 .......... 001 ..... 0111011 @r3
- fsrw .....10 .......... 101 ..... 0111011 @r3
- +bcompressw 0000100 .......... 110 ..... 0111011 @r
- +bdecompressw 0100100 .......... 110 ..... 0111011 @r
-
- fsriw .....10 .......... 101 ..... 0011011 @r3w_imm
- bsetiw 0010100 .......... 001 ..... 0011011 @sh5
- diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
- index 28a5b34bd4..d4374d174e 100644
- --- a/target/riscv/insn_trans/trans_rvb.c.inc
- +++ b/target/riscv/insn_trans/trans_rvb.c.inc
- @@ -295,6 +295,18 @@ static bool trans_bfp(DisasContext *ctx, arg_bfp *a)
- return gen_arith(ctx, a, gen_helper_bfp);
- }
-
- +static bool trans_bcompress(DisasContext *ctx, arg_bcompress *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_arith(ctx, a, gen_helper_bcompress);
- +}
- +
- +static bool trans_bdecompress(DisasContext *ctx, arg_bdecompress *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_arith(ctx, a, gen_helper_bdecompress);
- +}
- +
- static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
- {
- REQUIRE_EXT(ctx, RVB);
- @@ -384,6 +396,18 @@ static bool trans_fsriw(DisasContext *ctx, arg_fsri *a)
- return gen_quati(ctx, a, gen_fsrw);
- }
-
- +static bool trans_bcompressw(DisasContext *ctx, arg_bcompressw *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_arith(ctx, a, gen_bcompressw);
- +}
- +
- +static bool trans_bdecompressw(DisasContext *ctx, arg_bdecompressw *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_arith(ctx, a, gen_bdecompressw);
- +}
- +
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
- REQUIRE_64BIT(ctx);
- diff --git a/target/riscv/translate.c b/target/riscv/translate.c
- index 24bcf8c580..79d93feec3 100644
- --- a/target/riscv/translate.c
- +++ b/target/riscv/translate.c
- @@ -792,6 +792,22 @@ GEN_RV64ONLY_INSN_2(shflw)
- GEN_RV64ONLY_INSN_2(unshflw)
- GEN_RV64ONLY_INSN_2(bfpw)
-
- +static void gen_bcompressw(TCGv ret, TCGv arg1, TCGv arg2)
- +{
- + tcg_gen_ext32u_tl(arg1, arg1);
- + tcg_gen_ext32u_tl(arg2, arg2);
- + gen_helper_bcompress(ret, arg1, arg2);
- + tcg_gen_ext32s_tl(ret, ret);
- +}
- +
- +static void gen_bdecompressw(TCGv ret, TCGv arg1, TCGv arg2)
- +{
- + tcg_gen_ext32u_tl(arg1, arg1);
- + tcg_gen_ext32u_tl(arg2, arg2);
- + gen_helper_bdecompress(ret, arg1, arg2);
- + tcg_gen_ext32s_tl(ret, ret);
- +}
- +
- static bool gen_arith(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
- {
- --
- 2.33.0
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