0074-target-riscv-rvv-1.0-trigger-illegal-instruction-exc.patch 4.6 KB

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  1. From a2fcbad989e7e80e24876cf81fa5fa7b81df71ec Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Tue, 29 Sep 2020 10:45:54 +0800
  4. Subject: [PATCH 074/107] target/riscv: rvv-1.0: trigger illegal instruction
  5. exception if frm is not valid
  6. If the frm field contains an invalid rounding mode (101-111),
  7. attempting to execute any vector floating-point instruction, even
  8. those that do not depend on the rounding mode, will raise an illegal
  9. instruction exception.
  10. Call gen_set_rm() with DYN rounding mode to check and trigger illegal
  11. instruction exception if frm field contains invalid value at run-time
  12. for vector floating-point instructions.
  13. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  14. ---
  15. target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++++++++++
  16. 1 file changed, 22 insertions(+)
  17. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  18. index b3d2a9113e..f032a596b5 100644
  19. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  20. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  21. @@ -2605,6 +2605,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
  22. int rm)
  23. {
  24. if (checkfn(s, a)) {
  25. + if (rm != RISCV_FRM_DYN) {
  26. + gen_set_rm(s, RISCV_FRM_DYN);
  27. + }
  28. +
  29. uint32_t data = 0;
  30. TCGLabel *over = gen_new_label();
  31. gen_set_rm(s, rm);
  32. @@ -2690,6 +2694,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
  33. require_rvf(s) &&
  34. vext_check_isa_ill(s) &&
  35. require_align(a->rd, s->lmul)) {
  36. + gen_set_rm(s, RISCV_FRM_DYN);
  37. +
  38. TCGv_i64 t1;
  39. if (s->vl_eq_vlmax) {
  40. @@ -2772,6 +2778,10 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
  41. static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  42. { \
  43. if (opfv_widen_check(s, a)) { \
  44. + if (FRM != RISCV_FRM_DYN) { \
  45. + gen_set_rm(s, RISCV_FRM_DYN); \
  46. + } \
  47. + \
  48. uint32_t data = 0; \
  49. static gen_helper_gvec_3_ptr * const fns[2] = { \
  50. gen_helper_##HELPER##_h, \
  51. @@ -2857,6 +2867,10 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
  52. static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  53. { \
  54. if (opfv_narrow_check(s, a)) { \
  55. + if (FRM != RISCV_FRM_DYN) { \
  56. + gen_set_rm(s, RISCV_FRM_DYN); \
  57. + } \
  58. + \
  59. uint32_t data = 0; \
  60. static gen_helper_gvec_3_ptr * const fns[2] = { \
  61. gen_helper_##HELPER##_h, \
  62. @@ -2897,6 +2911,10 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
  63. static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  64. { \
  65. if (opxfv_narrow_check(s, a)) { \
  66. + if (FRM != RISCV_FRM_DYN) { \
  67. + gen_set_rm(s, RISCV_FRM_DYN); \
  68. + } \
  69. + \
  70. uint32_t data = 0; \
  71. static gen_helper_gvec_3_ptr * const fns[3] = { \
  72. gen_helper_##HELPER##_b, \
  73. @@ -3372,6 +3390,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
  74. if (require_rvv(s) &&
  75. require_rvf(s) &&
  76. vext_check_isa_ill(s)) {
  77. + gen_set_rm(s, RISCV_FRM_DYN);
  78. +
  79. unsigned int ofs = (8 << s->sew);
  80. unsigned int len = 64 - ofs;
  81. TCGv_i64 t_nan;
  82. @@ -3397,6 +3417,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
  83. if (require_rvv(s) &&
  84. require_rvf(s) &&
  85. vext_check_isa_ill(s)) {
  86. + gen_set_rm(s, RISCV_FRM_DYN);
  87. +
  88. /* The instructions ignore LMUL and vector register group. */
  89. TCGv_i64 t1;
  90. TCGLabel *over = gen_new_label();
  91. --
  92. 2.33.1