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- From a2fcbad989e7e80e24876cf81fa5fa7b81df71ec Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Tue, 29 Sep 2020 10:45:54 +0800
- Subject: [PATCH 074/107] target/riscv: rvv-1.0: trigger illegal instruction
- exception if frm is not valid
- If the frm field contains an invalid rounding mode (101-111),
- attempting to execute any vector floating-point instruction, even
- those that do not depend on the rounding mode, will raise an illegal
- instruction exception.
- Call gen_set_rm() with DYN rounding mode to check and trigger illegal
- instruction exception if frm field contains invalid value at run-time
- for vector floating-point instructions.
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- ---
- target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index b3d2a9113e..f032a596b5 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -2605,6 +2605,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
- int rm)
- {
- if (checkfn(s, a)) {
- + if (rm != RISCV_FRM_DYN) {
- + gen_set_rm(s, RISCV_FRM_DYN);
- + }
- +
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- gen_set_rm(s, rm);
- @@ -2690,6 +2694,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
- require_rvf(s) &&
- vext_check_isa_ill(s) &&
- require_align(a->rd, s->lmul)) {
- + gen_set_rm(s, RISCV_FRM_DYN);
- +
- TCGv_i64 t1;
-
- if (s->vl_eq_vlmax) {
- @@ -2772,6 +2778,10 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
- static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- { \
- if (opfv_widen_check(s, a)) { \
- + if (FRM != RISCV_FRM_DYN) { \
- + gen_set_rm(s, RISCV_FRM_DYN); \
- + } \
- + \
- uint32_t data = 0; \
- static gen_helper_gvec_3_ptr * const fns[2] = { \
- gen_helper_##HELPER##_h, \
- @@ -2857,6 +2867,10 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
- static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- { \
- if (opfv_narrow_check(s, a)) { \
- + if (FRM != RISCV_FRM_DYN) { \
- + gen_set_rm(s, RISCV_FRM_DYN); \
- + } \
- + \
- uint32_t data = 0; \
- static gen_helper_gvec_3_ptr * const fns[2] = { \
- gen_helper_##HELPER##_h, \
- @@ -2897,6 +2911,10 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
- static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- { \
- if (opxfv_narrow_check(s, a)) { \
- + if (FRM != RISCV_FRM_DYN) { \
- + gen_set_rm(s, RISCV_FRM_DYN); \
- + } \
- + \
- uint32_t data = 0; \
- static gen_helper_gvec_3_ptr * const fns[3] = { \
- gen_helper_##HELPER##_b, \
- @@ -3372,6 +3390,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
- if (require_rvv(s) &&
- require_rvf(s) &&
- vext_check_isa_ill(s)) {
- + gen_set_rm(s, RISCV_FRM_DYN);
- +
- unsigned int ofs = (8 << s->sew);
- unsigned int len = 64 - ofs;
- TCGv_i64 t_nan;
- @@ -3397,6 +3417,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
- if (require_rvv(s) &&
- require_rvf(s) &&
- vext_check_isa_ill(s)) {
- + gen_set_rm(s, RISCV_FRM_DYN);
- +
- /* The instructions ignore LMUL and vector register group. */
- TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
- --
- 2.33.1
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