0072-target-riscv-rvv-1.0-relax-RV_VLEN_MAX-to-1024-bits.patch 2.2 KB

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  1. From c20e6b080e9f932469ed72862e4a45cd314975e2 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 28 Sep 2020 15:57:56 +0800
  4. Subject: [PATCH 072/107] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
  5. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  6. --
  7. ---
  8. target/riscv/cpu.h | 2 +-
  9. target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
  10. target/riscv/vector_helper.c | 2 +-
  11. 3 files changed, 4 insertions(+), 4 deletions(-)
  12. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  13. index f773bae96b..d613520211 100644
  14. --- a/target/riscv/cpu.h
  15. +++ b/target/riscv/cpu.h
  16. @@ -103,7 +103,7 @@ typedef struct CPURISCVState CPURISCVState;
  17. #include "pmp.h"
  18. -#define RV_VLEN_MAX 256
  19. +#define RV_VLEN_MAX 1024
  20. FIELD(VTYPE, VLMUL, 0, 3)
  21. FIELD(VTYPE, VSEW, 3, 3)
  22. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  23. index ea79cfe7b8..d205a05e83 100644
  24. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  25. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  26. @@ -613,8 +613,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
  27. base = tcg_temp_new();
  28. /*
  29. - * As simd_desc supports at most 256 bytes, and in this implementation,
  30. - * the max vector group length is 2048 bytes. So split it into two parts.
  31. + * As simd_desc supports at most 2048 bytes, and in this implementation,
  32. + * the max vector group length is 4096 bytes. So split it into two parts.
  33. *
  34. * The first part is vlen in bytes, encoded in maxsz of simd_desc.
  35. * The second part is lmul, encoded in data of simd_desc.
  36. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  37. index 91dccdb04d..6f4f30c5f9 100644
  38. --- a/target/riscv/vector_helper.c
  39. +++ b/target/riscv/vector_helper.c
  40. @@ -129,7 +129,7 @@ static uint32_t vext_wd(uint32_t desc)
  41. static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
  42. {
  43. /*
  44. - * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
  45. + * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
  46. * so vlen in bytes (vlenb) is encoded as maxsz.
  47. */
  48. uint32_t vlenb = simd_maxsz(desc);
  49. --
  50. 2.33.1