From c20e6b080e9f932469ed72862e4a45cd314975e2 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Mon, 28 Sep 2020 15:57:56 +0800 Subject: [PATCH 072/107] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Signed-off-by: Frank Chang -- --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f773bae96b..d613520211 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -103,7 +103,7 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" -#define RV_VLEN_MAX 256 +#define RV_VLEN_MAX 1024 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ea79cfe7b8..d205a05e83 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -613,8 +613,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, base = tcg_temp_new(); /* - * As simd_desc supports at most 256 bytes, and in this implementation, - * the max vector group length is 2048 bytes. So split it into two parts. + * As simd_desc supports at most 2048 bytes, and in this implementation, + * the max vector group length is 4096 bytes. So split it into two parts. * * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 91dccdb04d..6f4f30c5f9 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -129,7 +129,7 @@ static uint32_t vext_wd(uint32_t desc) static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz) { /* - * As simd_desc support at most 256 bytes, the max vlen is 256 bits. + * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits. * so vlen in bytes (vlenb) is encoded as maxsz. */ uint32_t vlenb = simd_maxsz(desc); -- 2.33.1