0025-RISC-V-costs-support-shift-and-add-in-strength-reduc.patch 1.9 KB

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  1. From a545eb2c28726d0a574a7c6953a809362f6237e6 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Tue, 23 Nov 2021 11:41:12 +0800
  4. Subject: [PATCH 25/26] RISC-V: costs: support shift-and-add in
  5. strength-reduction
  6. ---
  7. gcc/config/riscv/riscv.c | 23 +++++++++++++++++++++++
  8. 1 file changed, 23 insertions(+)
  9. diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
  10. index 8e22e36eaaf..f832fb44d7e 100644
  11. --- a/gcc/config/riscv/riscv.c
  12. +++ b/gcc/config/riscv/riscv.c
  13. @@ -393,6 +393,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
  14. /* Simply BSETI. */
  15. codes[0].code = UNKNOWN;
  16. codes[0].value = value;
  17. +
  18. + /* RISC-V sign-extends all 32bit values that life in a 32bit
  19. + register. To avoid paradoxes, we thus need to use the
  20. + sign-extended (negative) representation for the value, if we
  21. + want to build 0x80000000 in SImode. This will then expand
  22. + to an ADDI/LI instruction. */
  23. + if (mode == SImode && value == 0x80000000)
  24. + codes[0].value = -2147483648;
  25. +
  26. return 1;
  27. }
  28. @@ -1998,6 +2007,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  29. *total = COSTS_N_INSNS (1);
  30. return true;
  31. }
  32. + /* Before strength-reduction, the shNadd can be expressed as the addition
  33. + of a multiplication with a power-of-two. If this case is not handled,
  34. + the strength-reduction in expmed.c will calculate an inflated cost. */
  35. + if (TARGET_ZBA
  36. + && ((!TARGET_64BIT && (mode == SImode)) ||
  37. + (TARGET_64BIT && (mode == DImode)))
  38. + && (GET_CODE (XEXP (x, 0)) == MULT)
  39. + && REG_P (XEXP (XEXP (x, 0), 0))
  40. + && CONST_INT_P (XEXP (XEXP (x, 0), 1))
  41. + && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3))
  42. + {
  43. + *total = COSTS_N_INSNS (1);
  44. + return true;
  45. + }
  46. /* shNadd.uw pattern for zba.
  47. [(set (match_operand:DI 0 "register_operand" "=r")
  48. (plus:DI
  49. --
  50. 2.33.1