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- From a545eb2c28726d0a574a7c6953a809362f6237e6 Mon Sep 17 00:00:00 2001
- From: "yilun.xie" <yilun.xie@starfivetech.com>
- Date: Tue, 23 Nov 2021 11:41:12 +0800
- Subject: [PATCH 25/26] RISC-V: costs: support shift-and-add in
- strength-reduction
- ---
- gcc/config/riscv/riscv.c | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
- diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
- index 8e22e36eaaf..f832fb44d7e 100644
- --- a/gcc/config/riscv/riscv.c
- +++ b/gcc/config/riscv/riscv.c
- @@ -393,6 +393,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
- /* Simply BSETI. */
- codes[0].code = UNKNOWN;
- codes[0].value = value;
- +
- + /* RISC-V sign-extends all 32bit values that life in a 32bit
- + register. To avoid paradoxes, we thus need to use the
- + sign-extended (negative) representation for the value, if we
- + want to build 0x80000000 in SImode. This will then expand
- + to an ADDI/LI instruction. */
- + if (mode == SImode && value == 0x80000000)
- + codes[0].value = -2147483648;
- +
- return 1;
- }
-
- @@ -1998,6 +2007,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- *total = COSTS_N_INSNS (1);
- return true;
- }
- + /* Before strength-reduction, the shNadd can be expressed as the addition
- + of a multiplication with a power-of-two. If this case is not handled,
- + the strength-reduction in expmed.c will calculate an inflated cost. */
- + if (TARGET_ZBA
- + && ((!TARGET_64BIT && (mode == SImode)) ||
- + (TARGET_64BIT && (mode == DImode)))
- + && (GET_CODE (XEXP (x, 0)) == MULT)
- + && REG_P (XEXP (XEXP (x, 0), 0))
- + && CONST_INT_P (XEXP (XEXP (x, 0), 1))
- + && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3))
- + {
- + *total = COSTS_N_INSNS (1);
- + return true;
- + }
- /* shNadd.uw pattern for zba.
- [(set (match_operand:DI 0 "register_operand" "=r")
- (plus:DI
- --
- 2.33.1
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