0016-merge-sifve-change-for-bitmanip.patch 18 KB

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  1. From e243539f72938317c85bb9859576c39b1baf011d Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Thu, 18 Nov 2021 14:25:18 +0800
  4. Subject: [PATCH 16/26] merge sifve change for bitmanip
  5. ---
  6. gcc/config/riscv/bitmanip.md | 446 ++++++++++++++---------------------
  7. 1 file changed, 173 insertions(+), 273 deletions(-)
  8. diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
  9. index ceb5c89dd47..d2e1d6c936b 100644
  10. --- a/gcc/config/riscv/bitmanip.md
  11. +++ b/gcc/config/riscv/bitmanip.md
  12. @@ -1,5 +1,5 @@
  13. ;; Machine description for RISC-V Bit Manipulation operations.
  14. -;; Copyright (C) 2019 Free Software Foundation, Inc.
  15. +;; Copyright (C) 2021 Free Software Foundation, Inc.
  16. ;; This file is part of GCC.
  17. @@ -19,7 +19,7 @@
  18. (define_code_iterator bitmanip_bitwise [and ior])
  19. -(define_code_iterator any_minmax [smin smax umin umax])
  20. +(define_code_iterator bitmanip_minmax [smin umin smax umax])
  21. (define_code_iterator clz_ctz_pcnt [clz ctz popcount])
  22. @@ -31,6 +31,7 @@
  23. (ctz "ctz")
  24. (popcount "popcount")])
  25. +
  26. (define_code_attr bitmanip_insn [(smin "min")
  27. (smax "max")
  28. (umin "minu")
  29. @@ -41,74 +42,206 @@
  30. (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
  31. +;; ZBA extension.
  32. +
  33. +(define_insn "*zero_extendsidi2_bitmanip"
  34. + [(set (match_operand:DI 0 "register_operand" "=r,r")
  35. + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
  36. + "TARGET_64BIT && TARGET_ZBA"
  37. + "@
  38. + zext.w\t%0,%1
  39. + lwu\t%0,%1"
  40. + [(set_attr "type" "bitmanip,load")
  41. + (set_attr "mode" "DI")])
  42. +
  43. +(define_insn "*shNadd"
  44. + [(set (match_operand:X 0 "register_operand" "=r")
  45. + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
  46. + (match_operand:QI 2 "immediate_operand" "I"))
  47. + (match_operand:X 3 "register_operand" "r")))]
  48. + "TARGET_ZBA
  49. + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
  50. + "sh%2add\t%0,%1,%3"
  51. + [(set_attr "type" "bitmanip")
  52. + (set_attr "mode" "<X:MODE>")])
  53. +
  54. +(define_insn "*shNadduw"
  55. + [(set (match_operand:DI 0 "register_operand" "=r")
  56. + (plus:DI
  57. + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
  58. + (match_operand:QI 2 "immediate_operand" "I"))
  59. + (match_operand 3 "immediate_operand" ""))
  60. + (match_operand:DI 4 "register_operand" "r")))]
  61. + "TARGET_64BIT && TARGET_ZBA
  62. + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
  63. + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
  64. + "sh%2add.uw\t%0,%1,%4"
  65. + [(set_attr "type" "bitmanip")
  66. + (set_attr "mode" "DI")])
  67. +
  68. +(define_insn "*add.uw"
  69. + [(set (match_operand:DI 0 "register_operand" "=r")
  70. + (plus:DI (zero_extend:DI
  71. + (match_operand:SI 1 "register_operand" "r"))
  72. + (match_operand:DI 2 "register_operand" "r")))]
  73. + "TARGET_64BIT && TARGET_ZBA"
  74. + "add.uw\t%0,%1,%2"
  75. + [(set_attr "type" "bitmanip")
  76. + (set_attr "mode" "DI")])
  77. +
  78. +(define_insn "*slliuw"
  79. + [(set (match_operand:DI 0 "register_operand" "=r")
  80. + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
  81. + (match_operand:QI 2 "immediate_operand" "I"))
  82. + (match_operand 3 "immediate_operand" "")))]
  83. + "TARGET_64BIT && TARGET_ZBA
  84. + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
  85. + "slli.uw\t%0,%1,%2"
  86. + [(set_attr "type" "bitmanip")
  87. + (set_attr "mode" "DI")])
  88. +
  89. +;; ZBB extension.
  90. +
  91. +(define_insn "*<optab>_not<mode>"
  92. + [(set (match_operand:X 0 "register_operand" "=r")
  93. + (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
  94. + (match_operand:X 2 "register_operand" "r")))]
  95. + "TARGET_ZBB"
  96. + "<insn>n\t%0,%2,%1"
  97. + [(set_attr "type" "bitmanip")
  98. + (set_attr "mode" "<X:MODE>")])
  99. +
  100. +(define_insn "*xor_not<mode>"
  101. + [(set (match_operand:X 0 "register_operand" "=r")
  102. + (not:X (xor:X (match_operand:X 1 "register_operand" "r")
  103. + (match_operand:X 2 "register_operand" "r"))))]
  104. + "TARGET_ZBB"
  105. + "xnor\t%0,%1,%2"
  106. + [(set_attr "type" "bitmanip")
  107. + (set_attr "mode" "<X:MODE>")])
  108. +
  109. (define_insn "<bitmanip_optab>si2"
  110. [(set (match_operand:SI 0 "register_operand" "=r")
  111. - (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
  112. + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
  113. "TARGET_ZBB"
  114. { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
  115. - [(set_attr "type" "bitmanip")])
  116. + [(set_attr "type" "bitmanip")
  117. + (set_attr "mode" "SI")])
  118. -;; TODO: In theory zero_extend should be OK to combine too, since the output
  119. -;; range is 0 ~ 32, zero_extend or sign_extend will get same result.
  120. (define_insn "*<bitmanip_optab>disi2"
  121. [(set (match_operand:DI 0 "register_operand" "=r")
  122. - (sign_extend:DI
  123. - (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
  124. + (sign_extend:DI
  125. + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
  126. "TARGET_64BIT && TARGET_ZBB"
  127. "<bitmanip_insn>w\t%0,%1"
  128. - [(set_attr "type" "bitmanip")])
  129. + [(set_attr "type" "bitmanip")
  130. + (set_attr "mode" "SI")])
  131. (define_insn "<bitmanip_optab>di2"
  132. [(set (match_operand:DI 0 "register_operand" "=r")
  133. - (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
  134. + (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
  135. "TARGET_64BIT && TARGET_ZBB"
  136. "<bitmanip_insn>\t%0,%1"
  137. - [(set_attr "type" "bitmanip")])
  138. + [(set_attr "type" "bitmanip")
  139. + (set_attr "mode" "DI")])
  140. -(define_insn "*<optab>_not<mode>"
  141. - [(set (match_operand:X 0 "register_operand" "=r")
  142. - (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
  143. - (match_operand:X 2 "register_operand" "r")))]
  144. +(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
  145. + [(set (match_operand:GPR 0 "register_operand" "=r,r")
  146. + (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
  147. "TARGET_ZBB"
  148. - "<insn>n\t%0,%2,%1"
  149. - [(set_attr "type" "bitmanip")])
  150. + "@
  151. + zext.h\t%0,%1
  152. + lhu\t%0,%1"
  153. + [(set_attr "type" "bitmanip,load")
  154. + (set_attr "mode" "<GPR:MODE>")])
  155. -(define_insn "*xor_not<mode>"
  156. - [(set (match_operand:X 0 "register_operand" "=r")
  157. - (not:X (xor:X (match_operand:X 1 "register_operand" "r")
  158. - (match_operand:X 2 "register_operand" "r"))))]
  159. +(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_zbb"
  160. + [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
  161. + (sign_extend:SUPERQI
  162. + (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
  163. "TARGET_ZBB"
  164. - "xnor\t%0,%1,%2"
  165. - [(set_attr "type" "bitmanip")])
  166. -
  167. -;;; ??? pack
  168. + "@
  169. + sext.<SHORT:size>\t%0,%1
  170. + l<SHORT:size>\t%0,%1"
  171. + [(set_attr "type" "bitmanip,load")
  172. + (set_attr "mode" "<SUPERQI:MODE>")])
  173. -(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
  174. - [(set (match_operand:GPR 0 "register_operand" "=r,r")
  175. - (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
  176. +(define_insn "*zero_extendhi<GPR:mode>2_zbb"
  177. + [(set (match_operand:GPR 0 "register_operand" "=r,r")
  178. + (zero_extend:GPR
  179. + (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
  180. "TARGET_ZBB"
  181. "@
  182. zext.h\t%0,%1
  183. lhu\t%0,%1"
  184. - [(set_attr "type" "bitmanip,load")])
  185. + [(set_attr "type" "bitmanip,load")
  186. + (set_attr "mode" "HI")])
  187. -(define_insn "*zero_extendsidi2_bitmanip"
  188. - [(set (match_operand:DI 0 "register_operand" "=r,r")
  189. - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
  190. - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBA)"
  191. - "@
  192. - zext.w\t%0,%1
  193. - lwu\t%0,%1"
  194. - [(set_attr "type" "bitmanip,load")])
  195. +(define_insn "rotrsi3"
  196. + [(set (match_operand:SI 0 "register_operand" "=r")
  197. + (rotatert:SI (match_operand:SI 1 "register_operand" "r")
  198. + (match_operand:QI 2 "arith_operand" "rI")))]
  199. + "TARGET_ZBB"
  200. + { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
  201. + [(set_attr "type" "bitmanip")])
  202. +
  203. +(define_insn "rotrdi3"
  204. + [(set (match_operand:DI 0 "register_operand" "=r")
  205. + (rotatert:DI (match_operand:DI 1 "register_operand" "r")
  206. + (match_operand:QI 2 "arith_operand" "rI")))]
  207. + "TARGET_64BIT && TARGET_ZBB"
  208. + "ror%i2\t%0,%1,%2"
  209. + [(set_attr "type" "bitmanip")])
  210. +
  211. +(define_insn "rotrsi3_sext"
  212. + [(set (match_operand:DI 0 "register_operand" "=r")
  213. + (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
  214. + (match_operand:QI 2 "register_operand" "r"))))]
  215. + "TARGET_64BIT && TARGET_ZBB"
  216. + "rorw\t%0,%1,%2"
  217. + [(set_attr "type" "bitmanip")])
  218. +
  219. +(define_insn "rotlsi3"
  220. + [(set (match_operand:SI 0 "register_operand" "=r")
  221. + (rotate:SI (match_operand:SI 1 "register_operand" "r")
  222. + (match_operand:QI 2 "register_operand" "r")))]
  223. + "TARGET_ZBB"
  224. + { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
  225. + [(set_attr "type" "bitmanip")])
  226. +
  227. +(define_insn "rotldi3"
  228. + [(set (match_operand:DI 0 "register_operand" "=r")
  229. + (rotate:DI (match_operand:DI 1 "register_operand" "r")
  230. + (match_operand:QI 2 "register_operand" "r")))]
  231. + "TARGET_64BIT && TARGET_ZBB"
  232. + "rol\t%0,%1,%2"
  233. + [(set_attr "type" "bitmanip")])
  234. +
  235. +(define_insn "rotlsi3_sext"
  236. + [(set (match_operand:DI 0 "register_operand" "=r")
  237. + (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  238. + (match_operand:QI 2 "register_operand" "r"))))]
  239. + "TARGET_64BIT && TARGET_ZBB"
  240. + "rolw\t%0,%1,%2"
  241. + [(set_attr "type" "bitmanip")])
  242. +
  243. +(define_insn "bswap<mode>2"
  244. + [(set (match_operand:X 0 "register_operand" "=r")
  245. + (bswap:X (match_operand:X 1 "register_operand" "r")))]
  246. + "TARGET_64BIT && TARGET_ZBB"
  247. + "rev8\t%0,%1"
  248. + [(set_attr "type" "bitmanip")])
  249. (define_insn "<bitmanip_optab><mode>3"
  250. [(set (match_operand:X 0 "register_operand" "=r")
  251. - (any_minmax:X (match_operand:X 1 "register_operand" "r")
  252. - (match_operand:X 2 "register_operand" "r")))]
  253. + (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
  254. + (match_operand:X 2 "register_operand" "r")))]
  255. "TARGET_ZBB"
  256. "<bitmanip_insn>\t%0,%1,%2"
  257. [(set_attr "type" "bitmanip")])
  258. +;; ZBS extension.
  259. +
  260. (define_insn "*bset<mode>"
  261. [(set (match_operand:X 0 "register_operand" "=r")
  262. (ior:X (ashift:X (const_int 1)
  263. @@ -155,41 +288,6 @@
  264. "bseti\t%0,%1,%S2"
  265. [(set_attr "type" "bitmanip")])
  266. -(define_insn "*bsetw"
  267. - [(set (match_operand:DI 0 "register_operand" "=r")
  268. - (sign_extend:DI
  269. - (subreg:SI
  270. - (ior:DI (subreg:DI
  271. - (ashift:SI (const_int 1)
  272. - (match_operand:QI 2 "register_operand" "r")) 0)
  273. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  274. - "TARGET_64BIT && TARGET_ZBS"
  275. - "bsetw\t%0,%1,%2"
  276. - [(set_attr "type" "bitmanip")])
  277. -
  278. -(define_insn "*bsetw_mask"
  279. - [(set (match_operand:DI 0 "register_operand" "=r")
  280. - (sign_extend:DI
  281. - (subreg:SI
  282. - (ior:DI (subreg:DI
  283. - (ashift:SI
  284. - (const_int 1)
  285. - (subreg:QI
  286. - (and:DI (match_operand:DI 2 "register_operand" "r")
  287. - (match_operand 3 "const31_operand" "i")) 0)) 0)
  288. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  289. - "TARGET_64BIT && TARGET_ZBS"
  290. - "bsetw\t%0,%1,%2"
  291. - [(set_attr "type" "bitmanip")])
  292. -
  293. -(define_insn "*bsetiw"
  294. - [(set (match_operand:DI 0 "register_operand" "=r")
  295. - (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  296. - (match_operand 2 "single_bit_mask_operand" "i")))]
  297. - "TARGET_64BIT && TARGET_ZBS"
  298. - "bsetiw\t%0,%1,%S2"
  299. - [(set_attr "type" "bitmanip")])
  300. -
  301. (define_insn "*bclr<mode>"
  302. [(set (match_operand:X 0 "register_operand" "=r")
  303. (and:X (rotate:X (const_int -2)
  304. @@ -207,27 +305,6 @@
  305. "bclri\t%0,%1,%T2"
  306. [(set_attr "type" "bitmanip")])
  307. -(define_insn "*bclrw"
  308. - [(set (match_operand:DI 0 "register_operand" "=r")
  309. - (sign_extend:DI
  310. - (subreg:SI
  311. - (and:DI
  312. - (not:DI (subreg:DI
  313. - (ashift:SI (const_int 1)
  314. - (match_operand:QI 2 "register_operand" "r")) 0))
  315. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  316. - "TARGET_64BIT && TARGET_ZBS"
  317. - "bclrw\t%0,%1,%2"
  318. - [(set_attr "type" "bitmanip")])
  319. -
  320. -(define_insn "*bclriw"
  321. - [(set (match_operand:DI 0 "register_operand" "=r")
  322. - (and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  323. - (match_operand 2 "not_single_bit_mask_operand" "i")))]
  324. - "TARGET_64BIT && TARGET_ZBS"
  325. - "bclriw\t%0,%1,%T2"
  326. - [(set_attr "type" "bitmanip")])
  327. -
  328. (define_insn "*binv<mode>"
  329. [(set (match_operand:X 0 "register_operand" "=r")
  330. (xor:X (ashift:X (const_int 1)
  331. @@ -245,26 +322,6 @@
  332. "binvi\t%0,%1,%S2"
  333. [(set_attr "type" "bitmanip")])
  334. -(define_insn "*binvw"
  335. - [(set (match_operand:DI 0 "register_operand" "=r")
  336. - (sign_extend:DI
  337. - (subreg:SI
  338. - (xor:DI (subreg:DI
  339. - (ashift:SI (const_int 1)
  340. - (match_operand:QI 2 "register_operand" "r")) 0)
  341. - (match_operand:DI 1 "register_operand" "r")) 0)))]
  342. - "TARGET_64BIT && TARGET_ZBS"
  343. - "binvw\t%0,%1,%2"
  344. - [(set_attr "type" "bitmanip")])
  345. -
  346. -(define_insn "*binviw"
  347. - [(set (match_operand:DI 0 "register_operand" "=r")
  348. - (xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  349. - (match_operand 2 "single_bit_mask_operand" "i")))]
  350. - "TARGET_64BIT && TARGET_ZBS"
  351. - "binviw\t%0,%1,%S2"
  352. - [(set_attr "type" "bitmanip")])
  353. -
  354. (define_insn "*bext<mode>"
  355. [(set (match_operand:X 0 "register_operand" "=r")
  356. (zero_extract:X (match_operand:X 1 "register_operand" "r")
  357. @@ -282,161 +339,4 @@
  358. (match_operand 2 "immediate_operand" "i")))]
  359. "TARGET_ZBS"
  360. "bexti\t%0,%1,%2"
  361. - [(set_attr "type" "bitmanip")])
  362. -
  363. -(define_insn "*bextw"
  364. - [(set (match_operand:DI 0 "register_operand" "=r")
  365. - (and:DI
  366. - (subreg:DI
  367. - (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
  368. - (match_operand:QI 2 "register_operand" "r")) 0)
  369. - (const_int 1)))]
  370. - "TARGET_64BIT && TARGET_ZBS"
  371. - "bextw\t%0,%1,%2"
  372. - [(set_attr "type" "bitmanip")])
  373. -
  374. -;;; ??? s[lr]o*
  375. -
  376. -(define_insn "rotrsi3"
  377. - [(set (match_operand:SI 0 "register_operand" "=r")
  378. - (rotatert:SI (match_operand:SI 1 "register_operand" "r")
  379. - (match_operand:QI 2 "arith_operand" "rI")))]
  380. - "TARGET_ZBB"
  381. - { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
  382. - [(set_attr "type" "bitmanip")])
  383. -
  384. -(define_insn "rotrdi3"
  385. - [(set (match_operand:DI 0 "register_operand" "=r")
  386. - (rotatert:DI (match_operand:DI 1 "register_operand" "r")
  387. - (match_operand:QI 2 "arith_operand" "rI")))]
  388. - "TARGET_64BIT && TARGET_ZBB"
  389. - "ror%i2\t%0,%1,%2"
  390. - [(set_attr "type" "bitmanip")])
  391. -
  392. -(define_expand "riscv_rolw"
  393. - [(match_operand:SI 0 "register_operand" "=r")
  394. - (match_operand:SI 1 "register_operand" "r")
  395. - (match_operand:SI 2 "register_operand" "r")]
  396. - "TARGET_64BIT && TARGET_ZBB"
  397. -{
  398. - emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2]));
  399. - DONE;
  400. -})
  401. -
  402. -(define_insn "rotlsi3"
  403. - [(set (match_operand:SI 0 "register_operand" "=r")
  404. - (rotate:SI (match_operand:SI 1 "register_operand" "r")
  405. - (match_operand:QI 2 "register_operand" "r")))]
  406. - "TARGET_ZBB"
  407. - { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
  408. - [(set_attr "type" "bitmanip")])
  409. -
  410. -(define_insn "rotldi3"
  411. - [(set (match_operand:DI 0 "register_operand" "=r")
  412. - (rotate:DI (match_operand:DI 1 "register_operand" "r")
  413. - (match_operand:QI 2 "register_operand" "r")))]
  414. - "TARGET_64BIT && TARGET_ZBB"
  415. - "rol\t%0,%1,%2"
  416. - [(set_attr "type" "bitmanip")])
  417. -
  418. -(define_insn "rotlsi3_sext"
  419. - [(set (match_operand:DI 0 "register_operand" "=r")
  420. - (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  421. - (match_operand:QI 2 "register_operand" "r"))))]
  422. - "TARGET_64BIT && TARGET_ZBB"
  423. - "rolw\t%0,%1,%2"
  424. - [(set_attr "type" "bitmanip")])
  425. -
  426. -;;; ??? grev
  427. -
  428. -(define_insn "bswapsi2"
  429. - [(set (match_operand:SI 0 "register_operand" "=r")
  430. - (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
  431. - "TARGET_ZBB"
  432. -{
  433. - if (TARGET_64BIT)
  434. - return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1";
  435. - else
  436. - return "rev8\t%0,%1";
  437. -}
  438. - [(set_attr "type" "bitmanip")])
  439. -
  440. -(define_insn "bswapdi2"
  441. - [(set (match_operand:DI 0 "register_operand" "=r")
  442. - (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
  443. - "TARGET_64BIT && TARGET_ZBB"
  444. - "rev8\t%0,%1"
  445. - [(set_attr "type" "bitmanip")])
  446. -
  447. -;;; ??? shfl/unshfl
  448. -
  449. -;;; ??? bext/bdep
  450. -
  451. -;;; ??? clmul
  452. -
  453. -;;; ??? crc
  454. -
  455. -;;; ??? bmat
  456. -
  457. -;; ??? Can we do this by using the % communtative constraint?
  458. -
  459. -;;; ??? cmov
  460. -
  461. -;;; ??? fs[lr]
  462. -
  463. -(define_insn "*shNadd"
  464. - [(set (match_operand:X 0 "register_operand" "=r")
  465. - (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
  466. - (match_operand:QI 2 "immediate_operand" "I"))
  467. - (match_operand:X 3 "register_operand" "r")))]
  468. - "TARGET_ZBA
  469. - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
  470. - "sh%2add\t%0,%1,%3"
  471. - [(set_attr "type" "bitmanip")])
  472. -
  473. -(define_insn "*shNadduw"
  474. - [(set (match_operand:DI 0 "register_operand" "=r")
  475. - (plus:DI
  476. - (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
  477. - (match_operand:QI 2 "immediate_operand" "I"))
  478. - (match_operand 3 "immediate_operand" ""))
  479. - (match_operand:DI 4 "register_operand" "r")))]
  480. - "TARGET_64BIT && TARGET_ZBA
  481. - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
  482. - && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
  483. - "sh%2add.uw\t%0,%1,%4"
  484. - [(set_attr "type" "bitmanip")])
  485. -
  486. -(define_insn "*add.uw"
  487. - [(set (match_operand:DI 0 "register_operand" "=r")
  488. - (plus:DI (zero_extend:DI
  489. - (match_operand:SI 1 "register_operand" "r"))
  490. - (match_operand:DI 2 "register_operand" "r")))]
  491. - "TARGET_64BIT && TARGET_ZBA"
  492. - "add.uw\t%0,%1,%2"
  493. - [(set_attr "type" "bitmanip")])
  494. -
  495. -(define_insn "*slliuw"
  496. - [(set (match_operand:DI 0 "register_operand" "=r")
  497. - (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
  498. - (match_operand:QI 2 "immediate_operand" "I"))
  499. - (match_operand 3 "immediate_operand" "")))]
  500. - "TARGET_64BIT && TARGET_ZBA
  501. - && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
  502. - "slli.uw\t%0,%1,%2"
  503. - [(set_attr "type" "bitmanip")])
  504. -
  505. -;; ??? bfxp
  506. -
  507. -;; sext
  508. -
  509. -(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip"
  510. - [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
  511. - (sign_extend:SUPERQI
  512. - (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
  513. - "TARGET_ZBB"
  514. - "@
  515. - sext.<SHORT:size>\t%0,%1
  516. - l<SHORT:size>\t%0,%1"
  517. - [(set_attr "type" "bitmanip")
  518. - (set_attr "length" "4")])
  519. + [(set_attr "type" "bitmanip")])
  520. \ No newline at end of file
  521. --
  522. 2.33.1