From e243539f72938317c85bb9859576c39b1baf011d Mon Sep 17 00:00:00 2001 From: "yilun.xie" Date: Thu, 18 Nov 2021 14:25:18 +0800 Subject: [PATCH 16/26] merge sifve change for bitmanip --- gcc/config/riscv/bitmanip.md | 446 ++++++++++++++--------------------- 1 file changed, 173 insertions(+), 273 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index ceb5c89dd47..d2e1d6c936b 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -1,5 +1,5 @@ ;; Machine description for RISC-V Bit Manipulation operations. -;; Copyright (C) 2019 Free Software Foundation, Inc. +;; Copyright (C) 2021 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -19,7 +19,7 @@ (define_code_iterator bitmanip_bitwise [and ior]) -(define_code_iterator any_minmax [smin smax umin umax]) +(define_code_iterator bitmanip_minmax [smin umin smax umax]) (define_code_iterator clz_ctz_pcnt [clz ctz popcount]) @@ -31,6 +31,7 @@ (ctz "ctz") (popcount "popcount")]) + (define_code_attr bitmanip_insn [(smin "min") (smax "max") (umin "minu") @@ -41,74 +42,206 @@ (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")]) +;; ZBA extension. + +(define_insn "*zero_extendsidi2_bitmanip" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] + "TARGET_64BIT && TARGET_ZBA" + "@ + zext.w\t%0,%1 + lwu\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "DI")]) + +(define_insn "*shNadd" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:X 3 "register_operand" "r")))] + "TARGET_ZBA + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)" + "sh%2add\t%0,%1,%3" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*shNadduw" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand 3 "immediate_operand" "")) + (match_operand:DI 4 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBA + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" + "sh%2add.uw\t%0,%1,%4" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) + +(define_insn "*add.uw" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (zero_extend:DI + (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBA" + "add.uw\t%0,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) + +(define_insn "*slliuw" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand 3 "immediate_operand" "")))] + "TARGET_64BIT && TARGET_ZBA + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" + "slli.uw\t%0,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) + +;; ZBB extension. + +(define_insn "*_not" + [(set (match_operand:X 0 "register_operand" "=r") + (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) + (match_operand:X 2 "register_operand" "r")))] + "TARGET_ZBB" + "n\t%0,%2,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*xor_not" + [(set (match_operand:X 0 "register_operand" "=r") + (not:X (xor:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r"))))] + "TARGET_ZBB" + "xnor\t%0,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + (define_insn "si2" [(set (match_operand:SI 0 "register_operand" "=r") - (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" { return TARGET_64BIT ? "w\t%0,%1" : "\t%0,%1"; } - [(set_attr "type" "bitmanip")]) + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) -;; TODO: In theory zero_extend should be OK to combine too, since the output -;; range is 0 ~ 32, zero_extend or sign_extend will get same result. (define_insn "*disi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI - (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] + (sign_extend:DI + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "w\t%0,%1" - [(set_attr "type" "bitmanip")]) + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) (define_insn "di2" [(set (match_operand:DI 0 "register_operand" "=r") - (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] + (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBB" "\t%0,%1" - [(set_attr "type" "bitmanip")]) + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) -(define_insn "*_not" - [(set (match_operand:X 0 "register_operand" "=r") - (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) - (match_operand:X 2 "register_operand" "r")))] +(define_insn "*zero_extendhi2_bitmanip" + [(set (match_operand:GPR 0 "register_operand" "=r,r") + (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))] "TARGET_ZBB" - "n\t%0,%2,%1" - [(set_attr "type" "bitmanip")]) + "@ + zext.h\t%0,%1 + lhu\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "")]) -(define_insn "*xor_not" - [(set (match_operand:X 0 "register_operand" "=r") - (not:X (xor:X (match_operand:X 1 "register_operand" "r") - (match_operand:X 2 "register_operand" "r"))))] +(define_insn "*extend2_zbb" + [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") + (sign_extend:SUPERQI + (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] "TARGET_ZBB" - "xnor\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -;;; ??? pack + "@ + sext.\t%0,%1 + l\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "")]) -(define_insn "*zero_extendhi2_bitmanip" - [(set (match_operand:GPR 0 "register_operand" "=r,r") - (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))] +(define_insn "*zero_extendhi2_zbb" + [(set (match_operand:GPR 0 "register_operand" "=r,r") + (zero_extend:GPR + (match_operand:HI 1 "nonimmediate_operand" " r,m")))] "TARGET_ZBB" "@ zext.h\t%0,%1 lhu\t%0,%1" - [(set_attr "type" "bitmanip,load")]) + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "HI")]) -(define_insn "*zero_extendsidi2_bitmanip" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBA)" - "@ - zext.w\t%0,%1 - lwu\t%0,%1" - [(set_attr "type" "bitmanip,load")]) +(define_insn "rotrsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotatert:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "arith_operand" "rI")))] + "TARGET_ZBB" + { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; } + [(set_attr "type" "bitmanip")]) + +(define_insn "rotrdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (rotatert:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "arith_operand" "rI")))] + "TARGET_64BIT && TARGET_ZBB" + "ror%i2\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_insn "rotrsi3_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r"))))] + "TARGET_64BIT && TARGET_ZBB" + "rorw\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_insn "rotlsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotate:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r")))] + "TARGET_ZBB" + { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; } + [(set_attr "type" "bitmanip")]) + +(define_insn "rotldi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (rotate:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBB" + "rol\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_insn "rotlsi3_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r"))))] + "TARGET_64BIT && TARGET_ZBB" + "rolw\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_insn "bswap2" + [(set (match_operand:X 0 "register_operand" "=r") + (bswap:X (match_operand:X 1 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBB" + "rev8\t%0,%1" + [(set_attr "type" "bitmanip")]) (define_insn "3" [(set (match_operand:X 0 "register_operand" "=r") - (any_minmax:X (match_operand:X 1 "register_operand" "r") - (match_operand:X 2 "register_operand" "r")))] + (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")))] "TARGET_ZBB" "\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +;; ZBS extension. + (define_insn "*bset" [(set (match_operand:X 0 "register_operand" "=r") (ior:X (ashift:X (const_int 1) @@ -155,41 +288,6 @@ "bseti\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) -(define_insn "*bsetw" - [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI - (subreg:SI - (ior:DI (subreg:DI - (ashift:SI (const_int 1) - (match_operand:QI 2 "register_operand" "r")) 0) - (match_operand:DI 1 "register_operand" "r")) 0)))] - "TARGET_64BIT && TARGET_ZBS" - "bsetw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_insn "*bsetw_mask" - [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI - (subreg:SI - (ior:DI (subreg:DI - (ashift:SI - (const_int 1) - (subreg:QI - (and:DI (match_operand:DI 2 "register_operand" "r") - (match_operand 3 "const31_operand" "i")) 0)) 0) - (match_operand:DI 1 "register_operand" "r")) 0)))] - "TARGET_64BIT && TARGET_ZBS" - "bsetw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_insn "*bsetiw" - [(set (match_operand:DI 0 "register_operand" "=r") - (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand 2 "single_bit_mask_operand" "i")))] - "TARGET_64BIT && TARGET_ZBS" - "bsetiw\t%0,%1,%S2" - [(set_attr "type" "bitmanip")]) - (define_insn "*bclr" [(set (match_operand:X 0 "register_operand" "=r") (and:X (rotate:X (const_int -2) @@ -207,27 +305,6 @@ "bclri\t%0,%1,%T2" [(set_attr "type" "bitmanip")]) -(define_insn "*bclrw" - [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI - (subreg:SI - (and:DI - (not:DI (subreg:DI - (ashift:SI (const_int 1) - (match_operand:QI 2 "register_operand" "r")) 0)) - (match_operand:DI 1 "register_operand" "r")) 0)))] - "TARGET_64BIT && TARGET_ZBS" - "bclrw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_insn "*bclriw" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand 2 "not_single_bit_mask_operand" "i")))] - "TARGET_64BIT && TARGET_ZBS" - "bclriw\t%0,%1,%T2" - [(set_attr "type" "bitmanip")]) - (define_insn "*binv" [(set (match_operand:X 0 "register_operand" "=r") (xor:X (ashift:X (const_int 1) @@ -245,26 +322,6 @@ "binvi\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) -(define_insn "*binvw" - [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI - (subreg:SI - (xor:DI (subreg:DI - (ashift:SI (const_int 1) - (match_operand:QI 2 "register_operand" "r")) 0) - (match_operand:DI 1 "register_operand" "r")) 0)))] - "TARGET_64BIT && TARGET_ZBS" - "binvw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_insn "*binviw" - [(set (match_operand:DI 0 "register_operand" "=r") - (xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand 2 "single_bit_mask_operand" "i")))] - "TARGET_64BIT && TARGET_ZBS" - "binviw\t%0,%1,%S2" - [(set_attr "type" "bitmanip")]) - (define_insn "*bext" [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") @@ -282,161 +339,4 @@ (match_operand 2 "immediate_operand" "i")))] "TARGET_ZBS" "bexti\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_insn "*bextw" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI - (subreg:DI - (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r")) 0) - (const_int 1)))] - "TARGET_64BIT && TARGET_ZBS" - "bextw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -;;; ??? s[lr]o* - -(define_insn "rotrsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (rotatert:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_ZBB" - { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; } - [(set_attr "type" "bitmanip")]) - -(define_insn "rotrdi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (rotatert:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_64BIT && TARGET_ZBB" - "ror%i2\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_expand "riscv_rolw" - [(match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r")] - "TARGET_64BIT && TARGET_ZBB" -{ - emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_insn "rotlsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (rotate:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r")))] - "TARGET_ZBB" - { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; } - [(set_attr "type" "bitmanip")]) - -(define_insn "rotldi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (rotate:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBB" - "rol\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_insn "rotlsi3_sext" - [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_64BIT && TARGET_ZBB" - "rolw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -;;; ??? grev - -(define_insn "bswapsi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (bswap:SI (match_operand:SI 1 "register_operand" "r")))] - "TARGET_ZBB" -{ - if (TARGET_64BIT) - return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1"; - else - return "rev8\t%0,%1"; -} - [(set_attr "type" "bitmanip")]) - -(define_insn "bswapdi2" - [(set (match_operand:DI 0 "register_operand" "=r") - (bswap:DI (match_operand:DI 1 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBB" - "rev8\t%0,%1" - [(set_attr "type" "bitmanip")]) - -;;; ??? shfl/unshfl - -;;; ??? bext/bdep - -;;; ??? clmul - -;;; ??? crc - -;;; ??? bmat - -;; ??? Can we do this by using the % communtative constraint? - -;;; ??? cmov - -;;; ??? fs[lr] - -(define_insn "*shNadd" - [(set (match_operand:X 0 "register_operand" "=r") - (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) - (match_operand:X 3 "register_operand" "r")))] - "TARGET_ZBA - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)" - "sh%2add\t%0,%1,%3" - [(set_attr "type" "bitmanip")]) - -(define_insn "*shNadduw" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI - (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) - (match_operand 3 "immediate_operand" "")) - (match_operand:DI 4 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBA - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) - && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" - "sh%2add.uw\t%0,%1,%4" - [(set_attr "type" "bitmanip")]) - -(define_insn "*add.uw" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (zero_extend:DI - (match_operand:SI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBA" - "add.uw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -(define_insn "*slliuw" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) - (match_operand 3 "immediate_operand" "")))] - "TARGET_64BIT && TARGET_ZBA - && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" - "slli.uw\t%0,%1,%2" - [(set_attr "type" "bitmanip")]) - -;; ??? bfxp - -;; sext - -(define_insn "*extend2_bitmanip" - [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") - (sign_extend:SUPERQI - (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] - "TARGET_ZBB" - "@ - sext.\t%0,%1 - l\t%0,%1" - [(set_attr "type" "bitmanip") - (set_attr "length" "4")]) + [(set_attr "type" "bitmanip")]) \ No newline at end of file -- 2.33.1