0011-remove-b-flag-and-use-zba_zbb_zbc_zbs-instead.patch 2.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677
  1. From b4060fc036995229bd9c4c0d7d9b74b45a4ccf50 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Wed, 27 Oct 2021 19:09:37 -0700
  4. Subject: [PATCH 11/15] remove 'b' flag and use zba_zbb_zbc_zbs instead
  5. ---
  6. gcc/common/config/riscv/riscv-common.c | 1 -
  7. gcc/config/riscv/riscv-opts.h | 18 +++++++++---------
  8. gcc/config/riscv/riscv.opt | 4 +---
  9. 3 files changed, 10 insertions(+), 13 deletions(-)
  10. diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
  11. index 48eb558bcf5..a00b20e065a 100644
  12. --- a/gcc/common/config/riscv/riscv-common.c
  13. +++ b/gcc/common/config/riscv/riscv-common.c
  14. @@ -105,7 +105,6 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
  15. {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
  16. {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
  17. - {"b", ISA_SPEC_CLASS_NONE, 1, 0},
  18. {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
  19. {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
  20. {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
  21. diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
  22. index 61d1e9d96d8..617feebc7bb 100644
  23. --- a/gcc/config/riscv/riscv-opts.h
  24. +++ b/gcc/config/riscv/riscv-opts.h
  25. @@ -67,15 +67,15 @@ enum stack_protector_guard {
  26. SSP_GLOBAL /* global canary */
  27. };
  28. -#define MASK_ZBA (1 << 0)
  29. -#define MASK_ZBB (1 << 1)
  30. -#define MASK_ZBS (1 << 2)
  31. -#define MASK_ZBC (1 << 3)
  32. -
  33. -#define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
  34. -#define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
  35. -#define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
  36. -#define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
  37. +#define MASK_ZBA (1 << 0)
  38. +#define MASK_ZBB (1 << 1)
  39. +#define MASK_ZBC (1 << 2)
  40. +#define MASK_ZBS (1 << 3)
  41. +
  42. +#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
  43. +#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
  44. +#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
  45. +#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
  46. #define MASK_ZICSR (1 << 0)
  47. #define MASK_ZIFENCEI (1 << 1)
  48. diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
  49. index 0e73e2ab758..7f7e1c4f50b 100644
  50. --- a/gcc/config/riscv/riscv.opt
  51. +++ b/gcc/config/riscv/riscv.opt
  52. @@ -136,8 +136,6 @@ Mask(64BIT)
  53. Mask(MUL)
  54. -Mask(BITMANIP)
  55. -
  56. Mask(ATOMIC)
  57. Mask(HARD_FLOAT)
  58. @@ -198,7 +196,7 @@ TargetVariable
  59. int riscv_zi_subext
  60. TargetVariable
  61. -int riscv_bitmanip_subext
  62. +int riscv_zb_subext
  63. Enum
  64. Name(isa_spec_class) Type(enum riscv_isa_spec_class)
  65. --
  66. 2.33.1