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- From b4060fc036995229bd9c4c0d7d9b74b45a4ccf50 Mon Sep 17 00:00:00 2001
- From: "max.ma" <max.ma@starfivetech.com>
- Date: Wed, 27 Oct 2021 19:09:37 -0700
- Subject: [PATCH 11/15] remove 'b' flag and use zba_zbb_zbc_zbs instead
- ---
- gcc/common/config/riscv/riscv-common.c | 1 -
- gcc/config/riscv/riscv-opts.h | 18 +++++++++---------
- gcc/config/riscv/riscv.opt | 4 +---
- 3 files changed, 10 insertions(+), 13 deletions(-)
- diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
- index 48eb558bcf5..a00b20e065a 100644
- --- a/gcc/common/config/riscv/riscv-common.c
- +++ b/gcc/common/config/riscv/riscv-common.c
- @@ -105,7 +105,6 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
- {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
- {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
-
- - {"b", ISA_SPEC_CLASS_NONE, 1, 0},
- {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
- {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
- {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
- diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
- index 61d1e9d96d8..617feebc7bb 100644
- --- a/gcc/config/riscv/riscv-opts.h
- +++ b/gcc/config/riscv/riscv-opts.h
- @@ -67,15 +67,15 @@ enum stack_protector_guard {
- SSP_GLOBAL /* global canary */
- };
-
- -#define MASK_ZBA (1 << 0)
- -#define MASK_ZBB (1 << 1)
- -#define MASK_ZBS (1 << 2)
- -#define MASK_ZBC (1 << 3)
- -
- -#define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
- -#define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
- -#define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
- -#define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
- +#define MASK_ZBA (1 << 0)
- +#define MASK_ZBB (1 << 1)
- +#define MASK_ZBC (1 << 2)
- +#define MASK_ZBS (1 << 3)
- +
- +#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
- +#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
- +#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
- +#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
-
- #define MASK_ZICSR (1 << 0)
- #define MASK_ZIFENCEI (1 << 1)
- diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
- index 0e73e2ab758..7f7e1c4f50b 100644
- --- a/gcc/config/riscv/riscv.opt
- +++ b/gcc/config/riscv/riscv.opt
- @@ -136,8 +136,6 @@ Mask(64BIT)
-
- Mask(MUL)
-
- -Mask(BITMANIP)
- -
- Mask(ATOMIC)
-
- Mask(HARD_FLOAT)
- @@ -198,7 +196,7 @@ TargetVariable
- int riscv_zi_subext
-
- TargetVariable
- -int riscv_bitmanip_subext
- +int riscv_zb_subext
-
- Enum
- Name(isa_spec_class) Type(enum riscv_isa_spec_class)
- --
- 2.33.1
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