0038-target-riscv-rvv-1.0-set-X-first-mask-bit-instructio.patch 3.3 KB

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  1. From b31244216af0f936b1839b917e1f0e11d189c760 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 11:54:41 +0800
  4. Subject: [PATCH 038/107] target/riscv: rvv-1.0: set-X-first mask bit
  5. instructions
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32.decode | 6 +++---
  10. target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++-
  11. target/riscv/vector_helper.c | 4 ----
  12. 3 files changed, 7 insertions(+), 8 deletions(-)
  13. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  14. index c66bc4fad1..58ca0a7638 100644
  15. --- a/target/riscv/insn32.decode
  16. +++ b/target/riscv/insn32.decode
  17. @@ -604,9 +604,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
  18. vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
  19. vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
  20. vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
  21. -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
  22. -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
  23. -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
  24. +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
  25. +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
  26. +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
  27. viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
  28. vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
  29. vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
  30. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  31. index 52ad12bf43..ae53c83a8d 100644
  32. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  33. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  34. @@ -2964,7 +2964,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
  35. #define GEN_M_TRANS(NAME) \
  36. static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  37. { \
  38. - if (vext_check_isa_ill(s)) { \
  39. + if (require_rvv(s) && \
  40. + vext_check_isa_ill(s) && \
  41. + require_vm(a->vm, a->rd) && \
  42. + (a->rd != a->rs2)) { \
  43. uint32_t data = 0; \
  44. gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
  45. TCGLabel *over = gen_new_label(); \
  46. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  47. index fbde77326e..cb12585956 100644
  48. --- a/target/riscv/vector_helper.c
  49. +++ b/target/riscv/vector_helper.c
  50. @@ -4466,7 +4466,6 @@ enum set_mask_type {
  51. static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
  52. uint32_t desc, enum set_mask_type type)
  53. {
  54. - uint32_t vlmax = env_archcpu(env)->cfg.vlen;
  55. uint32_t vm = vext_vm(desc);
  56. uint32_t vl = env->vl;
  57. int i;
  58. @@ -4496,9 +4495,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
  59. }
  60. }
  61. }
  62. - for (; i < vlmax; i++) {
  63. - vext_set_elem_mask(vd, i, 0);
  64. - }
  65. }
  66. void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
  67. --
  68. 2.33.1