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- From b31244216af0f936b1839b917e1f0e11d189c760 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Thu, 2 Jul 2020 11:54:41 +0800
- Subject: [PATCH 038/107] target/riscv: rvv-1.0: set-X-first mask bit
- instructions
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- ---
- target/riscv/insn32.decode | 6 +++---
- target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++-
- target/riscv/vector_helper.c | 4 ----
- 3 files changed, 7 insertions(+), 8 deletions(-)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index c66bc4fad1..58ca0a7638 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -604,9 +604,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
- vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
- vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
- vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
- -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
- -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
- -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
- +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
- +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
- +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
- viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
- vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
- vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index 52ad12bf43..ae53c83a8d 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -2964,7 +2964,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
- #define GEN_M_TRANS(NAME) \
- static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- { \
- - if (vext_check_isa_ill(s)) { \
- + if (require_rvv(s) && \
- + vext_check_isa_ill(s) && \
- + require_vm(a->vm, a->rd) && \
- + (a->rd != a->rs2)) { \
- uint32_t data = 0; \
- gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
- index fbde77326e..cb12585956 100644
- --- a/target/riscv/vector_helper.c
- +++ b/target/riscv/vector_helper.c
- @@ -4466,7 +4466,6 @@ enum set_mask_type {
- static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc, enum set_mask_type type)
- {
- - uint32_t vlmax = env_archcpu(env)->cfg.vlen;
- uint32_t vm = vext_vm(desc);
- uint32_t vl = env->vl;
- int i;
- @@ -4496,9 +4495,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
- }
- }
- }
- - for (; i < vlmax; i++) {
- - vext_set_elem_mask(vd, i, 0);
- - }
- }
-
- void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
- --
- 2.33.1
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