0020-target-riscv-rvv-1.0-add-fractional-LMUL.patch 4.0 KB

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  1. From 37f5622ac3d829866e2d81a1c5f46dc67ba22420 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Fri, 14 Aug 2020 17:35:55 +0800
  4. Subject: [PATCH 020/107] target/riscv: rvv-1.0: add fractional LMUL
  5. Introduce the concepts of fractional LMUL for RVV 1.0.
  6. In RVV 1.0, LMUL bits are contiguous in vtype register.
  7. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
  8. and MSTATUS_FS (0x6000) bits.
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  11. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  12. ---
  13. target/riscv/cpu.h | 18 ++++++++++--------
  14. target/riscv/translate.c | 16 ++++++++++++++--
  15. target/riscv/vector_helper.c | 16 ++++++++++++++--
  16. 3 files changed, 38 insertions(+), 12 deletions(-)
  17. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  18. index 8fd7c01567..33cb265304 100644
  19. --- a/target/riscv/cpu.h
  20. +++ b/target/riscv/cpu.h
  21. @@ -105,10 +105,10 @@ typedef struct CPURISCVState CPURISCVState;
  22. #define RV_VLEN_MAX 256
  23. -FIELD(VTYPE, VLMUL, 0, 2)
  24. -FIELD(VTYPE, VSEW, 2, 3)
  25. -FIELD(VTYPE, VEDIV, 5, 2)
  26. -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
  27. +FIELD(VTYPE, VLMUL, 0, 3)
  28. +FIELD(VTYPE, VSEW, 3, 3)
  29. +FIELD(VTYPE, VEDIV, 8, 2)
  30. +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
  31. FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
  32. struct CPURISCVState {
  33. @@ -390,12 +390,14 @@ typedef RISCVCPU ArchCPU;
  34. #include "exec/cpu-all.h"
  35. FIELD(TB_FLAGS, MEM_IDX, 0, 3)
  36. -FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
  37. -FIELD(TB_FLAGS, LMUL, 4, 2)
  38. +FIELD(TB_FLAGS, LMUL, 3, 3)
  39. FIELD(TB_FLAGS, SEW, 6, 3)
  40. -FIELD(TB_FLAGS, VILL, 9, 1)
  41. +/* Skip MSTATUS_VS (0x600) bits */
  42. +FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
  43. +FIELD(TB_FLAGS, VILL, 12, 1)
  44. +/* Skip MSTATUS_FS (0x6000) bits */
  45. /* Is a Hypervisor instruction load/store allowed? */
  46. -FIELD(TB_FLAGS, HLSX, 10, 1)
  47. +FIELD(TB_FLAGS, HLSX, 15, 1)
  48. bool riscv_cpu_is_32bit(CPURISCVState *env);
  49. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  50. index b18f76c344..d10e489cfe 100644
  51. --- a/target/riscv/translate.c
  52. +++ b/target/riscv/translate.c
  53. @@ -61,7 +61,19 @@ typedef struct DisasContext {
  54. bool hlsx;
  55. /* vector extension */
  56. bool vill;
  57. - uint8_t lmul;
  58. + /*
  59. + * Encode LMUL to lmul as follows:
  60. + * LMUL vlmul lmul
  61. + * 1 000 0
  62. + * 2 001 1
  63. + * 4 010 2
  64. + * 8 011 3
  65. + * - 100 -
  66. + * 1/8 101 -3
  67. + * 1/4 110 -2
  68. + * 1/2 111 -1
  69. + */
  70. + int8_t lmul;
  71. uint8_t sew;
  72. uint16_t vlen;
  73. bool vl_eq_vlmax;
  74. @@ -694,7 +706,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
  75. ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
  76. ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
  77. ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
  78. - ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
  79. + ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
  80. ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
  81. ctx->cs = cs;
  82. }
  83. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  84. index dea1d190ed..f28d20a97d 100644
  85. --- a/target/riscv/vector_helper.c
  86. +++ b/target/riscv/vector_helper.c
  87. @@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc)
  88. return FIELD_EX32(simd_data(desc), VDATA, VM);
  89. }
  90. -static inline uint32_t vext_lmul(uint32_t desc)
  91. +/*
  92. + * Encode LMUL to lmul as following:
  93. + * LMUL vlmul lmul
  94. + * 1 000 0
  95. + * 2 001 1
  96. + * 4 010 2
  97. + * 8 011 3
  98. + * - 100 -
  99. + * 1/8 101 -3
  100. + * 1/4 110 -2
  101. + * 1/2 111 -1
  102. + */
  103. +static inline int32_t vext_lmul(uint32_t desc)
  104. {
  105. - return FIELD_EX32(simd_data(desc), VDATA, LMUL);
  106. + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
  107. }
  108. static uint32_t vext_wd(uint32_t desc)
  109. --
  110. 2.33.1