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- From 37f5622ac3d829866e2d81a1c5f46dc67ba22420 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Fri, 14 Aug 2020 17:35:55 +0800
- Subject: [PATCH 020/107] target/riscv: rvv-1.0: add fractional LMUL
- Introduce the concepts of fractional LMUL for RVV 1.0.
- In RVV 1.0, LMUL bits are contiguous in vtype register.
- Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
- and MSTATUS_FS (0x6000) bits.
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
- ---
- target/riscv/cpu.h | 18 ++++++++++--------
- target/riscv/translate.c | 16 ++++++++++++++--
- target/riscv/vector_helper.c | 16 ++++++++++++++--
- 3 files changed, 38 insertions(+), 12 deletions(-)
- diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
- index 8fd7c01567..33cb265304 100644
- --- a/target/riscv/cpu.h
- +++ b/target/riscv/cpu.h
- @@ -105,10 +105,10 @@ typedef struct CPURISCVState CPURISCVState;
-
- #define RV_VLEN_MAX 256
-
- -FIELD(VTYPE, VLMUL, 0, 2)
- -FIELD(VTYPE, VSEW, 2, 3)
- -FIELD(VTYPE, VEDIV, 5, 2)
- -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
- +FIELD(VTYPE, VLMUL, 0, 3)
- +FIELD(VTYPE, VSEW, 3, 3)
- +FIELD(VTYPE, VEDIV, 8, 2)
- +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
- FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
-
- struct CPURISCVState {
- @@ -390,12 +390,14 @@ typedef RISCVCPU ArchCPU;
- #include "exec/cpu-all.h"
-
- FIELD(TB_FLAGS, MEM_IDX, 0, 3)
- -FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
- -FIELD(TB_FLAGS, LMUL, 4, 2)
- +FIELD(TB_FLAGS, LMUL, 3, 3)
- FIELD(TB_FLAGS, SEW, 6, 3)
- -FIELD(TB_FLAGS, VILL, 9, 1)
- +/* Skip MSTATUS_VS (0x600) bits */
- +FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
- +FIELD(TB_FLAGS, VILL, 12, 1)
- +/* Skip MSTATUS_FS (0x6000) bits */
- /* Is a Hypervisor instruction load/store allowed? */
- -FIELD(TB_FLAGS, HLSX, 10, 1)
- +FIELD(TB_FLAGS, HLSX, 15, 1)
-
- bool riscv_cpu_is_32bit(CPURISCVState *env);
-
- diff --git a/target/riscv/translate.c b/target/riscv/translate.c
- index b18f76c344..d10e489cfe 100644
- --- a/target/riscv/translate.c
- +++ b/target/riscv/translate.c
- @@ -61,7 +61,19 @@ typedef struct DisasContext {
- bool hlsx;
- /* vector extension */
- bool vill;
- - uint8_t lmul;
- + /*
- + * Encode LMUL to lmul as follows:
- + * LMUL vlmul lmul
- + * 1 000 0
- + * 2 001 1
- + * 4 010 2
- + * 8 011 3
- + * - 100 -
- + * 1/8 101 -3
- + * 1/4 110 -2
- + * 1/2 111 -1
- + */
- + int8_t lmul;
- uint8_t sew;
- uint16_t vlen;
- bool vl_eq_vlmax;
- @@ -694,7 +706,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
- ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
- ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
- ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
- - ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
- + ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
- ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
- ctx->cs = cs;
- }
- diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
- index dea1d190ed..f28d20a97d 100644
- --- a/target/riscv/vector_helper.c
- +++ b/target/riscv/vector_helper.c
- @@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc)
- return FIELD_EX32(simd_data(desc), VDATA, VM);
- }
-
- -static inline uint32_t vext_lmul(uint32_t desc)
- +/*
- + * Encode LMUL to lmul as following:
- + * LMUL vlmul lmul
- + * 1 000 0
- + * 2 001 1
- + * 4 010 2
- + * 8 011 3
- + * - 100 -
- + * 1/8 101 -3
- + * 1/4 110 -2
- + * 1/2 111 -1
- + */
- +static inline int32_t vext_lmul(uint32_t desc)
- {
- - return FIELD_EX32(simd_data(desc), VDATA, LMUL);
- + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
- }
-
- static uint32_t vext_wd(uint32_t desc)
- --
- 2.33.1
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