0018-target-riscv-rvv-1.0-check-MSTATUS_VS-when-accessing.patch 1.1 KB

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  1. From ea46dc1dd9050c1962ee8e887f14e022d84f4d0c Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Fri, 24 Jul 2020 10:56:15 +0800
  4. Subject: [PATCH 018/107] target/riscv: rvv-1.0: check MSTATUS_VS when
  5. accessing vector csr registers
  6. If VS field is off, accessing vector csr registers should raise an
  7. illegal-instruction exception.
  8. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  9. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  10. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  11. ---
  12. target/riscv/csr.c | 5 +++++
  13. 1 file changed, 5 insertions(+)
  14. diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  15. index 5a0bc9a71f..e065b042df 100644
  16. --- a/target/riscv/csr.c
  17. +++ b/target/riscv/csr.c
  18. @@ -48,6 +48,11 @@ static int fs(CPURISCVState *env, int csrno)
  19. static int vs(CPURISCVState *env, int csrno)
  20. {
  21. if (env->misa & RVV) {
  22. +#if !defined(CONFIG_USER_ONLY)
  23. + if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
  24. + return -RISCV_EXCP_ILLEGAL_INST;
  25. + }
  26. +#endif
  27. return 0;
  28. }
  29. return -RISCV_EXCP_ILLEGAL_INST;
  30. --
  31. 2.33.1