From ea46dc1dd9050c1962ee8e887f14e022d84f4d0c Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 24 Jul 2020 10:56:15 +0800 Subject: [PATCH 018/107] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5a0bc9a71f..e065b042df 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -48,6 +48,11 @@ static int fs(CPURISCVState *env, int csrno) static int vs(CPURISCVState *env, int csrno) { if (env->misa & RVV) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif return 0; } return -RISCV_EXCP_ILLEGAL_INST; -- 2.33.1