0009-target-riscv-drop-vector-0.7.1-and-add-1.0-support.patch 2.3 KB

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  1. From b73aa71fc7af86158c95c3410146e7bb60f5d612 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 3 May 2021 17:41:19 +0800
  4. Subject: [PATCH 009/107] target/riscv: drop vector 0.7.1 and add 1.0 support
  5. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  6. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  7. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  8. ---
  9. target/riscv/cpu.c | 8 ++++----
  10. target/riscv/cpu.h | 2 +-
  11. 2 files changed, 5 insertions(+), 5 deletions(-)
  12. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  13. index 636d006f80..4a29175e20 100644
  14. --- a/target/riscv/cpu.c
  15. +++ b/target/riscv/cpu.c
  16. @@ -380,7 +380,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  17. CPURISCVState *env = &cpu->env;
  18. RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
  19. int priv_version = PRIV_VERSION_1_11_0;
  20. - int vext_version = VEXT_VERSION_0_07_1;
  21. + int vext_version = VEXT_VERSION_1_00_0;
  22. target_ulong target_misa = env->misa;
  23. Error *local_err = NULL;
  24. @@ -498,8 +498,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  25. return;
  26. }
  27. if (cpu->cfg.vext_spec) {
  28. - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
  29. - vext_version = VEXT_VERSION_0_07_1;
  30. + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
  31. + vext_version = VEXT_VERSION_1_00_0;
  32. } else {
  33. error_setg(errp,
  34. "Unsupported vector spec version '%s'",
  35. @@ -508,7 +508,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  36. }
  37. } else {
  38. qemu_log("vector version is not specified, "
  39. - "use the default value v0.7.1\n");
  40. + "use the default value v1.0\n");
  41. }
  42. set_vext_version(env, vext_version);
  43. }
  44. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  45. index 9b599f083d..dc4271be2a 100644
  46. --- a/target/riscv/cpu.h
  47. +++ b/target/riscv/cpu.h
  48. @@ -86,7 +86,7 @@ enum {
  49. #define PRIV_VERSION_1_10_0 0x00011000
  50. #define PRIV_VERSION_1_11_0 0x00011100
  51. -#define VEXT_VERSION_0_07_1 0x00000701
  52. +#define VEXT_VERSION_1_00_0 0x00010000
  53. enum {
  54. TRANSLATE_SUCCESS,
  55. --
  56. 2.33.1