From b73aa71fc7af86158c95c3410146e7bb60f5d612 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Mon, 3 May 2021 17:41:19 +0800 Subject: [PATCH 009/107] target/riscv: drop vector 0.7.1 and add 1.0 support Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 636d006f80..4a29175e20 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -380,7 +380,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = PRIV_VERSION_1_11_0; - int vext_version = VEXT_VERSION_0_07_1; + int vext_version = VEXT_VERSION_1_00_0; target_ulong target_misa = env->misa; Error *local_err = NULL; @@ -498,8 +498,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { - vext_version = VEXT_VERSION_0_07_1; + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version = VEXT_VERSION_1_00_0; } else { error_setg(errp, "Unsupported vector spec version '%s'", @@ -508,7 +508,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } else { qemu_log("vector version is not specified, " - "use the default value v0.7.1\n"); + "use the default value v1.0\n"); } set_vext_version(env, vext_version); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9b599f083d..dc4271be2a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,7 +86,7 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 -#define VEXT_VERSION_0_07_1 0x00000701 +#define VEXT_VERSION_1_00_0 0x00010000 enum { TRANSLATE_SUCCESS, -- 2.33.1