0005-target-riscv-fix-TB_FLAGS-bits-overlapping-bug-for-r.patch 2.2 KB

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  1. From e408ddf0f9da8e643c61d956c7a694192299f539 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Fri, 19 Feb 2021 16:48:29 +0800
  4. Subject: [PATCH 005/107] target/riscv: fix TB_FLAGS bits overlapping bug for
  5. rvv/rvh
  6. TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
  7. commit: c445593, but other TB_FLAGS bits for rvv and rvh were
  8. not shift as well so these bits may overlap with each other when
  9. rvv is enabled.
  10. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  11. ---
  12. target/riscv/cpu.h | 12 ++++++------
  13. target/riscv/translate.c | 2 +-
  14. 2 files changed, 7 insertions(+), 7 deletions(-)
  15. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  16. index 6362394204..9b599f083d 100644
  17. --- a/target/riscv/cpu.h
  18. +++ b/target/riscv/cpu.h
  19. @@ -379,7 +379,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
  20. target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
  21. void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
  22. -#define TB_FLAGS_MMU_MASK 7
  23. #define TB_FLAGS_PRIV_MMU_MASK 3
  24. #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
  25. #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
  26. @@ -388,12 +387,13 @@ typedef CPURISCVState CPUArchState;
  27. typedef RISCVCPU ArchCPU;
  28. #include "exec/cpu-all.h"
  29. -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
  30. -FIELD(TB_FLAGS, LMUL, 3, 2)
  31. -FIELD(TB_FLAGS, SEW, 5, 3)
  32. -FIELD(TB_FLAGS, VILL, 8, 1)
  33. +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
  34. +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
  35. +FIELD(TB_FLAGS, LMUL, 4, 2)
  36. +FIELD(TB_FLAGS, SEW, 6, 3)
  37. +FIELD(TB_FLAGS, VILL, 9, 1)
  38. /* Is a Hypervisor instruction load/store allowed? */
  39. -FIELD(TB_FLAGS, HLSX, 9, 1)
  40. +FIELD(TB_FLAGS, HLSX, 10, 1)
  41. bool riscv_cpu_is_32bit(CPURISCVState *env);
  42. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  43. index 045475a63b..b199bec4b4 100644
  44. --- a/target/riscv/translate.c
  45. +++ b/target/riscv/translate.c
  46. @@ -642,7 +642,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
  47. uint32_t tb_flags = ctx->base.tb->flags;
  48. ctx->pc_succ_insn = ctx->base.pc_first;
  49. - ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
  50. + ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
  51. ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
  52. ctx->priv_ver = env->priv_ver;
  53. #if !defined(CONFIG_USER_ONLY)
  54. --
  55. 2.33.1