12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364 |
- From e408ddf0f9da8e643c61d956c7a694192299f539 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Fri, 19 Feb 2021 16:48:29 +0800
- Subject: [PATCH 005/107] target/riscv: fix TB_FLAGS bits overlapping bug for
- rvv/rvh
- TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
- commit: c445593, but other TB_FLAGS bits for rvv and rvh were
- not shift as well so these bits may overlap with each other when
- rvv is enabled.
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- ---
- target/riscv/cpu.h | 12 ++++++------
- target/riscv/translate.c | 2 +-
- 2 files changed, 7 insertions(+), 7 deletions(-)
- diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
- index 6362394204..9b599f083d 100644
- --- a/target/riscv/cpu.h
- +++ b/target/riscv/cpu.h
- @@ -379,7 +379,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
- target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
- void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-
- -#define TB_FLAGS_MMU_MASK 7
- #define TB_FLAGS_PRIV_MMU_MASK 3
- #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
- #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
- @@ -388,12 +387,13 @@ typedef CPURISCVState CPUArchState;
- typedef RISCVCPU ArchCPU;
- #include "exec/cpu-all.h"
-
- -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
- -FIELD(TB_FLAGS, LMUL, 3, 2)
- -FIELD(TB_FLAGS, SEW, 5, 3)
- -FIELD(TB_FLAGS, VILL, 8, 1)
- +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
- +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
- +FIELD(TB_FLAGS, LMUL, 4, 2)
- +FIELD(TB_FLAGS, SEW, 6, 3)
- +FIELD(TB_FLAGS, VILL, 9, 1)
- /* Is a Hypervisor instruction load/store allowed? */
- -FIELD(TB_FLAGS, HLSX, 9, 1)
- +FIELD(TB_FLAGS, HLSX, 10, 1)
-
- bool riscv_cpu_is_32bit(CPURISCVState *env);
-
- diff --git a/target/riscv/translate.c b/target/riscv/translate.c
- index 045475a63b..b199bec4b4 100644
- --- a/target/riscv/translate.c
- +++ b/target/riscv/translate.c
- @@ -642,7 +642,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
- uint32_t tb_flags = ctx->base.tb->flags;
-
- ctx->pc_succ_insn = ctx->base.pc_first;
- - ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
- + ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
- ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
- ctx->priv_ver = env->priv_ver;
- #if !defined(CONFIG_USER_ONLY)
- --
- 2.33.1
|