0007-merge-Add-four-new-instruction-of-custom-CSRs.patch 2.8 KB

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  1. From 8e97f38276f8c6cec1c8a345ee61a9b3cecde8be Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Wed, 27 Oct 2021 23:14:48 -0700
  4. Subject: [PATCH 07/11] merge 'Add four new instruction of custom CSRs'
  5. ---
  6. include/opcode/riscv-opc.h | 15 +++++++++++++++
  7. opcodes/riscv-opc.c | 5 +++++
  8. 2 files changed, 20 insertions(+)
  9. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  10. index a62eada16a..566ab6e706 100644
  11. --- a/include/opcode/riscv-opc.h
  12. +++ b/include/opcode/riscv-opc.h
  13. @@ -267,6 +267,15 @@
  14. #define MASK_SFENCE_VMA 0xfe007fff
  15. #define MATCH_WFI 0x10500073
  16. #define MASK_WFI 0xffffffff
  17. +/* Custom CSRs instruction */
  18. +#define MATCH_CFLUSH_D_L1 0xfc000073
  19. +#define MASK_CFLUSH_D_L1 0xfff07fff
  20. +#define MATCH_CDISCARD_D_L1 0xfc200073
  21. +#define MASK_CDISCARD_D_L1 0xfff07fff
  22. +#define MATCH_CFLUSH_D_L2 0xfc400073
  23. +#define MASK_CFLUSH_D_L2 0xfff07fff
  24. +#define MATCH_CDISCARD_D_L2 0xfc600073
  25. +#define MASK_CDISCARD_D_L2 0xfff07fff
  26. #define MATCH_CSRRW 0x1073
  27. #define MASK_CSRRW 0x707f
  28. #define MATCH_CSRRS 0x2073
  29. @@ -3023,6 +3032,12 @@ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
  30. DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
  31. DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
  32. DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
  33. +/* Custom CSRs instruction */
  34. +DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
  35. +DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
  36. +DECLARE_INSN(cflush_d_l2, MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2)
  37. +DECLARE_INSN(cdiscard_d_l2, MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2)
  38. +/* end */
  39. DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
  40. DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
  41. DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
  42. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  43. index 98e7fa33f0..ea0fa1209c 100644
  44. --- a/opcodes/riscv-opc.c
  45. +++ b/opcodes/riscv-opc.c
  46. @@ -1179,6 +1179,11 @@ const struct riscv_opcode riscv_opcodes[] =
  47. {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
  48. /* Supervisor instructions. */
  49. +// Custom CSRs instructions
  50. +{"cflush.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 },
  51. +{"cdiscard.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 },
  52. +{"cflush.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2, match_opcode, 0 },
  53. +{"cdiscard.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2, match_opcode, 0 },
  54. {"csrr", 0, INSN_CLASS_ZICSR,"d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
  55. {"csrwi", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
  56. {"csrsi", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS },
  57. --
  58. 2.33.1