From 8e97f38276f8c6cec1c8a345ee61a9b3cecde8be Mon Sep 17 00:00:00 2001 From: "max.ma" Date: Wed, 27 Oct 2021 23:14:48 -0700 Subject: [PATCH 07/11] merge 'Add four new instruction of custom CSRs' --- include/opcode/riscv-opc.h | 15 +++++++++++++++ opcodes/riscv-opc.c | 5 +++++ 2 files changed, 20 insertions(+) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index a62eada16a..566ab6e706 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -267,6 +267,15 @@ #define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff +/* Custom CSRs instruction */ +#define MATCH_CFLUSH_D_L1 0xfc000073 +#define MASK_CFLUSH_D_L1 0xfff07fff +#define MATCH_CDISCARD_D_L1 0xfc200073 +#define MASK_CDISCARD_D_L1 0xfff07fff +#define MATCH_CFLUSH_D_L2 0xfc400073 +#define MASK_CFLUSH_D_L2 0xfff07fff +#define MATCH_CDISCARD_D_L2 0xfc600073 +#define MASK_CDISCARD_D_L2 0xfff07fff #define MATCH_CSRRW 0x1073 #define MASK_CSRRW 0x707f #define MATCH_CSRRS 0x2073 @@ -3023,6 +3032,12 @@ DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +/* Custom CSRs instruction */ +DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1) +DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1) +DECLARE_INSN(cflush_d_l2, MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2) +DECLARE_INSN(cdiscard_d_l2, MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2) +/* end */ DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 98e7fa33f0..ea0fa1209c 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1179,6 +1179,11 @@ const struct riscv_opcode riscv_opcodes[] = {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, /* Supervisor instructions. */ +// Custom CSRs instructions +{"cflush.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 }, +{"cdiscard.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 }, +{"cflush.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2, match_opcode, 0 }, +{"cdiscard.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2, match_opcode, 0 }, {"csrr", 0, INSN_CLASS_ZICSR,"d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrwi", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, {"csrsi", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS }, -- 2.33.1