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dubhe: gdb: Added patch files

Added 2 new gdb patch files to align with latest StarFive toolchain version.
Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
yang.lee 2 年 前
コミット
68f1a642b7

+ 2 - 0
recipes-devtools/gdb/gdb-10.1.inc

@@ -13,6 +13,8 @@ SRC_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${BRANCH};protoc
            file://0001-add-b-v-extension-support.patch \
            file://0002-RISC-V-Hypervisor-ext-drop-Privileged-Spec-1.9.1-and.patch \
            file://0003-RISC-V-Hypervisor-ext-support-Privileged-Spec-1.12.patch \
+           file://0004-add-pref-instruction.patch \
+           file://0005-Rename-some-assembler-mnemonic-for-rvv1.0.patch \
            file://0001-make-man-install-relative-to-DESTDIR.patch \
            file://0002-mips-linux-nat-Define-_ABIO32-if-not-defined.patch \
            file://0003-ppc-ptrace-Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch \

+ 70 - 0
recipes-devtools/gdb/gdb/0004-add-pref-instruction.patch

@@ -0,0 +1,70 @@
+From e4acc8143a553e7dbd039e76d42ee74e568546ae Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Sun, 20 Mar 2022 22:12:45 -0700
+Subject: [PATCH 4/5] add pref instruction
+
+---
+ gas/config/tc-riscv.c | 24 ++++++++++++------------
+ opcodes/riscv-opc.c   |  1 +
+ 2 files changed, 13 insertions(+), 12 deletions(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index cae279b647..672de3e33a 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -1380,7 +1380,7 @@ check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
+ 
+ static bfd_boolean check_pref_type(unsigned long type)
+ {
+-  if (type != 0 && type != 1 && type != 3 && type != 8)
++  if (type != 0 && type != 1 && type != 2 && type != 3 && type != 8)
+     as_bad (_("Improper pref type (%lu)"), type);
+ }
+ 
+@@ -2471,20 +2471,20 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	      s = expr_end;
+ 	      continue;
+ 
+-            case '#':
+-              my_getExpression (imm_expr, s);
+-              check_pref_type((unsigned long)imm_expr->X_add_number);
+-              INSERT_OPERAND (PREF_TYPE, *ip, imm_expr->X_add_number);
+-              imm_expr->X_op = O_absent;
+-              s = expr_end;
+-              continue;      
++      case '#':
++        my_getExpression (imm_expr, s);
++        check_pref_type((unsigned long)imm_expr->X_add_number);
++        INSERT_OPERAND (PREF_TYPE, *ip, imm_expr->X_add_number);
++        imm_expr->X_op = O_absent;
++        s = expr_end;
++        continue;      
+ 
+-            case '+':
++      case '+':
+ 	      my_getExpression (imm_expr, s);
+ 	      check_absolute_expr (ip, imm_expr, FALSE);
+-	      if ((unsigned long) imm_expr->X_add_number > 0xff)
+-		as_bad (_("Improper pref offset value (%lu)"),
+-			(unsigned long) imm_expr->X_add_number);
++	      if (imm_expr->X_add_number > 127 || imm_expr->X_add_number < -128)
++		as_bad (_("Improper pref offset value (%d)"),
++			(long) imm_expr->X_add_number);
+ 	      INSERT_OPERAND (PREF_OFFSET, *ip, imm_expr->X_add_number);
+ 	      imm_expr->X_op = O_absent;
+ 	      s = expr_end;
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index a7c697a938..1fd2fc4a9f 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -758,6 +758,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"snez",        0, INSN_CLASS_I,   "d,t",  MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
+ {"sltz",        0, INSN_CLASS_I,   "d,s",  MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
+ {"sgtz",        0, INSN_CLASS_I,   "d,t",  MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
++{"pref",        0, INSN_CLASS_I,   "#,+(s)",    MATCH_SLTI, MASK_PREF, match_opcode, INSN_ALIAS },
+ {"slti",        0, INSN_CLASS_I,   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
+ {"slt",         0, INSN_CLASS_I,   "d,s,t",  MATCH_SLT, MASK_SLT, match_opcode, 0 },
+ {"slt",         0, INSN_CLASS_I,   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
+-- 
+2.25.1
+

+ 38 - 0
recipes-devtools/gdb/gdb/0005-Rename-some-assembler-mnemonic-for-rvv1.0.patch

@@ -0,0 +1,38 @@
+From 019ac5d84c015cf692ae0cd486aced865c1c5d33 Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Fri, 8 Apr 2022 15:37:29 +0800
+Subject: [PATCH 5/5] Rename some assembler mnemonic for rvv1.0
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ opcodes/riscv-opc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 1fd2fc4a9f..1c71dff1a3 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -2045,14 +2045,17 @@ const struct riscv_opcode riscv_opcodes[] =
+ 
+ {"vmand.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
+ {"vmnand.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
+-{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
++{"vmandn.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
++{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, INSN_ALIAS},
+ {"vmxor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
+ {"vmor.mm",    0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
+ {"vmnor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
+-{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
++{"vmorn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
++{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, INSN_ALIAS},
+ {"vmxnor.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
+ 
+-{"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
++{"vcpop.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
++{"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, INSN_ALIAS},
+ {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
+ {"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
+ {"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
+-- 
+2.25.1
+