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+From c9ff2e904f6646338b50dc7b4b7b4116066780a4 Mon Sep 17 00:00:00 2001
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+From: "eric.tang" <eric.tang@starfivetech.com>
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+Date: Thu, 7 Apr 2022 14:42:34 +0800
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+Subject: [PATCH 16/18] Rename some assembler mnemonic for rvv1.0
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+
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+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
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+---
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+ gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d | 12 ++++++------
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+ gas/testsuite/gas/riscv/vector-insns.d | 8 ++++----
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+ opcodes/riscv-opc.c | 9 ++++++---
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+ 3 files changed, 16 insertions(+), 13 deletions(-)
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+
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+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
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+index 207a410c28..1e050f14ba 100644
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+--- a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
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++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
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+@@ -12,18 +12,18 @@ Disassembly of section .text:
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+ [ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t
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+ [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
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+ [ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
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+-[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
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++[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12
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+ [ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
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+-[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
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+-[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
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++[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12
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++[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0
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+ [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
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+ [ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
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+ [ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
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+ [ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t
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+ [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
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+ [ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
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+-[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
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++[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12
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+ [ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
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+-[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
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+-[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
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++[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12
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++[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0
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+ [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
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+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
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+index f09d139b83..92a61185ca 100644
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+--- a/gas/testsuite/gas/riscv/vector-insns.d
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++++ b/gas/testsuite/gas/riscv/vector-insns.d
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+@@ -1883,20 +1883,20 @@ Disassembly of section .text:
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+ [ ]+[0-9a-f]+:[ ]+76842257[ ]+vmnot.m[ ]+v4,v8
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+ [ ]+[0-9a-f]+:[ ]+66862257[ ]+vmand.mm[ ]+v4,v8,v12
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+ [ ]+[0-9a-f]+:[ ]+76862257[ ]+vmnand.mm[ ]+v4,v8,v12
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+-[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandnot.mm[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandn.mm[ ]+v4,v8,v12
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+ [ ]+[0-9a-f]+:[ ]+6e862257[ ]+vmxor.mm[ ]+v4,v8,v12
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+ [ ]+[0-9a-f]+:[ ]+6a862257[ ]+vmor.mm[ ]+v4,v8,v12
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+ [ ]+[0-9a-f]+:[ ]+7a862257[ ]+vmnor.mm[ ]+v4,v8,v12
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+-[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmornot.mm[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmorn.mm[ ]+v4,v8,v12
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+ [ ]+[0-9a-f]+:[ ]+7e862257[ ]+vmxnor.mm[ ]+v4,v8,v12
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+-[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vpopc.m[ ]+a0,v12
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++[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vcpop.m[ ]+a0,v12
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+ [ ]+[0-9a-f]+:[ ]+42c8a557[ ]+vfirst.m[ ]+a0,v12
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+ [ ]+[0-9a-f]+:[ ]+5280a257[ ]+vmsbf.m[ ]+v4,v8
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+ [ ]+[0-9a-f]+:[ ]+5281a257[ ]+vmsif.m[ ]+v4,v8
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+ [ ]+[0-9a-f]+:[ ]+52812257[ ]+vmsof.m[ ]+v4,v8
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+ [ ]+[0-9a-f]+:[ ]+52882257[ ]+viota.m[ ]+v4,v8
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+ [ ]+[0-9a-f]+:[ ]+5208a257[ ]+vid.v[ ]+v4
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+-[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vpopc.m[ ]+a0,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vcpop.m[ ]+a0,v12,v0.t
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+ [ ]+[0-9a-f]+:[ ]+40c8a557[ ]+vfirst.m[ ]+a0,v12,v0.t
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+ [ ]+[0-9a-f]+:[ ]+5080a257[ ]+vmsbf.m[ ]+v4,v8,v0.t
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+ [ ]+[0-9a-f]+:[ ]+5081a257[ ]+vmsif.m[ ]+v4,v8,v0.t
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+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
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+index f42a0db494..a2c782309c 100644
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+--- a/opcodes/riscv-opc.c
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++++ b/opcodes/riscv-opc.c
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+@@ -2043,14 +2043,17 @@ const struct riscv_opcode riscv_opcodes[] =
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+
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+ {"vmand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
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+ {"vmnand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
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+-{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
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++{"vmandn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0},
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++{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, INSN_ALIAS},
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+ {"vmxor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
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+ {"vmor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
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+ {"vmnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
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+-{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
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++{"vmorn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0},
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++{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, INSN_ALIAS},
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+ {"vmxnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
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+
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+-{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
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++{"vcpop.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, 0},
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++{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, INSN_ALIAS},
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+ {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
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+ {"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
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+ {"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
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+--
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+2.25.1
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+
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