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dubhe: binutils: Added patch files

Added 3 new binutils patch files to align with latest Starfive toolchain version.
Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
yang.lee 2 years ago
parent
commit
c56242b634

+ 98 - 0
recipes-devtools/binutils/binutils/0016-Rename-some-assembler-mnemonic-for-rvv1.0.patch

@@ -0,0 +1,98 @@
+From c9ff2e904f6646338b50dc7b4b7b4116066780a4 Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Thu, 7 Apr 2022 14:42:34 +0800
+Subject: [PATCH 16/18] Rename some assembler mnemonic for rvv1.0
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d | 12 ++++++------
+ gas/testsuite/gas/riscv/vector-insns.d         |  8 ++++----
+ opcodes/riscv-opc.c                            |  9 ++++++---
+ 3 files changed, 16 insertions(+), 13 deletions(-)
+
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+index 207a410c28..1e050f14ba 100644
+--- a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+@@ -12,18 +12,18 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+6cc64457[ 	]+vmslt.vx[ 	]+v8,v12,a2,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
+ [ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandn.mm[ 	]+v0,v0,v12
+ [ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
+-[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandn.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandn.mm[ 	]+v4,v4,v0
+ [ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
+ [ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
+ [ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
+ [ 	]+[0-9a-f]+:[ 	]+68c64457[ 	]+vmsltu.vx[ 	]+v8,v12,a2,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
+ [ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandn.mm[ 	]+v0,v0,v12
+ [ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
+-[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
+-[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandn.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandn.mm[ 	]+v4,v4,v0
+ [ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+index f09d139b83..92a61185ca 100644
+--- a/gas/testsuite/gas/riscv/vector-insns.d
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -1883,20 +1883,20 @@ Disassembly of section .text:
+ [ 	]+[0-9a-f]+:[ 	]+76842257[ 	]+vmnot.m[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+66862257[ 	]+vmand.mm[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+76862257[ 	]+vmnand.mm[ 	]+v4,v8,v12
+-[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+vmandnot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+vmandn.mm[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+6e862257[ 	]+vmxor.mm[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+6a862257[ 	]+vmor.mm[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+7a862257[ 	]+vmnor.mm[ 	]+v4,v8,v12
+-[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+vmornot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+vmorn.mm[ 	]+v4,v8,v12
+ [ 	]+[0-9a-f]+:[ 	]+7e862257[ 	]+vmxnor.mm[ 	]+v4,v8,v12
+-[ 	]+[0-9a-f]+:[ 	]+42c82557[ 	]+vpopc.m[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+42c82557[ 	]+vcpop.m[ 	]+a0,v12
+ [ 	]+[0-9a-f]+:[ 	]+42c8a557[ 	]+vfirst.m[ 	]+a0,v12
+ [ 	]+[0-9a-f]+:[ 	]+5280a257[ 	]+vmsbf.m[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+5281a257[ 	]+vmsif.m[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+52812257[ 	]+vmsof.m[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+52882257[ 	]+viota.m[ 	]+v4,v8
+ [ 	]+[0-9a-f]+:[ 	]+5208a257[ 	]+vid.v[ 	]+v4
+-[ 	]+[0-9a-f]+:[ 	]+40c82557[ 	]+vpopc.m[ 	]+a0,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+40c82557[ 	]+vcpop.m[ 	]+a0,v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+40c8a557[ 	]+vfirst.m[ 	]+a0,v12,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+5080a257[ 	]+vmsbf.m[ 	]+v4,v8,v0.t
+ [ 	]+[0-9a-f]+:[ 	]+5081a257[ 	]+vmsif.m[ 	]+v4,v8,v0.t
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index f42a0db494..a2c782309c 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -2043,14 +2043,17 @@ const struct riscv_opcode riscv_opcodes[] =
+ 
+ {"vmand.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
+ {"vmnand.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
+-{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
++{"vmandn.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0},
++{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, INSN_ALIAS},
+ {"vmxor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
+ {"vmor.mm",    0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
+ {"vmnor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
+-{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
++{"vmorn.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0},
++{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, INSN_ALIAS},
+ {"vmxnor.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
+ 
+-{"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
++{"vcpop.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, 0},
++{"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, INSN_ALIAS},
+ {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
+ {"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
+ {"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
+-- 
+2.25.1
+

+ 45 - 0
recipes-devtools/binutils/binutils/0017-add-miss-change-riscv-opc.h-for-rvv1.0.patch

@@ -0,0 +1,45 @@
+From 934316687cfbd86ae14e073dbdc9f4c88cf61f22 Mon Sep 17 00:00:00 2001
+From: "eric.tang" <eric.tang@starfivetech.com>
+Date: Fri, 15 Apr 2022 16:00:53 +0800
+Subject: [PATCH 17/18] add miss change riscv-opc.h for rvv1.0
+
+Signed-off-by: eric.tang <eric.tang@starfivetech.com>
+---
+ include/opcode/riscv-opc.h | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 8963216302..bc43e710f6 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -2531,21 +2531,21 @@ funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
+ #define MASK_VMANDMM     0xfe00707f
+ #define MATCH_VMNANDMM   0x76002057
+ #define MASK_VMNANDMM    0xfe00707f
+-#define MATCH_VMANDNOTMM 0x62002057
+-#define MASK_VMANDNOTMM  0xfe00707f
++#define MATCH_VMANDNMM   0x62002057
++#define MASK_VMANDNMM    0xfe00707f
+ #define MATCH_VMXORMM    0x6e002057
+ #define MASK_VMXORMM     0xfe00707f
+ #define MATCH_VMORMM     0x6a002057
+ #define MASK_VMORMM      0xfe00707f
+ #define MATCH_VMNORMM    0x7a002057
+ #define MASK_VMNORMM     0xfe00707f
+-#define MATCH_VMORNOTMM  0x72002057
+-#define MASK_VMORNOTMM   0xfe00707f
++#define MATCH_VMORNMM    0x72002057
++#define MASK_VMORNMM     0xfe00707f
+ #define MATCH_VMXNORMM   0x7e002057
+ #define MASK_VMXNORMM    0xfe00707f
+ 
+-#define MATCH_VPOPCM   0x40082057
+-#define MASK_VPOPCM    0xfc0ff07f
++#define MATCH_VCPOPM   0x40082057
++#define MASK_VCPOPM    0xfc0ff07f
+ #define MATCH_VFIRSTM  0x4008a057
+ #define MASK_VFIRSTM   0xfc0ff07f
+ 
+-- 
+2.25.1
+

+ 31 - 0
recipes-devtools/binutils/binutils/0018-ignore-zvl-and-zve-extension-for-now.patch

@@ -0,0 +1,31 @@
+From 9851835f05178608811784dec135c598146d9d67 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Mon, 18 Apr 2022 09:23:06 -0700
+Subject: [PATCH 18/18] ignore zvl and zve extension for now
+
+---
+ bfd/elfxx-riscv.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 24c045c46e..aa0a2ee537 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1714,6 +1714,14 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
+ 	  return NULL;
+ 	}
+ 
++	// we ignore zvl extension now.
++	  if (!strcasecmp ("zvl", subset) || !strcasecmp ("zve", subset))
++	{
++		while (*p != '\0' && *p != '_')
++			p++;
++		continue;
++	}
++
+       riscv_parse_add_subset (rps, subset,
+ 			      major_version,
+ 			      minor_version, false);
+-- 
+2.25.1
+

+ 3 - 0
recipes-devtools/binutils/binutils_2.37.bbappend

@@ -20,4 +20,7 @@ SRC_URI += "\
      file://0013-RISC-V-Hypervisor-ext-support-Privileged-Spec-1.12.patch \
      file://0014-fixed-a-compiled-error-when-enable-gdb.patch \
      file://0015-fix-incorrect-pref-address-range.patch \
+     file://0016-Rename-some-assembler-mnemonic-for-rvv1.0.patch \
+     file://0017-add-miss-change-riscv-opc.h-for-rvv1.0.patch \
+     file://0018-ignore-zvl-and-zve-extension-for-now.patch \
 "