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@@ -0,0 +1,105 @@
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+/** @file
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+ RISC-V Processor supervisor mode trap handler
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+
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+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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+
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+ SPDX-License-Identifier: BSD-2-Clause-Patent
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+
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+**/
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+
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+#include <Base.h>
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+#include "CpuExceptionHandlerLib.h"
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+
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+ .align 3
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+ .section .entry, "ax", %progbits
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+ .globl SupervisorModeTrap
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+SupervisorModeTrap:
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+ addi sp, sp, -SMODE_TRAP_REGS_SIZE
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+
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+ /* Save all general regisers except SP */
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+ sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
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+
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+ csrr t0, CSR_SSTATUS
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+ and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)
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+ sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
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+ csrr t0, CSR_SEPC
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+ sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
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+ csrr t0, CSR_SIE
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+ sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
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+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
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+
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+ sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
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+ sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
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+ sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
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+ sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
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+ sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
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+ sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
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+ sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
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+ sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
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+ sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
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+ sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
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+ sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
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+ sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
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+ sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
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+ sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
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+ sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
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+ sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
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+ sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
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+ sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
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+ sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
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+ sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
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+ sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
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+ sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
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+ sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
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+ sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
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+ sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
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+ sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
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+ sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
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+ sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
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+ sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
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+
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+ /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
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+ call RiscVSupervisorModeTrapHandler
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+
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+ /* Restore all general regisers except SP */
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+ ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
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+ ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
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+ ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
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+ ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
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+ ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
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+ ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
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+ ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
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+ ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
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+ ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
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+ ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
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+ ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
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+ ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
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+ ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
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+ ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
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+ ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
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+ ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
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+ ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
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+ ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
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+ ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
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+ ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
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+ ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
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+ ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
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+ ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
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+ ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
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+ ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
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+ ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
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+ ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
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+ ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
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+
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+ ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
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+ csrw CSR_SEPC, t0
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+ ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
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+ csrw CSR_SIE, t0
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+ csrr t0, CSR_SSTATUS
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+ ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
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+ or t0, t0, t1
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+ csrw CSR_SSTATUS, t0
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+ ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
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+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
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+ addi sp, sp, SMODE_TRAP_REGS_SIZE
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+ sret
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