SupervisorTrapHandler.S 3.8 KB

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  1. /** @file
  2. RISC-V Processor supervisor mode trap handler
  3. Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Base.h>
  7. #include "CpuExceptionHandlerLib.h"
  8. .align 3
  9. .section .entry, "ax", %progbits
  10. .globl SupervisorModeTrap
  11. SupervisorModeTrap:
  12. addi sp, sp, -SMODE_TRAP_REGS_SIZE
  13. /* Save all general regisers except SP */
  14. sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  15. csrr t0, CSR_SSTATUS
  16. and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)
  17. sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
  18. csrr t0, CSR_SEPC
  19. sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
  20. csrr t0, CSR_SIE
  21. sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
  22. ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  23. sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
  24. sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
  25. sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
  26. sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
  27. sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
  28. sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
  29. sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
  30. sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
  31. sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
  32. sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
  33. sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
  34. sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
  35. sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
  36. sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
  37. sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
  38. sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
  39. sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
  40. sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
  41. sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
  42. sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
  43. sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
  44. sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
  45. sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
  46. sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
  47. sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
  48. sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
  49. sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
  50. sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
  51. sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
  52. /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
  53. call RiscVSupervisorModeTrapHandler
  54. /* Restore all general regisers except SP */
  55. ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
  56. ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
  57. ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
  58. ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
  59. ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
  60. ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
  61. ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
  62. ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
  63. ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
  64. ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
  65. ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
  66. ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
  67. ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
  68. ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
  69. ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
  70. ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
  71. ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
  72. ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
  73. ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
  74. ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
  75. ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
  76. ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
  77. ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
  78. ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
  79. ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
  80. ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
  81. ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
  82. ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
  83. ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
  84. csrw CSR_SEPC, t0
  85. ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
  86. csrw CSR_SIE, t0
  87. csrr t0, CSR_SSTATUS
  88. ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
  89. or t0, t0, t1
  90. csrw CSR_SSTATUS, t0
  91. ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
  92. ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  93. addi sp, sp, SMODE_TRAP_REGS_SIZE
  94. sret