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+/** @file
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+* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
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+*
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+* This file lists all the processors available on the platform that the OSPM
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+* can enumerate and boot. It also lists all the interrupt controllers available
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+* in the system.
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+*
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+* Copyright (c) 2021, Arm Ltd. All rights reserved.
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+*
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+* SPDX-License-Identifier: BSD-2-Clause-Patent
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+*
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+* @par Specification Reference:
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+* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
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+**/
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+
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+#include <Library/AcpiLib.h>
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+#include <Library/ArmLib.h>
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+#include <Library/PcdLib.h>
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+#include <IndustryStandard/Acpi.h>
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+
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+#include "SgiAcpiHeader.h"
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+#include "SgiPlatform.h"
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+
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+#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
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+ FixedPcdGet32 (PcdCoreCount))
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+
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+// Multiple APIC Description Table
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+#pragma pack (1)
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+
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+typedef struct {
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+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
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+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
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+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
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+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
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+ EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3];
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+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
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+
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+#pragma pack ()
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+
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+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
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+ {
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+ ARM_ACPI_HEADER (
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+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
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+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
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+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
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+ ),
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+ // MADT specific fields
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+ 0, // LocalApicAddress
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+ 0 // Flags
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+ },
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+ {
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+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
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+ // PmuIrq, GicBase, GicVBase,
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+ // GicHBase, GsivId, GicRBase,
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+ // Efficiency)
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+ // Note: The GIC Structure of the primary CPU must be the first entry
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+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
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+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
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+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
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+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
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+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
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+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
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+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
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+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
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+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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+ 0, 0, 0, 25, 0, 0),
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+ },
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+ // GIC Distributor Entry
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+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
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+ 0, 3),
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+ // GIC Redistributor
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+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
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+ SIZE_16MB),
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+ // GIC ITS
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+ {
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+ EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
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+ EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
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+ EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
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+ },
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+};
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+
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+//
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+// Reference the table being generated to prevent the optimizer from removing
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+// the data structure from the executable
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+//
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+VOID* CONST ReferenceAcpiTable = &Madt;
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