Madt.aslc 3.9 KB

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  1. /** @file
  2. * Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
  3. *
  4. * This file lists all the processors available on the platform that the OSPM
  5. * can enumerate and boot. It also lists all the interrupt controllers available
  6. * in the system.
  7. *
  8. * Copyright (c) 2021, Arm Ltd. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: BSD-2-Clause-Patent
  11. *
  12. * @par Specification Reference:
  13. * - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
  14. **/
  15. #include <Library/AcpiLib.h>
  16. #include <Library/ArmLib.h>
  17. #include <Library/PcdLib.h>
  18. #include <IndustryStandard/Acpi.h>
  19. #include "SgiAcpiHeader.h"
  20. #include "SgiPlatform.h"
  21. #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
  22. FixedPcdGet32 (PcdCoreCount))
  23. // Multiple APIC Description Table
  24. #pragma pack (1)
  25. typedef struct {
  26. EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
  27. EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
  28. EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
  29. EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
  30. EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3];
  31. } EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
  32. #pragma pack ()
  33. STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
  34. {
  35. ARM_ACPI_HEADER (
  36. EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
  37. EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
  38. EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
  39. ),
  40. // MADT specific fields
  41. 0, // LocalApicAddress
  42. 0 // Flags
  43. },
  44. {
  45. // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
  46. // PmuIrq, GicBase, GicVBase,
  47. // GicHBase, GsivId, GicRBase,
  48. // Efficiency)
  49. // Note: The GIC Structure of the primary CPU must be the first entry
  50. // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
  51. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
  52. 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  53. 0, 0, 0, 25, 0, 0),
  54. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
  55. 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  56. 0, 0, 0, 25, 0, 0),
  57. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
  58. 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  59. 0, 0, 0, 25, 0, 0),
  60. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
  61. 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  62. 0, 0, 0, 25, 0, 0),
  63. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
  64. 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  65. 0, 0, 0, 25, 0, 0),
  66. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
  67. 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  68. 0, 0, 0, 25, 0, 0),
  69. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
  70. 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  71. 0, 0, 0, 25, 0, 0),
  72. EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
  73. 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
  74. 0, 0, 0, 25, 0, 0),
  75. },
  76. // GIC Distributor Entry
  77. EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
  78. 0, 3),
  79. // GIC Redistributor
  80. EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
  81. SIZE_16MB),
  82. // GIC ITS
  83. {
  84. EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
  85. EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
  86. EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
  87. },
  88. };
  89. //
  90. // Reference the table being generated to prevent the optimizer from removing
  91. // the data structure from the executable
  92. //
  93. VOID* CONST ReferenceAcpiTable = &Madt;