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@@ -6,7 +6,7 @@
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family, processor id, maximum operating frequency, and other information
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related to the processor.
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- Copyright (c) 2021, ARM Limited. All rights reserved.
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+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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@@ -27,7 +27,7 @@
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#define SOCKET_TYPE_BASE 3
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#define SOCKET_TYPE_NUM 1
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#define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
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-#define PROCESSOR_VERSION_NUM 9
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+#define PROCESSOR_VERSION_NUM 10
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#define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE + PROCESSOR_VERSION_NUM)
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#define TYPE4_STRINGS \
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"0x000\0" /* Part Number */ \
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@@ -42,6 +42,7 @@
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"Neoverse-V1\0" \
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"Neoverse-N2\0" \
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"Neoverse-N2\0" \
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+ "Neoverse-N2\0" \
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"000-0\0" /* Serial number */ \
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"783-3\0" \
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"786-1\0" \
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@@ -50,7 +51,8 @@
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"78A-1\0" \
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"78A-2\0" \
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"7B7-1\0" \
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- "7B6-1\0"
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+ "7B6-1\0" \
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+ "7B7-1\0"
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typedef enum {
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PartNumber = 1,
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@@ -188,6 +190,13 @@ InstallType4ProcessorInformation (
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mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount * FixedPcdGet32 (PcdChipCount);
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mArmRdSmbiosType4.Base.ThreadCount = CoreCount * FixedPcdGet32 (PcdChipCount);
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break;
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+ case RdN2Cfg2:
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+ mArmRdSmbiosType4.Base.CoreCount = CoreCount * FixedPcdGet32 (PcdChipCount);
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+ mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount * FixedPcdGet32 (PcdChipCount);
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+ mArmRdSmbiosType4.Base.ThreadCount = CoreCount * FixedPcdGet32 (PcdChipCount);
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+ mArmRdSmbiosType4.Base.MaxSpeed = 3200; // Frequency in MHz
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+ mArmRdSmbiosType4.Base.CurrentSpeed = 3200; // Frequency in MHz
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+ break;
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case RdE1Edge:
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mArmRdSmbiosType4.Base.CoreCount = CoreCount / NEOVERSE_E1_THREADS_PER_CORE;
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mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount / NEOVERSE_E1_THREADS_PER_CORE;
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